Winbond W83627HF User manual
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W83627HF/F
PRELIMINARY
Publication Release Date: November 2000
-1-Revision 1.0
GENERAL DESCRIPTION
The W83627HF and W83627F are evolving product from Winbond's most popular I/O family. They
feature a whole new interface, namely LPC (Low Pin Count) interface, which will be supported in the
next generation Intel chip-set. This interface as its name suggests is to provide an economical
implementation of I/O's interface with lower pin count and still maintains equivalent performance as its
ISA interface counterpart. Approximately 40 pin counts are saved in LPC I/O comparing to ISA
implementation. With this additional freedom, we can implement more devices on a single chip as
demonstrated in W83627F/HF's integration of Game Port and MIDI Port. It is fully transparent in terms of
software which means no BIOS or device driver update is needed except chip-specific configuration.
The disk drive adapter functions of W83627F/HF include a floppy disk drive controller compatible with the
industry standard 82077/ 765, data separator, write pre-compensation circuit, decode logic, data rate
selection, clock generator, drive interface control logic, and interrupt and DMA logic. The wide range of
functions integrated onto the W83627F/HF greatly reduces the number of components required for
interfacing with floppy disk drives. The W83627F/HF supports four 360K, 720K, 1.2M, 1.44M, or 2.88M
disk drives and data transfer rates of 250 Kb/s, 300 Kb/s, 500 Kb/s,1 Mb/s, and 2 Mb/s.
The W83627F/HF provides two high-speed serial communication ports (UARTs), one of which supports
serial Infrared communication. Each UART includes a 16-byte send/receive FIFO, a programmable
baud rate generator, complete modem control capability, and a processor interrupt system. Both
UARTs provide legacy speed with baud rate up to 115.2k bps and also advanced speed with baud rates
of 230k, 460k, or 921k bps which support higher speed modems. In addition, the W83627F/HF provides
IR functions: IrDA 1.0 (SIR for 1.152K bps) and TV remote IR (Consumer IR, supporting NEC, RC-5,
extended RC-5, and RECS-80 protocols).
The W83627F/HF supports one PC-compatible printer port (SPP), Bi-directional Printer port (BPP) and
also Enhanced Parallel Port (EPP) and Extended Capabilities Port (ECP). Through the printer port
interface pins, also available are: Extension FDD Mode and Extension 2FDD Mode allowing one or two
external floppy disk drives to be connected.
The configuration registers support mode selection, function enable/disable, and power down function
selection. Furthermore, the configurable PnP features are compatible with the plug-and-play feature
demand of Windows 95/98TM, which makes system resource allocation more efficient than ever.
The W83627F/HF provides functions that complies with ACPI (Advanced Configuration and Power
Interface), which includes support of legacy and ACPI power management through PME# or PSOUT#
function pins. For OnNow keyboard Wake-Up, OnNow mouse Wake-Up, and OnNow CIR Wake-Up.
The W83627F/HF also has auto power management to reduce the power consumption.
The keyboard controller is based on 8042 compatible instruction set with a 2K Byte programmable ROM
and a 256-Byte RAM bank. Keyboard BIOS firmware are available with optional AMIKEYTM -2, Phoenix
MultiKey/42TM, or customer code.
The W83627F/HF provides a set of flexible I/O control functions to the system designer through a set of
General Purpose I/O ports. These GPIO ports may serve as simple I/O or may be individually configured
to provide a predefined alternate function. General Purpose Port 1 is designed to be functional even in
power down mode (VCC is off).
W83627HF/F
PRELIMINARY
Publication Release Date: November 2000
-2-Revision 1.0
The W83627F/HF is made to fully comply with Microsoft PC98 and PC99 Hardware Design Guide.
Moreover W83627F/HF is made to meet the specification of PC98/PC99's requirement in the power
management: ACPI and DPM (Device Power Management).
The W83627F/HF contains a game port and a MIDI port. The game port is designed to support 2
joysticks and can be applied to all standard PC game control devices, They are very important for a
entertainment or consumer computer.
Only the W83627HF support hardware status monitoring for personal computers. It can be used to
monitor several critical hardware parameters of the system, including power supply voltages, fan speeds,
and temperatures, which are very important for a high-end computer system to work stably and properly.
FEATURES
General
•Meet LPC Spec. 1.0
•Support LDRQ#(LPC DMA), SERIRQ (serial IRQ)
•Include all the features of Winbond I/O W83977TF and W83977EF
•Integrate Hardware Monitor functions
•Compliant with Microsoft PC98/PC99 Hardware Design Guide
•Support DPM (Device Power Management), ACPI
•Programmable configuration settings
•Single 24 or 48 MHz clock input
FDC
•Compatible with IBM PC AT disk drive systems
•Variable write pre-compensation with track selectable capability
•Support vertical recording format
•DMA enable logic
•16-byte data FIFOs
•Support floppy disk drives and tape drives
•Detects all overrun and underrun conditions
•Built-in address mark detection circuit to simplify the read electronics
•FDD anti-virus functions with software write protect and FDD write enable signal (write data
signal was forced to be inactive)
•Support up to four 3.5-inch or 5.25-inch floppy disk drives
•Completely compatible with industry standard 82077
•360K/720K/1.2M/1.44M/2.88M format; 250K, 300K, 500K, 1M, 2M bps data transfer rate
•Support 3-mode FDD, and its Win95/98 driver
W83627HF/F
PRELIMINARY
Publication Release Date: November 2000
-3-Revision 1.0
UART
•Two high-speed 16550 compatible UARTs with 16-byte send/receive FIFOs
•MIDI compatible
•Fully programmable serial-interface characteristics:
--- 5, 6, 7 or 8-bit characters
--- Even, odd or no parity bit generation/detection
--- 1, 1.5 or 2 stop bits generation
•Internal diagnostic capabilities:
--- Loop-back controls for communications link fault isolation
--- Break, parity, overrun, framing error simulation
•Programmable baud generator allows division of 1.8461 MHz and 24 MHz by 1 to (216-1)
•Maximum baud rate up to 921k bps for 14.769 MHz and 1.5M bps for 24 MHz
Infrared
•Support IrDA version 1.0 SIR protocol with maximum baud rate up to 115.2K bps
•Support SHARP ASK-IR protocol with maximum baud rate up to 57,600 bps
•Support Consumer IR
Parallel Port
•Compatible with IBM parallel port
•Support PS/2 compatible bi-directional parallel port
•Support Enhanced Parallel Port (EPP) −Compatible with IEEE 1284 specification
•Support Extended Capabilities Port (ECP) −Compatible with IEEE 1284 specification
•Extension FDD mode supports disk drive B; and Extension 2FDD mode supports disk drives A
and B through parallel port
•Enhanced printer port back-drive current protection
Keyboard Controller
•8042 based with optional F/W from AMIKKEYTM-2, Phoenix MultiKey/42TM or customer code
with 2K bytes of programmable ROM, and 256 bytes of RAM
•Asynchronous Access to Two Data Registers and One status Register
•Software compatibility with the 8042
•Support PS/2 mouse
W83627HF/F
PRELIMINARY
Publication Release Date: November 2000
-4-Revision 1.0
•Support port 92
•Support both interrupt and polling modes
•Fast Gate A20 and Hardware Keyboard Reset
•8 Bit Timer/ Counter
•Support binary and BCD arithmetic
•6 MHz, 8 MHz, 12 MHz, or 16 MHz operating frequency
Game Port
•Support two separate Joysticks
•Support every Joystick two axis (X,Y) and two button (A,B) controllers
MIDI Port
•The baud rate is 31.25 Kbaud
•16-byte input FIFO
•16-byte output FIFO
General Purpose I/O Ports
•22 programmable general purpose I/O ports
•General purpose I/O ports can serve as simple I/O ports, interrupt steering inputs, watch dog
timer output, power LED output, infrared I/O pins, KBC control I/O pins, suspend LED output,
RSMRST# signal, PWROK signal, Beep output
•Functional in power down mode (GP1 only)
OnNow Functions
•Keyboard Wake-Up by programmable keys
•Mouse Wake-Up by programmable buttons
•CIR Wake-Up by programmable keys
•On Now Wake-Up from all of the ACPI sleeping states (S1-S5)
Hardware Monitor Functions ( Only for W83627HF)
•5 VID input pins for CPU Vcore identification
•3 thermal inputs from optionally remote thermistors or 2N3904 transistors or PentiumTM II
(Deschutes) thermal diode output
•7 positive voltage inputs (typical for +12V, -12V, +5V, -5V, +3.3V, VcoreA, VcoreB)
•2 intrinsic voltage monitoring (typical for Vbat, +5VSB)
W83627HF/F
PRELIMINARY
Publication Release Date: November 2000
-5-Revision 1.0
•3 fan speed monitoring inputs
•2 fan speed control
•Build in Case open detection circuit
•WATCHDOG comparison of all monitored values
•Programmable hysteresis and setting points for all monitored items
•Over temperature indicate output
•Automatic Power On voltage detection Beep
•Issue SMI#, IRQ, OVT# to activate system protection
•Intel LDCMTM / Acer ADMTM compatible
Package
•128-pin PQFP
W83627HF/F
PRELIMINARY
Publication Release Date: November 2000
-6-Revision 1.0
PIN CONFIGURATION FOR 627F
12345678 9 1
01
11
21
31
41
51
61
71
81
92
02
12
22
32
42
52
62
72
82
93
03
13
23
33
43
53
63
73
8
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
V
B
A
T
KDAT
KCLK
VSB
KBRST
A20GATE
KBLOCK#
RIA#
DCDA#
VSS
SOUTA
SINA
DTRA#
RTSA#
DSRA#
CTSA#
VCC
STB#
AFD#
ERR#
INIT#
SLIN#
PD0
PD1
PD2
PD3
40
39
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
VCC
GPSA2/GP17
GPSB2/GP16
GPY1/GP15
GPY2/P16/GP14
GPX2/P15/GP13
GPX1/P14/GP12
1
0
21
0
11
0
09
99
89
79
69
59
49
39
29
19
08
98
88
78
68
58
48
38
28
18
07
97
87
77
67
57
47
37
27
17
06
96
86
76
66
5
GPSB1/P13/GP11
VSS
GPSA1/P12/GP10
G
P
2
1
G
P
2
2
I
R
R
X
/
G
P
2
5
I
R
T
X
/
G
P
2
6
R
I
B
#
D
C
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B
#
V
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T
B
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I
N
B
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B
#
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0
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2
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1
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7
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W83627F
MSI/GP20
MSO/IRQIN0
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
N
CN
CN
CN
CN
C
N
CN
CN
CN
C
#
W83627HF/F
PRELIMINARY
Publication Release Date: November 2000
-7-Revision 1.0
PIN CONFIGURATION FOR 627HF
1234567891
01
11
21
31
41
51
61
71
81
92
02
12
22
32
42
52
62
72
82
93
03
13
23
33
43
53
63
73
8
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
V
B
A
T
KDAT
KCLK
VSB
KBRST
A20GATE
KBLOCK#
RIA#
DCDA#
VSS
SOUTA
SINA
DTRA#
RTSA#
DSRA#
CTSA#
VCC
STB#
AFD#
ERR#
INIT#
SLIN#
PD0
PD1
PD2
PD3
40
39
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
V
R
E
F
V
T
I
N
3
VTIN2
VTIN1
OVT#
VID4
VID3
VID2
VID1
VID0
VCC
GPSA2/GP17
GPSB2/GP16
GPY1/GP15
GPY2/P16/GP14
GPX2/P15/GP13
GPX1/P14/GP12
1
0
21
0
11
0
09
99
89
79
69
59
49
39
29
19
08
98
88
78
68
58
48
38
28
18
07
97
87
77
67
57
47
37
27
17
06
96
86
76
66
5
GPSB1/P13/GP11
VSS
GPSA1/P12/GP10
FANPWM1
FANPWM2
FANIO1
FANIO2
FANIO3
S
C
L
/
G
P
2
1
S
D
A
/
G
P
2
2
I
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R
X
/
G
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2
5
I
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T
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2
6
R
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B
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W83627HF
BEEP
MSI/GP20
MSO/IRQIN0
#
W83627HF/F
PRELIMINARY
Publication Release Date: November 2000
-8-Revision 1.0
1. PIN DESCRIPTION
Note: Please refer to Section 13.2 DC CHARACTERISTICS for details.
I/O8t -TTL level bi-directional pin with 8 mA source-sink capability
I/O12t -TTL level bi-directional pin with 12 mA source-sink capability
I/O12tp3 -3.3V TTL level bi-directional pin with 12 mA source-sink capability
I/OD12t -TTL level bi-directional pin open drain output with 12 mA sink capability
I/O24t -TTL level bi-directional pin with 24 mA source-sink capability
OUT12t -TTL level output pin with 12 mA source-sink capability
OUT12tp3 -3.3V TTL level output pin with 12 mA source-sink capability
OD12 -Open-drain output pin with 12 mA sink capability
OD24 -Open-drain output pin with 24 mA sink capability
INcs -CMOS level Schmitt-trigger input pin
INt-TTL level input pin
INtd -TTL level input pin with internal pull down resistor
INts -TTL level Schmitt-trigger input pin
INtsp3 -3.3V TTL level Schmitt-trigger input pin
1.1 LPC Interface
SYMBOL PIN I/O FUNCTION
CLKIN 18 INtSystem clock input. According to the input frequency 24MHz or
48MHz, it is selectable through register. Default is 24MHz input.
PME# 19 OD12 Generated PME event.
PCICLK 21 INtsp3 PCI clock input.
LDRQ# 22 O12tp3 Encoded DMA Request signal.
SERIRQ 23 I/OD12t Serial IRQ input/Output.
LAD[3:0] 24-27 I/O12tp3 These signal lines communicate address, control, and data
information over the LPC bus between a host and a peripheral.
LFRAME# 29 INtsp3 Indicates start of a new cycle or termination of a broken cycle.
LRESET# 30 INtsp3 Reset signal. It can connect to PCIRST# signal on the host.
SUSCLKIN 75 INts 32khz clock input , for CIR only.
W83627HF/F
PRELIMINARY
Publication Release Date: November 2000
-9-Revision 1.0
1.2 FDC Interface
SYMBOL PIN I/O FUNCTION
DRVDEN0 1OD24 Drive Density Select bit 0.
DRVDEN1 2OD12 Drive Density Select bit 1. (Default)
SMI#
(IRQIN1)
GP27
Int
I/OD12
System Management Interrupt
(Interrupt channel input. For C version only)
General purpose I/O port 3 bit 6.
INDEX# 3INcs This Schmitt-triggered input from the disk drive is active low when
the head is positioned over the beginning of a track marked by an
index hole. This input pin is pulled up internally by a 1 KΩ
resistor. The resistor can be disabled by bit 7 of L0-CRF0
(FIPURDWN).
MOA# 4OD24 Motor A On. When set to 0, this pin enables disk drive 0. This
is an open drain output.
DSB# 5OD24 Drive Select B. When set to 0, this pin enables disk drive B.
This is an open drain output.
DSA# 6OD24 Drive Select A. When set to 0, this pin enables disk drive A.
This is an open drain output.
MOB# 7OD24 Motor B On. When set to 0, this pin enables disk drive 1. This
is an open drain output.
DIR# 8OD24 Direction of the head step motor. An open drain output.
Logic 1 = outward motion
Logic 0 = inward motion
STEP# 9OD24 Step output pulses. This active low open drain output produces a
pulse to move the head to another track.
WD# 10 OD24 Write data. This logic low open drain writes pre-compensation
serial data to the selected FDD. An open drain output.
WE# 11 OD24 Write enable. An open drain output.
TRAK0# 13 INcs Track 0. This Schmitt-triggered input from the disk drive is active
low when the head is positioned over the outermost track. This
input pin is pulled up internally by a 1 KΩresistor. The resistor
can be disabled by bit 7 of L0-CRF0 (FIPURDWN).
WP# 14 INcs Write protected. This active low Schmitt input from the disk drive
indicates that the diskette is write-protected. This input pin is
pulled up internally by a 1 KΩresistor. The resistor can be
disabled by bit 7 of L0-CRF0 (FIPURDWN).
W83627HF/F
PRELIMINARY
Publication Release Date: November 2000
-10 -Revision 1.0
1.2 FDC Interface, continued
SYMBOL PIN I/O FUNCTION
RDATA# 15 INcs The read data input signal from the FDD. This input pin is pulled
up internally by a 1 KΩresistor. The resistor can be disabled by
bit 7 of L0-CRF0 (FIPURDWN).
HEAD# 16 OD24 Head select. This open drain output determines which disk drive
head is active.
Logic 1 = side 0
Logic 0 = side 1
DSKCHG# 17 INcs Diskette change. This signal is active low at power on and
whenever the diskette is removed. This input pin is pulled up
internally by a 1 KΩ resistor. The resistor can be disabled by bit
7 of L0-CRF0 (FIPURDWN).
1.3 Multi-Mode Parallel Port
The following pins have alternate functions, which are controlled by CR28 and L3-CRF0.
SYMBOL PIN I/O FUNCTION
SLCT 31 INt
PRINTER MODE:
An active high input on this pin indicates that the printer is
selected. Refer to the description of the parallel port for definition
of this pin in ECP and EPP mode.
OD12
EXTENSION FDD MODE: WE2#
This pin is for Extension FDD B; its function is the same as the
WE# pin of FDC.
OD12
EXTENSION 2FDD MODE: WE2#
This pin is for Extension FDD A and B; its function is the same as
the WE# pin of FDC.
PE
32 INt
PRINTER MODE:
An active high input on this pin indicates that the printer has
detected the end of the paper. Refer to the description of the
parallel port for the definition of this pin in ECP and EPP mode.
OD12
EXTENSION FDD MODE: WD2#
This pin is for Extension FDD B; its function is the same as the
WD# pin of FDC.
OD12 EXTENSION 2FDD MODE: WD2#
This pin is for Extension FDD A and B; its function is the same as
the WD# pin of FDC.
W83627HF/F
PRELIMINARY
Publication Release Date: November 2000
-11 -Revision 1.0
1.3 Multi-Mode Parallel Port, continued
SYMBOL PIN I/O FUNCTION
BUSY 33 INt
PRINTER MODE:
An active high input indicates that the printer is not ready to
receive data. Refer to the description of the parallel port for
definition of this pin in ECP and EPP mode.
OD12
EXTENSION FDD MODE: MOB2#
This pin is for Extension FDD B; its function is the same as the
MOB# pin of FDC.
OD12 EXTENSION 2FDD MODE: MOB2#
This pin is for Extension FDD A and B; its function is the same as
the MOB# pin of FDC.
ACK# 34 INt
OD12
OD12
PRINTER MODE: ACK#
An active low input on this pin indicates that the printer has
received data and is ready to accept more data. Refer tothe
description of the parallel port for the definition of this pin in ECP
and EPP mode.
EXTENSION FDD MODE: DSB2#
This pin is for the Extension FDD B; its functions is the same as
the DSB# pin of FDC.
EXTENSION 2FDD MODE: DSB2#
This pin is for Extension
FDD A and B; its function is the same as
the DSB# pin of FDC.
ERR#
45
INt
OD12
OD12
PRINTER MODE: ERR#
An active low input on this pin indicates that the printer has
encountered an error condition. Refer to the description of the
parallel port for the definition of this pin in ECP and EPP mode.
EXTENSION FDD MODE: HEAD2#
This pin is for Extension FDD B; its function is the same as the
HEAD#pin of FDC.
EXTENSION 2FDD MODE: HEAD2#
This pin is for Extension FDD A and B; its function is the sa
me as
the HEAD# pin of FDC.
This manual suits for next models
1
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