Wyse WY-100 User manual

~ WY-l 00 Display Terminal
Maintenance Manual
WYSE
I I I I

WY-100 DISPLAY TERMINAL
MAINTENANCE MANUAL
Wyse No. 88-009-01

PUBLICATION HISTORY
Date
10-82
03-84
Notes
InitiaL PubLication (PreLiminary)
Second Edition
RELATED PUBLICATIONS
Wyse No.
TitLe
88-003-01
WY-100 DispLay TerminaL Reference ManuaL
TRADEMARKS
WY-100 is a registered trademark of Wyse TechnoLogy.
COPYRIGHT NOTICE
Copyright @ 1982, 84, Wyse TechnoLogy. ALL Rights Reserved
WorLdwide. No part of this pubLication may be reproduced without
the express written permission of Wyse TechnoLogy.
Page ii

SAFETY WARNING
The terminaL power cabLe is suppLied with a safety ground. Do not
use the ter~inaL with an ungrounded outLet. Disconnect the power
cabLe from the terminaL before removing the top cover for any
reason.
Dangerous voLtages are present when the terminaL is on and may
remain after the power is off. Be extremeLy cautious. Do not work
aLone.
The internaL phosphor of the CRT <cathode ray tube) is toxic.
Wear safety goggLes and rubber gLoves whenever the CRT is
handLed. If the tube breaks, exposing skin or eyes to the phos-
phor, immediateLy rinse the affected area with coLd water and
consuLt a physician.
DISCLAIMER
No representation or warranties are made regarding the contents
of this document, and any impLied warranties or fitness for any
particuLar appLication are discLaimed.
The specification and information are subject to change without
prior notification. The right to revise this document without
obLigation to notify any person or organization is aLso reserved.
FCC WARNING: This equipment generates, uses, and can
radiate radio frequency energy, and if not instaLLed and
used in accordance with the instruction manuaL, may cause
interference to radio communications. It has been tested
and found to compLy with the Limits for a CLass A compu-
ting device pursuant to Subpart J of Part 1S of FCC RuLes,
which are designed to provide reasonabLe protection
against such interference when operated in a commerciaL
environment. Operation of this equipment in a residentiaL
area is LikeLy to cause interference, in which case the
user, at his own expense, wiLL be required to take what-
ever measures may be required to correct the interference.
Page iii

Page iv

SECTION I
1.0
2.0
2.1
2.2
2.3
3.0
3.1
3.1
.1
3.1. 2
3.1. 3
3.1. 4
3.2
3.2.1
3.2.2
3.2.3
3.2.4
3.3
3.3.1
SECTION II
1.0
2.0
2.1
2.2
2.3
3.0
3.1
3.2
3.3
SECTION III
1.0
2.0
3.0
4.0
4.1
4.2
4.3
4.4
5.0
TABLE OF CONTENTS
Page
LOGIC BOARD MODULE
I nt rodu c t; on •••••••••••••••••••••••••••••• ,a •• • 1-1
Operating Parameters ••••••••••••••••••••••••••• 1-1
Physical Dimensions .•..••..••.•.••......•...... 1-1
Power Supply Requirements •••••••••••••••••••••• 1-1
Connector Information •••••••••••••••••••••••••• 1-2
Functional Description ••••••••••••••••••••••••• 1-4
Microprocessor Controller •••••••••••••••••••••• 1-4
8039 M;crocomputer ••••.•••..••••••••••••.•••••• 1-4
DispLay Memory ••••••••••••••••••••••••••••••••• 1-7
Program Memory ••••••••••••••••••••••••••••••••• 1-7
Communications and Data Buffer ••••••••••••••••• 1-7
Video Circuits ......................•.......... 1-8
CRT ControLLers •••••••••••••••••••••••••••••••• 1-8
Dot Clock and Dot Serializer •••••••••••••••••• 1-10
Character ROM ••••••••••••••••••••••••••••••••• 1-10
Attributes Synchronization and Generation ••••• 1-11
Asynchronous Communications Interface ••••••••• 1-11
Baud Rate Generation •••••••••••••••••••••••••• 1-11
KEYBOARD MODULE
I nt roduc t; on ••.••••••.•••••.••••••••••••.•••••• 2-1
Operating Parameters ••••••••••••••••••••••••••• 2-1
PhysicaL Dimensions •.•••.••.•..•.•..•...•.•.•.. 2-1
Power Supply Requirements •••••••••••••••••••••• 2-1
Connector Information •••••••••••••••••••••••••• 2-1
Functional Description ••••••••••••••••••••••••• 2-1
Co L umn Decoder ••••••••••••••••••••••••••••••••• 2-3
Row Se lee tor ••••. ~ ••••••• ~ .••••••••••• ' •.•••••• • 2-3
Keyswitch Matrix ••••••••••••••••••••••••••••••• 2-3
MONITOR/POWER SUPPLY BOARD
Theory of Operation •••••••••••••••••••••••••••• 3-1
CRT ••••••••••••••••••••••••••••••.••••.•••••••• 3-2
Power Transformer •••••••••••••••••••••••••••••• 3-2
Monitor/Power Supply PCB ••••••••••••••••••••••• 3-2
+5 Vo l t Supp Ly ••••••••• ~ •••••••••••••••••••••• • 3-2
+13.5 Volt SuppLy •••••••••••••••••••••••••••••• 3-2
+12 Va l t Supp ly .........•...........•.......... 3-2
-12 Volt SuppLy •••••••••••••••••••••••••••••••• 3-3
Horizontal Deflection Circuits ••••••••••••••••• 3-3
contents 1

Page
SECTION III (continued)
6.0 Vertical Deflection Circuit •••••••••••••••••••• 3-3
7.0 Video AmpLifier •••••••••••••••••••••••••••••••• 3-3
7.1 Procedure for Disconnecting the
Monitor/Power Supply PCB ••••••••••••••••••••• 3-3
7.2 Procedure for Installing the Monitor/PS to
the TerminaL Base •••••••••••••••••••••••••••• 3-4
7.3 Procedure for Adjusting the Monitor/PS ••••••••• 3-5
7.4 Procedure for Display Geometry Adjustment •••••• 3-6
A
B
C
D
E
F
G
H
Figure 1
Figure
2
Figure
3
Figure
4
Figure
5
Figure
6
Figure
A-1
Figure
A-2
Figure B-1
Figure B-2
Figure C-1
Figure C-2
Figure D-1
contents 2
APPENDICES
PC ASSY Logic Board 99-004-01 REV E Part Number
and Description
Keyboard PCB 99-003-01 REV B Part Number and
Description
Monitor/PS PCB 99-002-01 REV T Part Number and
Description
Monitor/Power Supply PCB ASSY 99-002-02 REV N
Monitor/Power Supply PCB ASSY 99-002-03 REV C
Troubleshooting Flowcharts
Notice
Current Loop Option
ILLUSTRATIONS .
Logic Board Block Diagram •••••••••••••••••••••• 1-5
Microprocessor Timing •••••••••••••••••••••••••• 1-6
Dot V; dec T; m; ng ••••••••••••••••••••••••••••••• 1-9
Frame Video Timing ••••••••••••••••••••••••••••• 1-9
Keyboard Block Diagram ••••••••••••••••••••••••• 2-2
System Wiring Diagram •••••••••••••••••••••••••• 3-1
Logic Circuit Diagram •••••••••••••••••••••••••• A-3
Logic Board Loading Diagram •••••••••••••••• A-4/A-5
Keyboard Schematic ••••••••••••••••••••••••• B-2/B-3
Keyboard Loading Diagram ••••••••••••••••••• B-4/B-5
Monitor/Power Supply Board 99-002-01
Load; n9 D; ag ram ••••••••••••••••••••••••.••••• C-4
Monitor/Power Supply 99-002-01 Schematic
D; ag ram •••••••••••••••••••••••••••••••••••••• C-5
Monitor/Power Supply 99-002-02 Loading
D; ag ram •••••••••••••••••••••••••••••••••••••• D-4

Figure
D-2
Figure
E-1
Figure
E-2
Figure
F-1
Figure
F-2
Figure
F-3
Figure
F-4
Figure
F-S
Figure
F-6
Figure
F-7
Figure
F-8
Page
Monitor/Power Supply 99-002-02 Circuit
0; ag ram •••••••••••••••••••••••••••••••••••••• D-5
Monitor/Power Supply 99-002-03 Loading
D; ag ram •••••••••••••••••••••••••••••••••••••• E-5
Monitor/Power Supply 99-002-03 Schematic
D; ag ram •••••••••••••••••••••••••••••••••• E-6/ E-7
Block Diagram for Troubleshooting •••••••••••••• F-2
No Power Troubleshooting Flowchart, Part 1 ••••• F-3
No Power Troubleshooting Flowchart, Part 2 ••••• F-4
No Power Troubleshooting Flowchart, Part 3 ••••• F-S
No Video Troubleshooting Flowchart ••••••••••••• F-6
No Brightness Control Troubleshooting
FLowe hart •••••••••••••••••••••••••••••••••••• F-7
No Horizontal Drive Troubleshooting Flowchart •• F-8
No Vertical Drive Troubleshooting FLowchart •••• F-9
contents 3

contents 4

Section I
LOGIC BOARD MODULE
1.0 !~IRQ2Y£I!Q~
The Logic board moduLe performs aLL of the terminaL Logic
functions. These can be divided into four major parts: micropro-
cessor controLLer, video timing, communication interface, and
keyboard interface.
The microprocessor controLLer contains program ROM, dispLay and
buffer RAM, I/O, and address I/O seLections.
The video timing fetches data from the dispLay memory, converts
it into a dispLayabLe format, and generates aLL the necessary
timing signaLs for interfacing with the monitor/power supply
moduLe.
The
communication interface does seriaL-to-paraLLeL data format
conversion, provides baud rate generation and controL signals
for an RS-232 modem port and a serial printer port.
The keyboard interface is the link between the microprocessor
and the keyboard module. It aLLows the microprocessor to scan
the key matrix and the DIP switch settings on the keyboard.
2.1 PHYSICAL DIMENSIONS
Size (L x W x D) = 6" x 7" x 0.05" (15.38cm x 17.95cm x 0.13cm)
2.2 POWER SUPPLY REQUIREMENTS
DC
POWER:
Standard:
+5
VDC
+-
5%
@
1A
+12
VDC
+-
10%
@ 20
MA
-12
VDC
+-
10%
@
-0.001
MA
With 20 MA Current
+5
VDC
+-
5%
@ 1 A
+12
VDC
+-
10%
@ 50
MA
-12
VDC
+-
10%
@
-0.001
MA
With 2nd Page Option:
+ 5 VDC +- 5% @ 1.25 A
+12
VDC +- 10% @ 20 MA
-12 VDC +- 10% @ -0.001 MA
Loop Option:
+5 VOC +-
+12 VDC +-
-12 VDC +-
5% @ 1. 25 A
10% @ 50 MA
10% @ -0.001 MA
Logic board moduLe 1-1

AC POWER:
120 VAC @ 1 A
240
VAC @ 0.5 A
2.3 CONNECTOR INFORMATION
J1 = RS-232 MODEM PORT
Connector and
Pin Assignment
J 1-1
J1-2
J1-3
J1-4
J1-5
J1-6
J1-7
J1-8
J1-9
J1-10
J1-11
J1-12
J1-13
J1-14
J1-15
J1-16
J1-17
J1-18
J1-19
J1-20
J1-21
J1-22
J1-23
J1-24
J1-25
J2 = PRINTER PORT
Connector and
Pin Assignment
J2-1
J2-2
J2-3
J2-4
J2-5
J2-6
J2-7
J2-8
J2-9
J2-10
J2-11
J2-12
logic board module 1-2
Signal Name
GND (AA)
TXD (BA)
RXD (BB)
RTS (CA)
CTS (CB)
GND (AB)
oeD (CF)
+12 V
+12
VA
DINRET
DOUTRET
+12 VA
+12 V
DTR (CD)
Signal Name
PGND
PRXD
PGND
Description
ShieLd Ground
Transmit Data
Receive Data
Request to Send
CLear to Send
N/C
SignaL Ground
Data Carrier Detect
+12 VDC
20 MA Current Source
Data In Return
Data Out Return
20 MA Current Source
+12 VDC
N/C
N/C
Nle
N/C
Nle
Data TerminaL Ready
N/C
N/C
N/C
N/C
N/C
Description
ShieLd Ground
Nle
Transmit Data
N/C
N/C
N/C
SignaL Ground
N/C
N/C
N/C
N/C
N/C

Connector
and
Pin Assignment
Signal
Name
Description
J2-13
N/C
J2-14
N/C
J2-15
N/C
J2-16
N/C
J2-17
N/C
J2-18
N/C
J2-19
N/C
J2-20
PDTR
Data
TerminaL
Ready
J2-21
N/C
J2-22
NIC
J2-23
N/C
J2-24
N/C
J2-25
N/C
J3
=
KEYBOARD
INTERFACE
Connector and
Pin Assignment
Signal
Name
Description
J3-1
GND
ShieLd
Ground
J3-2
GND
SignaL
Ground
J3-3 +5
V +5
V
J3-4
SCAN
2
Scan
Line
2
J3-5
SCAN
1
Scan
Line
1
J3-6
SCAN a
Scan
Line a
J3-7
SCAN
3
Scan
Line
3
J3-8
SCAN
5
Scan
Line
5
J3-9
SCAN
6
Scan
Line
6
J3-10
SCAN 4
Scan Line
4
J3-11
KEY IN
Key
Input
J4
=
MONITORIPOWER
SUPPLY
INTERFACE
Connector and
Pin Assignment
Signal Name
Description
J 4-1
GND
ShieLd Ground
J4-2
GND
ShieLd
Ground
J4-3
+12 V +12
VDC
J4-4
-12 V
-12 VDC
J4-5
GND
SignaL
Ground
J4-6 +5
V
+5
VDC
J4-7
VDR
VerticaL
Synch
J4-8
GND
SignaL
Ground
J4-9
HDR
HorizontaL
Synch
J4-10
VIDEO
Video
SignaL
logic board module 1-3

The logic board is functionally divided into four parts: micro-
processor controller, video timing, communication interface, and
keyboard interface. See Figure 1 for a block diagram of the Logic
board.
3.1 MICROPROCESSOR CONTROLLER
The microprocessor controller consists of an 8039 microcomputer,
display and buffer memory, program memory, I/O and address
decoder, and support circuits that are connected directly to the
processor bus. (See Figure 2 for the timing diagrams and Figure
A-1 for the schematic).
3.1.1 8039 Microcomputer (98)
The 8039 microcomputer is an 8-bit microprocessor with 128 bytes
of internal RAM, two 8-bit I/O ports and an on-chip timer/
counter. It operates with a 10.376 MHz crystal (X1) which is
also used for baud rate generation in the data communication
interface section, resulting in a 1.48 microsecond instruction
time for one-cycle instructions.
The data bus lines DBO through DB7 are used for transfer
tions and data bytes bet wen 8039 (98) and program ROM
display and buffer RAM (4A-13A), CRT controllers (7B,
UART (48). They are multiplexed into address lines
instruction fetch and external memory access.
instruc-
(2B/3B),
88) and
during
I/O ports P10 through P16 are used for outputting row and column
addresses during keyboard scan. P17 is a beLL enable signal. It
is used by the microprocessor to sound the bell. It is also used
to provide an audio feedback effect to the keyboard by generating
a click when a key is pressed on the keypoard.
The second I/O port is used for I/O and memory devices
selection. The lower four lines P20-P23 also contains the four
high order bits of address A8-A11 during external memory access.
In device selection mode, P20 indicates whether the data byte on
the bus is a command or a data byte when accessing the CRT
controllers. In memory selection mode, P20 contains the address
bit A8. P21-P23 contain the address bits A9-A11, respectively;
and they are meaningful onLy in the memory seLection mode. P24
seLects either the display RAM (6A-13A) or buffer RAM (4A, SA)
for externaL RAM access. P2S enabLes the read/write operation of
the UART. P27 selects the output data from UART to be
transmitted through either the RS-232 modem port (J1) or the
serial printer port (J2).
ACE, PSIN, [0, and WR are output controL signaLs. AtE is a cLock
signaL used to Latch the address bits during a memory or I/O
cycLe. PSEN occurs onLy during a fetch to externaL program
logic board module 1-4

r-
o
to
-I,
n
CT
o
III
.,
a.
:3
o
a.
c
r-
eo
I
VI
CONTROL ~ 8276
LOGIC I--- __ ~ CRT CNTRLR
1
VIDEO
CIRCUITS
8276
- CRT CNTRLR
VIDEO
I----~" HRT
I----~' VRT
'---.------~
Figure 1. IOOIC OOAID BUXI< DIJGWol
2651
UART
I BUFFER J
~ 1
RS-232 MODEM PORT
PRINTER PORT

~
0
to
~.
n
cr
0
C»
.,
0-
;a
0
0-
r;:
~
It
~
I
0-
ALE
ooE-- 150ms~
I I
~<---2~0~0-m-s--~>-----------------------------------------------
~Oms~
--?> 70ms~
-.,/ h'"'""7~""7'jX ADDRESS XT!17 //lX~_---Iol.OPA..L.CTA-....I.IOi.IJ.JUT __ --JX DATA IN ~1ZT17/u
~
350 ms
~QID1:==~ _____________ 4_8Q __ ID~S _____________ ~~
~40ms-+- --+ 160 IDS +-
P23-P20 P2HiQX,------------A-ll---A-8--------------XP23 - P20
(EXT. MEMORY CYCLE)
~ 300 ms ~
480 ms

memory. ~. W[, are the read and write signaLs for strobing
data onto the bus.
TO is a feedback signaL from the keyboard indicating whether a
particuLar key is being depressed. It is an active high signaL.
T1 is a status signaL randomLy monitored by the processor.
this signal is inserted, it indicates that a character has
received by the UART (88) and is ready to be fetched by
processor.
When
been
the
!NT is an interrupt request signaL asserted by the CRT controLLer
(78) when screen refresh is required. The processor responds to
the interrupt request by initiating a DMA process which transfers
a bLock of 80 characters from the display RAM (6A-13A) to the CRT
controLlers (78, 88).
RESET input signal provides a means for initializing the
processor upon power-on. It is held at logic low for at least 30
milliseconds after the power supply is in tolerance.
3.1.2 DispLay Memory (6A-13A)
The dispLay memory consists of 2K (4K) bytes of memory, or
4 (8) 2114 1K x 4 static memory components (6A-13A) external to
the processor. It is accessed by the processor to refresh the
screen and to update the text. The lower address lines are
Latched by an 8-bit Latch (3A) on the rising edge of ALE during
each external memory cycLe. A two-to-four decoder (58) is used
to decode the upper address Lines A10 and A11 into a 1K byte
memory bLock, and to select a pair of 2114 memory components.
3.1.3 Program Memory (28/38)
The terminal program is stored in a 4K x 8 2732 (28) EPROM. It
contains the display driver, the communication interface firm-
ware and the keyboard scanner. AlternativeLy, the 2732 can be
substituted with two 2716s (28, 38) by slightly modifying the
control line VPP/A11 and address line CEo
3.1.4 Communications and Data 8uffer
A 1K byte buffer consists of two 2114 static memory chips (4A,
5A) used as a buffer RAM area for storing characters received
from communication ports, soft function key codes and descrip-
tions on the screen. This 1K memory address space overlaps the
4K display RAM area. The I/O port P24 of 8039 is used to select
either the buffer RAM or display RAM access.
Logic board module 1-7

3.2 VIDEO CIRCUITS
The
video circuits can be divided into four parts: CRT
controLLers; cLock, characters cLock, and dot seriaLizer; char-
acter ROM; and attribute synchronization and generation. For
detaiLed video timing information see Figures 3 and 4.
3.2.1 CRT Controllers (78, 88)
Two InteL 8276 CRT controLLers are used to generate the scan Line
count, the character count, the horizontaL and verticaL timing
signaLs, and the visuaL attributes. The 8276 CRT controLLer
contains two 80-character on-chip row buffers: one is used as a
circuLating row buffer during each scan Line dispLay; the other
is used to store prefetched characters for the next dispLay
row.
The RD input signaL is never used by the 8039 processor and is
permanentLy tied to Logic high.
The C7P input signaL when used in conjunction with CS
whether the input information on DBO-DB7 is a command
byte.
indicates
or data
The data Lines DBO-DB7 are Linked to the 8039 processor bus for
transferring program parameters and dispLay characters from tWe
processor to the two CRT controLLers.
The CS signaL is asserted when the 8276s are seLected by the
processor for setting timing parameters. It is aLso used to
reset the J-K fLipfLop (SE) after each character row refresh.
BRDY is an interrupt request signaL asserted by the 8276 (7B) at
the beginning of each row refresh. The processor responds to
BRDY by initiating a DMA process which transfers a bLock of 80
characters from the dispLay RAM to the"row buffers inside of the
two 8276s. The BRDY signaL, when asserted, causes the foLLowing
CPU read operations to become write operations to the 8276s.
The Wi signal is derived from two signaL sources: the write
signaL from the CPU when the screen is not being refreshed, or
the read signaL from the CPU when the screen is being refreshed.
It is a controL signaL used either to strobe data into the row
buffers or to set the command/data parameters.
The ASCII codes of the row buffers are outputted on signaL Lines
CCO-CC6. SignaLs ceo through CC6 and the scan Line count LCO-LC3
index into the character ROM, and convert an ASCII code into its
corresponding dot pattern to be dispLayed on the screen.
BS is the buffer seLection signaL. It enabLes the current write
operation to access the character row buffers inside the
8276s. GPAO, GPA1, VSP, RVV, and HLGT are the visuaL attributes
vaLid during each character dispLay cycLe. They are used for
logic board module 1-8

~1l36~
DOT CLOCK
~ 541.136 ms '>
CHARACTER -E-- 270.568 ms --71 I~ ______ ~
CLOCK
(CCLK) ~150 ms~ .--- ________ -..
CHARACTER MW~ VALID ~h0< __________ _
CODE
(CCO-CC6) < 350 ms >
CHARACTER /////L////////////77/////////xy"'-AL----ID)0/# ///~ff// ~# ff #2>C
ROM
< 275 ms ~
ATTRIBUTE i/7//'//Z//7//7/dA ____ ""- _- _-......:..:-VA:U:D ====)@77§///#//;0( _______ _
CODES
Figure 3. oor VIDED T:IMJN:;
CHARACTER
CLOCK
r-
(CCLK)
~
54.1125 ms
0
HDR 60 Hz
~
fl ms
=?j
!S
IC
......
n
+--
16.6666 ms
f"r
0-
VDR 60 Hz
~
J.J
0
~
1.1?f35 ms
Q)
..,
Q.
~
54.1125 ms
~
:3 f"t"
0
HDR 50 Hz
It ms
~
,,~
Q.
~
c 19.9999
ms
~
r-
-+--
t"r
tD
VDR 50 Hz
14.rP57 ms
7f
,,~
+--
.....
I
-0
Figure 4. FRAME vm:m TIMJH;

blanking, underlining, video suppression, reverse video, and
highlighting display characters.
HRTC and VRTC are the horizontal and vertical drive signals. They
are used by the monitor/power supply moduLe to controL the sweep
of the Light beam on the screen. The HRTC pulse is triggered by
a 555
one-shot (18) which generates an approximate blanking time
of 24 microseconds independent of AC operating frequency. The
HRTC signal has a period of 54.1125 ms. The VRTC duty-cycle is
programmed by the CPU. It has a blanking time of 1.19035 ms when
the screen is refreshed at 60 Hz rate, and 14.2857 ms when the
screen is refreshed at 50 Hz rate.
The CCCK is a 50% duty-cycLe, 1.848 MHz character clock used by
the 8276s and the synchronizer (3D). It is the basic timing
signal for synchronizing the internal circuitry of the two 8276s.
3.2.2 Dot Clock and Dot Serializer
The character dot timing is generated by an oscilLator circuit
using an 18.48 MHz crystal. This 18.48 MHz, 50% duty-cycLe
signaL is the clock source for both the dot seriaLizer (70) and
the character clock generator (90). The character clock generator
(90) divides the dot cLock by 10 since each character celL is 10
dots wide. It aLso provides the appropriate timing signal to
reload the dot serializer (70) with the next character pattern~
and to reinitiaLize itself.
The dot serializer (70) converts an 8-bit pattern of a character
matrix from the character ROM (80) into 10 seriaL dots to be
displayed on each scan Line. The two extra dots are generated by
repeating the first dot twice after the eighth dot is displayed.
This scheme aLlows horizontal Lines of two adjacent graphic
characters to be connected.
3.2.3 Character ROM (8D)
The
basic character celL is a 10-dot by 11-scan Line rectangle.
Within the cell is the 7 x 8 character, surrounded by one dot on
the left side for horizontaL spacing, two scan Lines beLow for
Lower case descending, and one scan Line above for row-to-row
spacing.
ALL dots and aLL character scan Lines in the matrix are used for
graphics characters. Each character scan Line segment is stored
in ROM as an 8-bit word. Seven of the bits (01 through 07) are
used for the character dots, and the eighth (DO) is used to
specify dot-extension for graphic characters. If a graphic char-
acter scan is extended, two dots are jammed into the dot seriaL-
izer (70) after the first eight bits are Loaded. This results in
a continuous Line across the entire scan Line of the character
ceLL.
logic board module 1-10

3.2.4 Attributes Synchronization and Generation
The attributes associated with each character are vaLid during
the character cycLe. They must be latched by an 8-bit Latch (6B)
however, because the character ROM access time exceeds one
character cycLe time and the outputs of the character ROM must be
synchronized with the attribute signaLs.
The output signaL ceo of the second 8276 (8B) is OR'd with the
haLf-intensity attribute from the first 8276 (7B). This signaL
is used as a protect character mark for each ASCII code stored in
the dispLay RAM. This resuLts in every protected character being
dispLayed as dim.
3.3 ASYNCHRONOUS COMMUNICATIONS INTERFACE
The terminaL data communcations are centered around the 2651
UART (4B). This chip performs the seriaL-to-paraLLeL data con-
version for RS-232 data communication, as weLL as detecting
parity, framing, and overrun errors. In addition, signaLs RTS,
CfS, orR, DSR, DCD are handLed by the 2651.
Buffers 1488 (2E) and 1489A (1E) provide the necessary LeveL
conversions for the RS-232 data communications. The 470pf capa-
citors used on each driver and receiver are used for sLew rate
controL, and aLLow the datacomm Lines to be driven to 9600 baud.
3.3.1 Baud Rate Generation
The baud rates are generated by the 2651 UART from a 10.1376 MHz
cLock source. The programmabLe baud rates supported by the 2651
and their respective error rates are as foLLows:
Baud
Rate
50
70
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
Percent Error
0.016
0.253
Note: The percent error does not include the crystal error.
logic board module 1-11