Xilinx LogiCORE IP v1.02a User manual

LogiCORE IP I/O
Module v1.02a
Product Guide
PG052 October 16, 2012

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PG052 October 16, 2012
Table of Contents
SECTION I: SUMMARY
IP Facts
Chapter 1: Overview
Feature Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Licensing and Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chapter 2: Product Specification
Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Resource Utilization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Port Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Register Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Chapter 3: Designing with the Core
General Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
LMB Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Protocol Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
SECTION II: VIVADO DESIGN SUITE
Chapter 4: Customizing and Generating the Core
GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Parameter Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Chapter 5: Constraining the Core
Required Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Device, Package, and Speed Grade Selections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

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Clock Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Clock Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Clock Placement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Banking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Transceiver Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
I/O Standard and Placement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
SECTION III: ISE DESIGN SUITE
Chapter 6: Customizing and Generating the Core
GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Parameter Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Chapter 7: Constraining the Core
Clock Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
SECTION IV: APPENDICES
Appendix A: Migrating
Appendix B: Debugging
Solution Centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Appendix C: Application Software Development
Device Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Appendix D: Additional Resources
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Notice of Disclaimer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

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SECTION I: SUMMARY
IP Facts
Overview
Product Specification
Designing with the Core

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Introduction
The LogiCORE™ I/O Module is a highly
integrated and light-weight implementation of
a standard set of peripherals.
The I/O Module is a standalone version of the
tightly coupled I/O Module included in the
LogiCORE MicroBlaze™ Micro Controller
System (MCS). Using the I/O Module, a system
equivalent to MicroBlaze MCS can be design
using the ISE® Design Suite Embedded Edition
or the Vivado™ Design Suite.
The I/O Module connects to MicroBlaze
through the lmb_v10 bus.
Features
• LMB v1.0 bus interfaces to communicate
with MicroBlaze
•I/OBus
• Interrupt Controller with fast interrupt
mode support
•UART
•FixedIntervalTimers
• Programmable Interval Timers
• General Purpose Inputs
• General Purpose Outputs
IP Facts
LogiCORE IP Facts Table
Core Specifics
Supported
Device
Family(1)
Zynq™-7000(2), Virtex-7, Kintex™-7, Artix™-7,
Virtex-6, Spartan-6, Virtex-5, Virtex®-4,
Spartan®-3
Supported
User Interfaces
Local Memory Bus (LMB), Dynamic
Reconfiguration Port (DRP)
Resources See Table 2-2.
Provided with Core
Design Files ISE: VHDL
Vivado: RTL
Example
Design Not Provided
Test Ben ch Not Provided
Constraints
File Not Provided
Simulation
Model VHDL Behavioral
Supported
S/W Driver(3) Standalone
Tested Design Flows
Design Entry Xilinx Platform Studio (XPS)
Simulation Mentor Graphics ModelSim
Synthesis Xilinx Synthesis Technology (XST)
Vivado Synthesis(5)
Support
Provided by Xilinx @ www.xilinx.com/support
Notes:
1. For a complete list of supported derivative devices, see the
Embedded Edition Derivative Device Support.
2. Supported in ISE Design Suite implementations only.
3. Standalone driver details can be found in the EDK or SDK
directory (<install_directory>/doc/usenglish/
xilinx_drivers.htm). Linux OS and driver support information is
available from //wiki.xilinx.com.
4. For the supported versions of the tools, see the Xilinx Design
Tools: Release Notes Guide.
5. Supports only 7 series devices.

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Chapter 1
Overview
The I/O Module is a light-weight implementation of a set of standard I/O functions
commonly used in a MicroBlaze™ processor sub-system. The input/output signals of the I/O
Module are shown in Figure 1-1. The detailed list of signals are listed and described in
Tab le 2-3. See the description of LMB Signals in the MicroBlaze Bus Interfaces chapter in the
MicroBlaze Processor Reference Guide [Ref 1].
.
In a MicroBlaze system the I/O Module would typically be connected according to
Figure 1-2.
X-Ref Target - Figure 1-1
Figure 1-1: I/O Module Block Diagram
I/O Module
LMB
UART_Tx_IO
UART_Interrupt
FITx_Interrupt
PITx_Interrupt
GPOx_IO
INTC_Interrupt
INTC_IRQ
IO_Addr_Strobe
IO_Read_Strobe
IO_Write_Strobe
IO_Address
IO_Byte_Enable
IO_Write_Data
IO_Read_Data
IO_Ready
PITx_Toggle
INTC_Interrupt_Address
INTC_Interrupt_Ack
Interrupt
GPIx_IO
UART_Rx_IO
PITx_Enable FITx_Toggle
IO_Bus
GPIx_Interrupt

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Feature Summary
Feature Summary
I/O Bus
The I/O Bus provides a simple bus for accessing to external modules. The I/O Bus is mapped
in the MicroBlaze memory space, with the I/O Bus address directly reflecting the byte
address used by MicroBlaze Load/Store instructions. I/O Bus data is 32-bit wide, with byte
enables to write byte and half-word data.
The I/O Bus is fully compatible with the Xilinx Dynamic Reconfiguration Port (DRP).
UART
The Universal Asynchronous Receiver Transmitter (UART) interface provides the controller
interface for asynchronous serial data transfers. Features supported include:
• One transmit and one receive channel (full duplex)
• Configurable number of data bits in a character (5-8)
• Configurable parity bit (odd or even)
• Configurable and programmable baud rate
X-Ref Target - Figure 1-2
Figure 1-2: Typical MicroBlaze System
ILMB
MicroBlaze
LMB_v10
LMB BRAM
Interface Controller
BRAM Block
(Dual Port)
DLMB
LMB_v10
LMB BRAM
Interface Controller
I/O Module

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Licensing and Ordering Information
Fixed Interval Timer, FIT
The Fixed Interval Timer generates a strobe signal at fixed intervals. The Fixed Interval
Timer asserts the output signal and generates an interrupt according to the selected
parameter values.
Programmable Interval Timer, PIT
The Programmable Interval Timer, PIT, has a configurable width from 1 to 32. The PIT
operation and period are controlled by software. An interrupt can be generated when the
timer lapses.
General Purpose Output, GPO
The General Purpose Output, GPO, drives I/O Module GPO output signals defined by the
value of the corresponding GPO register, programmable from software. The width and
initial value are defined by parameters.
General Purpose Input, GPI
The General Purpose Input, GPI, makes it possible for software to sample the value of the
I/O Module GPI input signals by reading the GPI register. The width and whether to
generate an interrupt are defined by parameters.
Interrupt Controller INTC
The Interrupt Controller handles both I/O module internal interrupt events and external
ones. The internal interrupt events originate from the UART, the Fixed Interval Timers, the
Programmable Interval Timers, or the General Purpose Inputs.
Licensing and Ordering Information
This Xilinx LogiCORE IP module is provided at no additional cost with the Xilinx Vivado
Design Suite and ISE Design Suite Embedded Edition tools under the terms of the Xilinx End
User License.
Information about this and other Xilinx LogiCORE IP modules is available at the Xilinx
Intellectual Property page. For information on pricing and availability of other Xilinx
LogiCORE IP modules and tools, contact your local Xilinx sales representative.

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Chapter 2
Product Specification
Standards
The I/O Bus interface provided by the I/O Module is fully compatible with the Xilinx
Dynamic Reconfiguration Port (DRP). For a detailed description of the DRP, see the 7 Series
FPGAs Configuration User Guide [Ref 2].
Performance
The frequency and latency of the I/O Module are optimized for use together with
MicroBlaze™. This means that the frequency targets are aligned to MicroBlaze targets as
well as the access latency optimized for MicroBlaze data access.
Maximum Frequencies
The following are clock frequencies for the target families. The maximum achievable clock
frequency can vary. The maximum achievable clock frequency and all resource counts can
be affected by the used tool flow, other tool options, additional logic in the FPGA, using
different versions of Xilinx tools, and other factors.
Latency
Data read from I/O Module registers is available two clock cycles after the address strobe is
asserted.
Table 2-1: Maximum Frequencies
Architecture Speed grade Max Frequency
Virtex-7 -3 320
Kintex™-7 -3 320
Artix™-7 -3 225
Virtex®-6 -3 300
Spartan®-6 -4 195

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Resource Utilization
Data write to I/O Module registers is performed the clock cycle after the address strobe is
asserted.
Data accesses to peripherals connected on the I/O Bus take three clock cycles plus the
number of wait states introduced by the accessed peripheral.
Throughput
The maximum throughput when using the I/O Bus is one read or write access every three
clock cycles.
Resource Utilization
Because the MicroBlaze MCS is a module that is used together with other parts of the
design in the FPGA, the utilization and timing numbers reported in this section are just
estimates, and the actual utilization of FPGA resources and timing of the MicroBlaze MCS
design will vary from the results reported here. All parameters not given in the table below
have their default values.
Table 2-2: Performance and Resource Utilization Benchmarks on Virtex-6 (xc6vlx240t-1-ff1156)
Parameter Values (other parameters at default value) Device Resources
C_USE_UART_RX
C_USE_UART_TX
C_INTC_USE_EXT_INTR
C_INTC_INTR_SIZE
C_USE_FIT1
C_FIT1_No_CLOCKS
C_USE_PIT1
C_PIT1_SIZE
C_USE_GPI1
C_GPI1_SIZE
C_USE_GPO1
C_GPO1_SIZE
C_USE_IO_BUS
C_INTC_HAS_FAST
LUTs Flip-Flops
11000 0 000000 00 40 75
11150 0 000000 00 69 110
11150 0 000000 01 118 173
1 1 1 5 1 65000 0 0 0 0 0 0 0 0 75 122
1 1 1 5 1 65000 1 32 0 0 0 0 0 0 121 216
1115165000132132132 0 0 121 280
1115165000132132132 1 0 119 361