ZiLOG System 8000 Quick user guide

In affiliate of E'K0N Corporation
System 8000™ Central PrG~essing Unil
liardwareBf!~eleDCe ···Manaal
II •
••
•
- ~ •. ~
•
••
,

03-3200-01
September, 1982
Copyright 1982 by Zilog, Inc. All rights reserved. No part of this publication may be
reproduced, stored in aretrieval system,
or transmitted, in any form or by any
means, electronic, mechanical, photocopying, recording, or otherwise, without the
prior written permission
of Zilog.
The information in this publication
is subject to change without notice.
Zilog assumes no responsibility for the use
of any circuitry other than circuitry
embodied in aZilog product. No other circuit patent licenses are implied.

PRELIMINARY MANUSCRIPT RELEASE
SYSTEM 8000 CENTRAL PROCESSING UNIT (CPU)
HARDWARE REFERENCE MANUAL
03-3200-01
PRELIMINARY VERSION
The information contained in
this draft may undergo
changes, both in content and
organization, before arriving
at its final form.

CPU
i i
Zilog
Zilog
CPU
ii

CPU
Zilog
Preface
CPU
..
The System 8000 CPU Hardware Reference Manual descl;ibes the
processor board cap?bilities and application within the Sys-
tem 8000. Logic Diagrams are provided within the Appendix
and referenced to the circuit descriptions in Section 4.
The board is factory prepared, installed and tested in the
users system before shipment and should require no changes.
Any field change should be by qualified field service per-
sonnel.
The following listed manuals provide more technical documen-
tation for the System 8000:
Title
System 8000 HRM
Zeus System Administrator Manual
Zeus Utilities Manual
Zeus Reference Manual
Zilog Number
03-3237
03-3246
03-319f1
03-3195'
iii
Zilog
iii

CPU
iv
Zilog
Zilog
CPU
iv

CPU Zilog
CPU
Table of Contents
SECTION 1
OVERVIEW
...................................
1-1
1. 1.
1.2.
1.3.
Description •••••••••••••••••••••••••
Serial and Parallel I/O •••••••••••••
Memory and Memory Management ••••••••••••••••••
1-1
1-2
1-5
SECTION 2SPECIFICATIONS
2-1
2-1
2-1
2-1
2-1
2-2
2-5
2-6
2-6
2-6
2-7
2-7
2-8
........
Definitions •••••••••••••••••••
Lines •••••••••••••••••••• • ••
Introduction ••••••••••••• • ••••••••••••••••
Electrical Specifications •••••••••••••••
Physical Specifications •••••••••••••••••••••••
Environmental Specifications ••••••••
CPU I/O Connector •••••••••••••••
2.6. Bus Signals •••••••••••••••••••••••
2.6.1. ZBI Signal
2.6.2. ZBI Status
2.6.3. Data Width Codes •••••••••••••••••••••••••
Jumper Selection ••••••••••••••••••••••••••••••
Line Printer Jumper Selection ••••••••••••••
Baud Rate Selection •••••••••••••••••••••
2.1.
2.2.
2.3.
2.4.
2.5.
2.7.
2.8.
2.9.
SECTION 3
FUNCTIONAL DESCRIPTION .....................
3-1
·..........
.................
·...............
·...............
3-1
3-1
3-2
3-3
3-3
3-3
3-4
3-4
3-5
3-6
3-8
3-9
3-9
3~9
3-10
3-10
3-11
3-11
3-13
••• '.' •••••'•••• •.•• ~ ••• -•••• '.' •• e·.".
.............................
..............................
.......
'. ...........................
3.1. Description
3.1.1. Z8001A CPU Memory Addressing
3.1.2. Z8010A Memory Management Units •••••••••••
3.2. Memory Addressing ••••••••
3.2.1. Local Memory ••••••••
3.2.2. SCR Memory Selection •••••••••••••••••••••
3.2.3. Main Memory...................... ••
3.2.4. Byte Transactions •••••••••••••
3.3. I/O Addressing •••••••••••
3.3.1. Standard I/O
3.3.2. Special I/O
3.3.3. Offboard I/O ••••••••••
3.4. Reset, Interrupts and Traps
3.4.1. System Reset.
3.4.2. Non-maskable Interrupts •••••••••••
3.4.3. NMI Identification •••••••••••••••
3.4.4. Vectored Interrupts ••••••••••••••••••••••
3.4.5. The VI Daisy Chain •••••••
3.4.6. Non-vectored Interrupts
v
Zi10g
v

CPU
Zilog
CPU
3• 4• 7. Tr a ps •••••••••••••••••••••••••••••••••••• 3-13
3.5. Memory Management ••••••••••••••••••••••••••••• 3-14
3.5.1. MMU Configuration and Control •••••••••••• 3-15
3.5.2. System Configuration ••••••••••••••••••••• 3-17
SECTION 4CIRCUIT DESCRIPTION ........................
4-1
4-1
4-2
4-3
4-3
4-4
4-4
4-5
4-5
4-7
4-7
4-7
4-8
4-9
4-9
4-10
4-11
4-11
4-11
4-12
4-12
4-13
4-13
4-14
4-14
4-14
4-16
4-16
4-17
4-17
4-17
4.1. Z800JA CPU ••••••••••••••••••••••••••••••••••••
4.2. Clock Generation ••••••••••••••••••••••••••••••
4.2.1. Baud Clock •••••••••••••••••••••••••••••••
4.2.2. Real Time Clock ••••••••••••••••••••••••••
4.3. Parallel I/O Ports ••••••••••••••••••••••••••••
4.3.1. Printer Control Outputs ••••••••••••••••••
4.3.2. Printer Status Inputs ••••••••••••••••••••
4.4. Serial Input/ Output ••••••••••••••••••••••••••
4.4.1. SIC/CPU Interface ••••••••••••••••••••••••
4 • 5. In te r r upts ••••••••••••••••••••••••••••••••••••
4.5.1. Vectored Interrupt •••••••••••••••••••••••
4.5.2. vectored Interrupt Daisy Chain •••••••••••
4.5.3. NMI Identification •••••••••••••••••••••••
4.5.4. System Reset Logic •••••••••••••••••••••••
4.6. Memory Addressing •••••••••••••••••••••••••••••
4.6.1. Byte Transactions ••••••••••••••••••••••••
4.6.2. Read-Only Memory •••••••••••••••••••••••••
4.6.3. Read/Write Memory ••••••••••••••••••••••••
4.7. Byte Swap Buffer ••••••••••••••••••••••••••••••
4.8. Memory Management Control Logic •••••••••••••••
4.8.1. Non-segmented Operating System •••••••••••
4.8.2. Non-segmented User Program •••••••••••••••
4.8.3. Segmented User Program •••••••••••••••••••
4.8.4. MMU Configuration ••••••••••••••••••••••••
4.9. System Configuration Register •••••••••••••••••
4.9.1. SCR Configuration ••••••••••••••••••••••••
4.9.2. segmented/Non-segmented User •••••••••••••
4.9.3. parity Error Checking ••••••••••••••••••••
4.10. Special Logic Circuits •••••••••••••••••••••••
4.10.1. External Violation Registers ••••••••••••
4.10.2. Address/Data Buffers and
Steering Logic •••••••••••••••••••••••••••••••••• 4-17
4.10.3. T2, T3 Wait State Generator Logic ••••••• 4-18
4.10.4. peripheral Handshaking Logic •••••••••••• 4-19
4.10.5. Segment Trap Logic and Suppress ••••••••• 4-20
vi
Zilog
vi

CPU
Zilog CPU
SECTION 5
MAINTENANCE ••••••••••••••••••••••••••••••• e.
5-1
5.1. General............... • •••••
5.2. Preventive Maintenance ••••••
5.3. Corrective Maintenance ••••••••••
5.3.1. System Power-up Di agnost ics •••••••••.••
5.3.2. Inspection and Replacement ••••••••••••
5-1
5-1
5-1
5-1
5-6
SECTION 6
TIMING
..................................... 6-1
6-1
6-1
6-3
6-4
6-5
6-6
6-6
6-7
................
General ••••••••••••••
Memory Read and Write
Input/Output Timing
6.4. Interrupt Operation ••••••••• • •••••••••••••
6.4.1. Status Saving Sequence ••• • •••••••••••••
6.4.2. Bus Request Ackn~wledge Timing •••••••••
6.5. peripheral Interrupt Timing •••••••••••••••••
6.5.1. Return from Interrupt ••••••••••••••••••
6.1.
6.2.
6.3.
APPENDIX A
16 KILOBYTE EPROM MEMORY
.................. A-I
APPEllDIX BLOGIC
DIAGRAMS
B-1
vii Zilog
vii

CPU
Zi10g
List of Illustrations
CPU
Figure
1-1
1-2
System 8000 CPU Board ••••••••••••••••••••••• 1-3
CPU Functional Diagram •••••••••••••••••••••• 1-4
2-1 9~ pin Euro Standard Connector •••••••••••••• 2-2
3-1 Peripheral Interrupt priority ••••••••••••••• 3-13
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
6-1
6-2
6-3
6-4
6-5
6-6
6-7
vi ii
Clock Generation Circuit ••••••••••••••••••••
Baud Clock Generator ••••••••••••••••••••• ~ ••
Parallel I/O ••••••••••••••••••••••••••••••••
Serial I/O with CTC Channels ••••••••••••••••
vectored Interrupt ••••••••••••••••••••••••••
Interrupt priority Connection •••••••••••••••
System Reset Logic ••••••••••••••••.•••••••••
System Configuration Register •••••••••••••••
Setting Console Baud Rate
(9600 Baud) for a-inch Disk •••••••••••••••••
T3 Wait State Generator Logic •••••••••••••••
Peripheral Handshaking Logic ••••••••••••••••
Memory Read and Write Timing ••••••••••••••••
Write Cycle •••••••••••••••••••••••••••••••••
Read 'Cycle ••••••••••• : ••••••••••••••••••••••
Segment Trap/Interrupt Acknowledge Cycle ••••
Bus Request Acknowledge Cycle •••••••••••••••
Interrupt Acknowledge Cycle ••••••••••••• 0 •••
Return from Interrupt Cycle •••••••••••••••••
Zilog
4-3
4-3
4-4
4-6
4-8
4-9
4-10
4-15
4-16
4-19
4-20
6-2
6-4
6-4
6-5
6-6
6-7
6-8
viii

CPU
Table
2-1
2-2
2-3
2-4
2-5
2-fi
2-7
2-8
2-9
3-1
3-2
3-3
3-4
4-1
4-2
5-1
ix
Zilog
List of Tables
Electrical Requirements, Domestic •••••••••••
Physical Specification ••••••••••••••••••••••
Environmental Specifications ••••••••••••••••
CPU Pin Assignments (P2) ••••••••••••••••••••
CPU I/O BUs, Signal Definitions •••••••••••••
ZBI Connector (PI) Pin Assignments ••••••••••
Status Transaction Coding •••••••••••••••••••
Data Width: Byte, Word, Long Word •••••••••••
Baud Rate Setting and
primary Boot pevice (U70) •••••••••••••••••••
I/O Address,Device and Channel ••••••••••••••
Special I/O MMU Address •••••••••••••••••••••
NMI Identification ••••••••••••••••••••••••••
Peripheral Device priority ••••••••••••••••••
Printer Control Signals ••••••••••• 8 •••••••• 8
Printer Status Signals ••••••••••••••••••••••
SPUD Diagnostic Error List ••••••••••••••••••
Zilog
CPU
2-1
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
3-7
3-8
3-11
3-12
4-5
4-5
5-3
ix

CPU
zilog
Zilog
CPU
x

CPU
1.1. Description
Zilog
SECTION 1
OVERVIEW
CPU
The Zilog System 8000 Central Processor Unit (CPU) board
(Figure 1-1) is the controlling processor board for the Sys-
tem 8000.
The System 8000 CPU is designed around the Zilog Z8001A 16-
bit microprocessor which uses an advanced instruction set, 8
Mbyte segmented addressing space, and 16 bit registers.
Memory management increases the addressing capability to 16
Mbyte by dynamic segment relocation and protection from
three Z8010A Memory Management Units and special control
logic. Software addressing is then independent of the phy-
sical memory address and eliminates the need to specify
where information is actually located in memory.
The Zilog Z8001A segmented 6 MHz microprocessor runs the
Zilog ZEUS operating system, a high performance implementa-
tion of UNIX. The operating system presently implements
non-segmented operation while user programs can be either
segmented or non-segmented.
The System 8000 CPU board initiates and controls transac-
tions on both the system and input/output (I/O) bus. The
Z8001A microprocessor acts as the host and controls the
system bus Z-Bus Backplane Interconnect (ZBI) and all paral-
lel and serial I/O to and from the system.
The CPU board (Figure 1-2), at P2/J21, connects directly to
and controls the I/O bus and all I/O transactions pass
through P2 to the parallel port or one of eight serial I/O
ports. The eight serial channels support the RS-232C stan-
dard.
The System 8000 CPU board is one of several printed circuit
boards in a system and is inserted into slot one of the card
cage.
Plug Pl/Jll connects to the ZBI bus and P2/J2l connects to
the I/O bus. The connectors are three level 96 pin Euro
standard. The Zilog ZBI is a 32-bit backplane bus which
interconnects the boards of the system. Figure 1-1 identi-
fies the components of the System 8000 CPU board.
1-1
Zilog
1-1

CPU
Zilog
CPU
1.2. Serial and Parallel I/O
Eight serial ports and one parallel printer port are imple-
mented on the board using four Zilog Z808 Serial
Input/Output(SIO) chips and a single Z808 Parallel
Input/Output (PIO) chip. The eight asynchronous/full-duplex
serial channels receive and transmit serial dat'a. These
channels support up to eight users, with channell reserved
for the console, and are RS232C compatible.
1-2
Zi10g
1-2

CPU Zilog
SEGMENTEDINON-SEGMENTED
OPERATING SYSTEM
CONFIGURATION JUMPERS
E1-E12 TEST POINTS
%8001 A
MICROPROCESSOR
CONSOLE BAUD RATE
SELECTOR· SWITCH
AND BOOT DEVICE
3 MEMORY
MANAGEMENT
UNITS
PRINTER JUMPERS
E18,17,18
CPU
PRINTER JUMPERS
E13,14,15
BAUD RATE
GENERATORS
4PROM
MONITORS
PARALLEL
PORT
8SERIALUO
CHANNELS
BAUD RATE GENERATOR
AND REAL TIME CLOCK
1-3
Figure 1-1 System 8000 CPU Board
Zilog
1-3

CPU
Zilog
CPU
8 SERIAL PORTS
SERIAL
UO 7
RS232C
SERIAL
UO 1
RS232C
SERIAL
UOO
RS232C
PARALLEL
UO
·CENTRONICS
UO BUS CONNECTOR P2tP21
SLOT 1 ON BACKPLANE
CPU
Z8I P11J11
.. OR DATA PRODUCTS
00180
'igure 1-2 CPU Functional Diagram
1-4
Zi10g
1-4

CPU
Zilog
CPU
Each channel has an independently programmed selectable baud
rate from 300 Hz up to 19.2 KHz for individual terminals and
supplied by three Z80B Counter Timer Circuits(CTCs). Each
channel is limited to the same baud rate for receiving and
transmitting. The CTCs are driven by a baud rate oscillator
which is independent of the system clock frequency. A
daisy-chain peripheral device priority scheme selects the
highest priority onboard and offboard peripheral device.
Plug P2/J2l supplies the I/O connection to the offboard
peripheral equipment. Either a Centronics or Data Products
interface for a line printer is established by two jumper
changes on the board.
1.3. Memory and Memory Management
The local onboard memory is used for bootstrapping the
operating system and for hardware diagnostics. It consists
of 8K bytes (4K words) of resident Erasable programmable
Read-Only'Memory(EPROM) and 2K bytes (lK words) of Random
Access Memory(RAM) •
NOTE: The 8K EPROM has been increased to l6Kbytes as shown
by the Logic Drawing (Appendix B) (DZ-0288).
Three Zilog Z80l0A Memory Management Units (MMUs) facilitate
an efficient and flexible usage of the System 8000 by
dynamic relocation of tasks in main memory. Special control
logic is implemented that supports all the major goals of
memory management (Para.3.5). For the nonsegmented operating
system, the three MMUS separate code(program) ,data, and
stack areas, and the operating system uses segment 0 of each
of the three MMUs for its code, data and stack space. The
data and stack MMUs are selected by special hardware on the
board that compares the logical address with the contents of
a hardware system break register to determine the MMU
selected. The MMU N/S- input selects the MMU.
The non-segmented user programs are run in any segment (2-
63) while segmented user processes can use one or more logi-
cal segments (2-63) to (66-127). The SEG USER bit of the
System Configuration Register must be set before running a
segmented user process. The normal break register replaces
the system break register and the NORMAL MMU input selects
the MMU. This configuration reflects a non-segmented operat-
ing system for the segmentedornon-segmehted user.
1-5
Zilog
1-5

CPU
1-6
Zilog
Zilog
CPU
1-6

CPU
2.1. Introduction
Zilog
SECTION 2
SPECIFICATIONS
CPU
This section contains the electrical, physical, and environ-
mental specifications. Information on ZBI and I/O bus sig-
nals, status signals and encoding, and jumpering is also
incl uded.
2.2. Electrical Specifications
Table 2-1 lists the CPU board power requirements for u.s.
domestic systems.
Table 2-1. Electrical Requirements, Domestic
ITEM REQUIREMENT
Voltage +5Vdc, -SVdc +-O.2SVdc
Current 3.5 Amps (Typical)
2.3. Physical Specifications
Table
2-2 lists the physical specifications
for
board.
Table 2-2. Physical Specification
ITEM REQUIREMENT
Height
Width
27.9 cm (11 inches)
22.9 cm (9 inches)
2.4. Environmental Specifications
The CPU board can be expected to perform reliably provided
all environmental specifications are maintained.
2-1
Zilog
2-1

CPU
Zi10g
CPU
Table 2-3. Environmental Specifications
Operating temperature:
10 degrees C (50 degrees F) minimum
40 degrees C (104 degrees F) maximum
Relative Humidity:
80% noncondensing
2.5. CPU I/O Connector
Figure 2-1 illustrates the 96 pin Euro standard connector
with three rows (A,S,C,) of 32 pins each. This connector is
used for both I/O (P2) and ZSI (PI) connection •
o
32
••••••••••••••••••••••••••••••••
'::::::::::::::::::::::::::::::::1
C
B
_.............. ....,.""""'"' ...... --'A
Figure 2-1 96 pin Euro Standard Connector
Table 2-4 lists the I/O bus connections for plug P2 as well
as listing the signal descriptions and pin assignments for
each of the three rows of pins.
2-2
Zilog
2-2