ZiLOG Z8 Encore! User manual

Z8 Microcomputer
Technical Manual
April 1983

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Z8 Microcomputer
Technical Manual
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Copyright 1983 by Zilog, Inc. All rights reserved. No part of
this publication may be reproduced without the written
permission of Zilog, Inc.
The information in this publication is subject to change
without notice.

Table Of Conlents
Chapter 1. ZB Family Overview
1.1 Introduction
1.2 Fe~tures
1 .2. 1 I nstruction Set
1.2.2 Architecture •••
1.3 Microcomputers (Z8601/11) ••
1.4
Development Device (Z8612)
1.5 Protopack Emulator (Z8603/13)
1.6 BASIC/Debug Interpreter (Z8671) •
1.7 ROMless Microcomputer (Z8681/82)
1.8 Applications
Chapter 2. Architectural Overview
2.1 Introduction
2.2 Address Spaces
2.3 Register File ••
2.3.1 Register Pointer.
2.3.2 Instruction Set
2.3.3 Data Types ••••
2.3.4 Addressing Modes.
2.4 I/O Operations
2.4.1 Timers ••
2.4.2 Interrupts
2.5 Oscillator
2.6 Protopack.
Chapter 3. Address Spaces
3.1 Introduction
3.2 CPU Register File •
3.3
3.4
3.5
3.6
3.2.1 Error Conditions
CPU Control and Peripheral Registers
CPU Program Memory
CPU Data Memory •
CPU Stacks
• 1-1
• 1-1
• 1-1
1-1
1-3
• 1-3
• 1-4
• 1-4
• 1-4
•••• 1-4
• 2-1
• 2-1
••• 2-2
• 2-2
• 2-2
• 2-2
• 2-2
• 2-2
• • 2-2
• 2-2
••• 2-3
• 2-3
3-1
3-1
3-2
3-3
3-3
3-5
3-6
1
2
3
iii

Table Of Contents (Continued)
Chapter 4. Address Hodes
4.1
4.2
4.3
4.4
4.5
4.6
4.7
Introduction • • • • • • • •
Register Addressing (R) • • • • • •
Indirect Register Addressing (IR) •
Indexed Addressing (X)
Direct Addressing (DA)
Relative Addressing (RA)
Immediate Data Addressing (1M)
Chapter 5. Instruction Set
5.1
5.2
5.3
5.4
Functional Summary
Processor Flags ••
5.2.1 Carry Flag (C) •
5.2.2 Zero Flag (Z)
5.2.3 Sign Flag (S)
5.2.4 Over flow Flag
(V)
5.2.5
Decimal-Adjust Flag
5.2.6 Hal f-Carry F lag (H)
Condition Codes • •
(D)
Notation and Binary Encoding
5.4.1 Assembly Language Syntax •••••
5.4.2 Condition Codes and Flag Settings
5.5 Instruction Summary ••••••
5.6 Instruction Descriptions and Formats
Chapter 6. External Interface (Z8601, Z8611)
6.1
6.2
6.3
6.4
6.5
6.6
Introduction
Pin Description ••••••••
Configuring for External Memory
External Stacks •
Data Memory •
Bus Operation • •
6.6.1 Address Strobe (AS)
6.6.2 Data Strobe (DS) ••
6.6.3 External Memory Operations.
6.7 Shared Bus •••••
6.8 Extended Bus Timing •
6.9 Instruction Timing
6.10 Reset Conditions
iv
• • 4-1
• • 4-1
• • 4-2
• 4-2
• 4-3
• • 4-3
• • 4-4
• • 5-1
• 5-2
• • 5-2
• • 5-2
• • 5-2
• 5-3
••• 5-3
• • 5-3
• 5-3
• • 5-3
• 5-4
• 5-4
• • 5-6
• 5-7
• 6-1
•••• 6-1
••• 6-2
• • 6-3
• 6-3
• • 6-3
• 6-4
• 6-/~
• • 6-4
• •• 6-5
• 6-6
• 6-7
• 6-10
4
5
6

Chapter 7. External Interface (Z8681, Z8682)
7.1 Introduction
7.2 Pin Descriptions
7.3 Configuring Port 0
7.3.1 Z8681 Initialization ••
7.3.2 Z8682 Initialization.
7.3.3 Read/Write Operations
7.4 External Stacks
7.5 Data Memory ••
7.6 Bus Operation.
7.7
7.8
7.9
7.10
7.6.1 Address Strobe (AS)
7.6.2 Data Strobe (OS)
Extended Bus Timing
Instruction Timing
Z8681
Reset Conditions
Z8682 Reset
Conditions
Chapter 8. Reset and Clock
8.1 Reset •••••••••
8.2 Clock ••••••••••••••••
8.3 Power-down Operation
8.4 Test Mode •••• " •
8.4.1
8.4.2
Interrupt Testing
ROMless Operation
Chapter 9. I/O Ports
9.1
9.2
9.3
Introduction
9.1.1 Mode Registers ••••••
9.1.2 Input and Output Registers.
Port 0
9.2.1 Read/Write Operations
9.2.2 Handshake Operation
Port 1
9.3.1 Read/Write Operations
9.3.2 Handshake Operation
• 7-1
• • 7-1
• 7-2
• 7-2
• 7-3
• 7-4
•.•• 7-4
• 7-4
• 7-5
• 7-5
• 7-5
7-5
7-6
7-6
7-6
• • 8-1
• • 8-2
• 8-3
• 8-4
• • 8-5
• 8-5
9-1
• 9-1
• • 9-1
9-1
• 9-3
• 9-3
9-4
• 9-4
• • 9-4
7
8
v

Table Of Contents (Continued)
9.4
9.5
Port 2
9.4.1 Read/Write Operations
9.4.2 Handshake Operation
Port 3
9.5.1
9.5.2
Read/Write Operations
Special Functions
9.6 Port Handshake •••••
9.7 I/O Port Reset Conditions.
Chapter 10. Interrupts
10.1 Introduction
10.2 Interrupt Sources •
10.2.1 External Interrupt Sources
10.2.2 Internal Interrupt Sources
10.3 Interrupt Request Register Logic and Timing •
10.4 Interrupt Initialization •••••
10.4.1
10.4.2
10.4.3
Interrupt Priority Register Initialization
Interrupt Mask Register Initialization
Interrupt Request Register Initialization •
10.5 IRQ Software Interrupt Generation • •
10.6 Vectored Processing •••••••
10.7
10.8
vi
10.6.1
10.6.2
Vectored Interrupt Cycle Timing
Nesting of Vectored Interrupts
Polled Processing
Reset Conditions
9-5
• 9-5
9-5
9-6
9-6
9-7
9-8
9-10
10-1
10-1
10-1
10-3
10-3
10-3
10-4
10-5
10-5
10-5
10-6
10-7
10-7
10-7
10-7
9
10

Chapter 11. Counter/T imers
11.1 Introduction
11.2 Prescalers and Counter/Timers ••
11.3 Counter/Timer Operation
11.3.1 Load and Enable Count Bits
11.3.2 Prescaler Operations
11.4 TOUT Modes •••
11.5 TIN Modes.
11.5.1 External Clock Input Mode.
11.5.2 Gated Internal Clock Mode.
11.5.3 Triggered Input Mode
11.5.4 Retriggerable Input Mode
11.6 Cascading Counter/Timers.
11.7 Reset Conditions
Chapter 12. Serial I/O
12.1 Introduction
12.2 Bit Rate Generation
12.3 Receiver Operation.
12.4
12.5
12.3.1 Receiver Shift Register.
12.3.2 Overwrites
12.3.3 Framing Errors
12.3.4 Parity
Transmitter Operation •
12.4.1 Overwrites
12.4.2 Parity
Reset Conditions
Appendix A. Pin Descriptions and functions
A.1 Development Device (Z8612)
A.2 Protopack Emulator (Z8603/13)
Appendix B.
Control Registers
Appendix C. Opcode Hap • • • •
11-1
• 11-2
11-3
11-3
11-3
• 11-4
• 11-5
11-6
11-6
11-8
• 11-8
• 11-8
•• 11-8
••• 12-1
• 12-1
• 12-3
12-3
• 12-4
• 12-4
• 12-4
12-4
• 12-5
• 12-5
12-6
• A-1
• A-1
B-1
C-1
11
12
vii

Table Of Contents (Continued)
List of Illustrations
Figure 2-1 Z8 Block Diagram
Figure 2-2 Bits in Register •
Figure
3-1
Figure
3-2
Figure
3-3
Figure
3-4
Figure
3-5a
Figure
3-5b
Figure
3-5c
Figure
3-5d
Figure
3-6a
Figure
3-6b
Figure 3-6c
Figure
3-7
Figure
3-8
Figure
4-1
Figure
4-2
Figure
4-3
Figure
4-4
Figure 4-5
Figure 4-6
Figure
4-7
Figure
4-8
Figure
5-1
Figure
6-1
Figure
6-2
Figure
6-3
Figure
6-4
Figure
6-5
Figure
6-6a
Figure 6-6b
Figure
6-7
Figure
6-8
Figure
6-9a
Figure
6-9b
Figure
6-10
Figure
6-11
Figure
6-12
Figure 6-13
Figure 7-1
Figure 7-2
Figure 7-3
Figure 7-4
viii
Register File • • • • • •
16-Bit Register Addressing •
Working Register Groups
Working Register Addressing
Z8601 Program Memory Map
Z8611 Program Memory Map
Z8681 Program Memory Map •
Z8682 Program Memory Map
Z8601 or Z8682 Data Memory Map •
Z8611 Data Memory Map
Z8681 Data Memory Map
Stack Pointer
Stack Operations • •
Register Addressing
Working-Register Addressing
Indirect Register Addressing to Register File
Indirect Register Addressing to Program or Data Memory
Indexed Addressing •
Direct Addressing
Relative Addressing
Immediate Data Addressing
Flag
Register
Z8601/11 Pin Functions •••••••••
Z8601/11 Pin Assignments ••••••••
Ports 0 and 1 External Memory Operation
Ports 0 and 1 Stack Selection • • • • •
Data Memory Operation
External Instruction Fetch, or Memory Read Cycle •
External Memory Write Cycle
Shared Bus Operation • • • • • •
Extended Bus Timing • • • • • • ••••
Extended External Instruction Fetch, or Memory Read Cycle
Extended External Memory Write Cycle
Instruction Pipe lining • • • • • • • • • • • •
Instruction Cycle Timing (One Byte Instructions) •
Instruction Cycle Timing (Two and Three Byte Instructions
Ports 0 and 1 Reset
Z8681/82 Pin Functions • • • • •
Z8681/82 Pin Assignments • • •
Example Z8681/Memory Interface •
Example Z8681/Memory Interface •
• 2-1
• • 2-2
• • 3-1
• •• 3-1
• •• 3-2
• • 3-2
• 3-3
• • 3-4
• • 3-4
3-4
• • 3-5
• 3-5
• • 3-5
• •• 3-6
3-6
• • 4-1
• • 4-1
• • 4-2
• • 4-2
4-3
• • 4-3
• • 4-3
• • • 4-4
5-2
6-1
• • 6-1
• 6-2
6-3
• 6-3
• • • • 6-4
6-5
• 6-5
6-6
• • 6-6
• • 6-7
• • 6-8
• 6-9
• • 6-9
• 6-10
7-1
• • 7-1
• • 7-2
7-3

'",-,
Figure 7-5
Figure 7-6
Figure 7-7
Figure 7-8
Figure 7-9
Figure 7-10
Figure 7-11
Figure
8-1
Figure
8-2
Figure
8-3
Figure
8-4
Figure
8-5
Figure
8-6
Figure
8-7
Figure
8-8
Figure
9-1
Figure
9-2
Figure
9-3
Figure
9-4
Figure
9-5
Figure
9-6
Figure
9-7
Figure
9-8
Figure
9-9
Figure
9-10
Figure
9-11
Figure
9-12
Figure
9-13
Figure
9-14
Figure
9-15
Figure
9-16
Figure
9-17
Figure
9-18
Figure
9-19
Figure
9-20
Figure 9-21
Figure
9-22
Figure 9-23
Figure
10-1
Figure
10-2
Figure
10-3
Figure
10-4
Figure
10-5
Figure
10-6
Figure
10-7
Figure
10-8
Figure
10-9
Z8681 Port 0 Memory Operation
Z8682 Port 0 Memory Operation
External Stack Operation • • •
Port 3 Data Memory Operation • •
•
7-3
• 7-4
• 7-5
• • 7-5
Extended
Bus Timing • • • • • • • 7-5
Z8681 Port 0 and 1 Reset Conditions • • • • • • • • • • • • • • •• 7-6
Z8682 Ports 0 and 1 Reset Conditions •••••••••••••••• 7-6
Reset Timing
Power-Up Reset Circuit
Z8 Clock Circuit
Crystal/Ceramic Resonator Oscillator
External Clock Interface
Battery-Backed Register Supply
Normal and Test Mode Flow
Voltage Waveform for Test Mode
I/O Port and Port Mode Registers
Ports 0, 1, and 2 Block Diagram
Port 0 I/O Operation • • • •
Port 0 Handshake Operation •
Port 0 • • • • • • • • • • •
Port 1 I/o Operation • • • •
Port
Port
Handshake Operation •
Port 2 I/O Operation • • •
Port 3 Handshake Operation •
Port 2 • • • • • • • • • • •
Port 2 Open-Drain Outputs
Port 3 Block Diagram
Port 3 I/O Operation •
Z8 Input Handshake • •
• 8-2
• 8-3
• 8-3
• 8-3
• 8-3
• 8-4
• • 8-4
••••• 8-5
• • 9-1
9-2
• • 9-3
• 9-3
• 9-3
• 9-4
• • 9-4
• ••••• 9-4
• • 9-5
• 9-5
• • 9-5
• 9-6
• 9-6
• 9-7
• 9-8
Z8 Output Handshake • • • • • • • • • • • • • 9-9
Input Strobed Handshake using Port 2 • • • • • • • • • • • • 9-9
Output Strobed Handshake using Port 2 • 9-9
Z8601/11 Ports 0 and 1 Reset. • • • • • • 9-10
Z8681 Ports 0 and 1 Reset • • • • • • • 9-10
Z8682 Ports 0 and 1 Reset • • • • • • • • • • • • • • • • • • • •• 9-10
Port 2 Reset. • • • • • • • • • • • • • 9-11
Port 3 Reset. • • • • • • • • • 9-11
Interrupt Control Registers ••••• • •
Interrupt Block Diagram • • • • • • • •
Interrupt Sources IRQO-IRQ2 Block Diagram
Interrupt Source IRQ3 Block Diagram
IRQ Register Logic • • • • • • • • • • •
Interrupt Request Timing. • • • • ••••••
Interrupt Priority Register •••••
Interrupt Mask Register •••••
Interrupt Request Register • •
• 10-1
• 10-1
• 10-2
•• 10-2
• 10-3
• 10-3
• 10-4
• 10-5
• 10-5
ix

Table Of Contents (Continued)
Figure 10-10 Effect of Interrupt on Stack ••••••
Figure 10-11 Interrupt Vectoring •••••••••
Figure 10-12 ROM Z8 Interrupt Timing (shrink parts) •
Figure 10-13 Z8681 ROMless Z8 Interrupt Timing
Figure 11-1
Figure 11-2 Counter/Timer Block Diagram
Counter/Timer Register Map.
Figure 11-3 Prescaler 0 Register.
Figure 11-4 Prescaler 1 Register.
Figure 11-5 Counter/Timers 0 and Registers.
Figure 11-6 Timer Mode Register
Figure 11-7 Starting the Count.
Figure 11-8 Counting Modes. • • • • ••••••
Figure 11-9 Port 3 Mode Register TOUT Operation
Figure 11-10 Timer Mode Register TOUT Operation ••
Figure 11-11 Counter/Timers Output Via TOUT ••••••••••••
Figure 11-12 Internal Clock Output Via TOUT ••
Figure 11-13 Timer Mode Register TIN Operation •••••
Figure 11-14 Prescaler 1 TIN Operation
Figure 11-15 External Clock Input Mode
Figure 11-16 Gated Clock Input Mode.
Figure 11-17 Triggered Clock Mode •••••••••
Figure '11-18 Cascaded Counter/Timers
Figure 11-19 Counter/Timer Reset
Figure 11-20 Prescaler 1 Register Reset.
Figure 11-21 Prescaler 0 Reset
Figure 11-22 Timer Mode Register Reset
Figure 12-1
Figure 12-2
Figure 12-3
Figure 12-4
Figure 12-5
Figure 12-6
Figure 12-7
Serial I/O Block Diagram
Serial I/O Register Map
Port 3 Mode Register and
Bit Rate Divide Chain
Bit Rate Generation
Prescaler 0 Register and Bit Rate Generation
Timer
Mode Register and Bit Rate Generation
Receiver Timing
Figure 12-8 Receiver Data Formats •••••
Figure 12-9 Parity and Port 3 Mode Register
Figure 12-10 Transmitter Data Formats •
Figure 12-11 Serial I/O Register Reset
Figure 12-12 Port 3 Register Reset
Figure A-1
Figure A-2
Figure A-3
Figure A-4
Figure B-1
Figure C-1
x
Z8612 Pin Functions
Z8612 Pin Assignments
Protopack Emulator • •
Protopack
EPROM Socket
Control Registers
Opcode Map • • • •
• •••• 10-6
10-6
• • 10-8
• • 10-8
• 11-1
11-2
• 11-2
• 11-2
• •••• 11-2
• •• 11-3
• 11-3
• • 11-3
• • 11-4
• •• 11-4
• •••• 11-5
• • 11-5
• • 11-5
• •• 11-5
• • 11-6
• • 11-6
• 11-7
• • 11-7
• • 11-8
• 11-8
• •••• 11-9
• •••• 11-10
12-1
• 12-2
• 12-2
• •• 12-1
• 12-3
• •••• 12-3
••••••• 12-3
• • 12-4
• ••••• 12-5
• •••• 12-5
• • 12-6
12-6
• • A-2
• • A-3
• • A-3
• A-3
B-1
C-1

List of Tables
Table 1-1
Table 5-1
Table 8-1
Table
9-1
Table 10-1
Table 10-2
Table 12-1
Z8 Family of Products
Condition Codes • • •
Control and Peripheral Register Reset Values
Port 3 Line Functions • •
Interrupt Types, Sources, and Vectors
Interrupt Priority • • • • •
Bit Rate
1-2
5-5
8-1
9-7
• 10-2
• 10-4
12-2
xi

1.1 INTRODUCTION
This chapter provides an overview of the architec-
ture and features of the ZS Family of products,
with particular emphasis on those features that
set this microcomputer apart from earlier micro-
computers. Detailed information about the archi-
tecture, address spaces and modes,
set, external interface, timing,
instruction
input/output
operations, and interrupts can be found in subse-
quent chapters of this manual.
1.2 FEATURES
The ZS microcomputer introduces a new level of
sophistication to single-chip architecture. Com-
pared to earlier single-chip microcomputers, the
ZS offers faster execution; more efficient use of
memory; more sophisticated interrupt, input/output
and bit-manipulation capabilities; and easier sys-
tem expansion.
ZS products offer the standard on-chip functions
of earlier microcomputers, including:
•
2K or 4K bytes of ROM
• 144
S-bit registers
•
32 lines of programmable I/O
• Clock
oscillator
•
Arithmetic logic unit
•
Parallel and serial ports
Beyond these basic features, the ZS Family offers
such advanced characteristics as:
• Two counter/timers
• Six vectored interrupts
• UART for serial I/O communication
• Stack functions
• Power-down option
• TTL compatibility
• Optimized instruction set
• BASIC/Debug interpreter
All members of the ZS Family are variations of the
basic ZS microcomputer, the ZS601/11. The ZS
Family includes a development device (ZS612), a
RoMless
device (ZS6S1/S2), BASIC/Debug Interpreter
(ZS671), a Protopack emulator (ZS603/D), as well
Chapter 1
Z8 Family Overview
as the basic microcomputer. These products offer
all the parts and development tools necessary for
systems development (both hardware and software
prototyping), field trials (pre-production) and
full production. For prototyping and preproduc-
tion, or where code flexibility is important, the
ZS603/13 Protopack, 2K and 4K EPROM-based parts
are the most appropriate. The ROM-based ZS601/11
microcomputers are used in high-volume production
applications after the software has been per-
fected. For RoMless applications, two versions of
the ZS microcomputer are available: the 4o-pin
ZS6S1/S2 and the 64-pin ZS612. In addition, there
is a military version of the ZS611 4K ROM device,
available in both 4o-pin ceramic and 44-pin lead-
less chip carrier packages.
The ZS671 MCU is a complete microcomputer prepro-
grammed with a BASIC/Debug Interpreter. This
device, operating with both external ROM or RAM
and on-chip memory registers, is suitable for most
industrial control applications, or whenever fast
and efficient program development is necessary.
The ZS microcomputer is well-suited for dedicated
control applications in real-t ime mode. Since
speed is a key consideration in such applications,
the ZS Family is available in both Sand 12 MHz
versions,
modules:
Z-SCAN S.
supported by either of two development
the Development Module (BM) or the
The Z-SCAN module provides (ICE) in-
circuit emulation capability.
1.2.1 Instruction Set
The ZS instruction set, consisting of 43 basic
instructions, is optimized for high-code density
and reduced execution time. The 47 instruction
types and six addressing modes--together with the
ability to operate on bits, 4-bit words, BCD
digits, S-bit bytes, and 16-bit words--make for a
code-efficient, flexible microcomputer.
1.2.2 Architecture
ZS architecture offers more flexibility and per-
formance than previous A/B accumulator designs.
All 12S general-purpose registers, including
1-1

Z8 Family Overview
dedicated I/O port registers, can be used as
accumulators. This eliminates the bottleneck com-
monly found in A/B devices, particularly in high-
speed applications such as disk drives, printers
and terminals. In addition, the registers can be
used as address pointers for indirect addressing,
as index registers or for implementing an on-chip
stack. Speed of execution and smooth programming
are supported by a "working register area"--short
4-bit register addresses.
Table 1-1 lists the basic characteristics of the
members of the Z8 Family. As shown, the major
differences between the products are in their
physical packaging and the manner in which address
space is handled. An overall description for each
Z8 type is given in the following sections.
Variations within each group are specified where
applicable.
Table 1-1. ZB Family of Products
ROM
Part Capacity Progr~able Dedicated PCB
Product Ntnber
(Bytes)
I/O Pins
I/O Pins Footprint
Conments
2K ROM Z8601
2K
32, 4 ports 8 Power, 40 Pin
Masked ROM part, used
Control
primarily for high volume
production.
2K Protopack Z8603
0 32, 4 ports 8 Power, 40 Pin Piggyback
part used where
Control program flexibility is
plus
required (prototyping).
24 EPROM
4K ROM
Z8611 4K 32, 4 ports
8 Power, 40 Pin Masked ROM part, used
Control primarily for high volume
production.
4K Develop- Z8612 0 32, 4 ports 8 Power, 64 Pin ROMless part used primarily
ment part
Control
in development systems.
plus 24
external
memory
4K Protopack
Z8613 0 32, 4 ports 8 Power, 40 Pin Piggyback part used where
Control program
flexibility is
plus required (prototyping).
24 EPROM
BASIC/ Z8671
2K 32, 4 ports 8 Power, 40 Pin BASIC/Debug part used in
Debug
Control low volume applications.
ROMless
Z8681/82 0 24, 3 ports
8 Power,
40 Pin
Low
cost ROMless production
Control
part with reduced I/O.
plus 8 Program
memory is external.
external
memory
1-2

1.J MICROCOMPUTERS (Z8601/Z8611)
The Z8 can be a stand-alone microcomputer with
either 2K bytes (ZB601) or 4K bytes (Z8611) of
internal ROM, a traditional microprocessor that
can manage up to 124K bytes (ZB601) or 120K bytes
(ZB611) of external memory, Or a parallel proces-
sing element in a system with other processors and
peripheral controllers linked by a Z-BUS. In all
configurations, a large number of device pins are
available for I/O. Key features of the Z8601/11
microcomputer include:
• ROM 2K-byte (Z8601) or 4K-byte (Z8611) Program
Memory. This ROM is mask-programmed during
production with user-provided programs.
•
•
•
144-byte RAM Register File. The internal
register organization of the ZB microcomputer
centers around a 144-byte file composed of 124
general-purpose registers, 16 status and
control registers, and 4 I/O port registers.
Either an B-bit or a 4-bit address mode can be
used to access the register file. When the
4-bit mode is used, the register file is
divided into 9 groups of 16 working registers
each. A Register Pointer uses short-format
instructions to quickly access anyone of the
nine groups. Use of the 4-bit addressing mode
decreases access time and improves throughput.
Programmable Counter/Timers. Two 8-bit coun-
ter/timer circuits are provided, each driven by
its own prescaler. Both the counter/timers and
their prescaler circuits are programmable.
UART (Universal Asynchronous Receiver Transmit-
ter). A full-duplex UART is provided to
control serial data communications. One of the
on-chip counter/timer circuits provides the
required bit rate input to enable the UART to
operate at a maximum data transfer rate of
93.75K bits per second at a crystal frequency
of 12 MHz.
• I/O Lines/Ports. The ZB microcomputer provides
32 input/output lines, arranged as 4 8-bit
ports. Under software control, the I/O ports
(Ports 0, 1, 2, 3) can be programmed as input,
output, or additional address lines. The I/O
ports can also be programmed to provide timing,
status signals, interrupt inputs and serial or
parallel I/O (with or without handshake).
I-V I UIII.&.., \J",,",,~ y ..... .,..
• Vectored Interrupts. The ZB MPU permits the
use of six di fferent interrupts from any of
eight different sources. Four Port 3 lines
(P3
0-P33
), serial input pin (P30 ), the serial
output pin (P37) and both counter/timer
circuits may be interrupt sources. All
interrupts are vectored and are both maskable
and
prioritized.
• Oscillator Circuit. An oscillator circuit that
can be driven from an external clock or crystal
is provided on the Z8 microcomputer. The
oscillator will accept an input frequency of up
to 12 MHz on the two input pins provided.
• Optional Power-Down Feature.
This option
permits normal input power to be removed from
the chip without affecting the contents of the
register file. The power-down funct ion
requires an external battery backup system.
Pin functions and descriptions for the ZB601/11
microcomputer can be found in Chapter 6.
1.4 DEVELOPMENT DEVICE (Z8612)
A development device allows users to prototype a
system with an
actual hardware device and to
develop the code that is eventually mask-pro-
grammed into the on-chip ROM of the Z8601 or Z8611
microcomputer. Development devices are also use-
ful in applications where production volume does
not justify the expense of a ROM system. The
ZB612 development device is identical to its
equivalent microcomputer, the Z8611, with the fol-
lowing exceptions:
• No internal ROM is provided, so that code is
developed in an off-chip memory.
• The normally internal ROM address and data
lines are buffered and brought out to external
pins to interface with the external memory.
• Control lines are added to interface with
external program memory.
• The device package is enlarged in order to
accommodate the new control, address, and data
lines.
Pin functions and descriptions for the development
device can be found in the Appendix.
1-J

LO tam~ly uverv~ew
1.5 PROTOPACK EMULATOR (18603/13)
The Protopack emulator devices, Z8603 and Z8613,
are ROMless versions of their equivalent microcom-
puters (Z8601 and Z8611, respectively). The emu-
lators differ from development devices in two
ways: they use the same pinout as the microcom-
puters, and an external ROM or EPROM can be
plugged
into the top of the package. The emulator
package
allows for flexibility of application,
since it can be used in either prototype or final
pc boards, yet still allows for program develop-
ment.
When the final program is developed, it can be
mask-programmed
into the Z8601/11 which then
replaces the emulator. The emulator is also use-
ful in small volume applications where the cost of
mask-programming is prohibitive or where program
flexibility is desired.
Physical description for the Protopack emulator is
found in the Appendix.
1.6 BASIC/DEBUG INTERPRETER (18671)
The Z8671 MCU is a complete microcomputer prepro-
grammed with a BASIC/Debug interpreter. BASIC/
Debug can directly address the Z8671 ,s internal
registers and all external memory. It can quickly
examine and modify any external memory location or
I/O port, and can call machine language subrou-
tines to increase execution speed.
The Z8671 MCU has a combination of software and
hardware that is ideal for most industrial control
applications. Along with the functions mentioned
above,
this microcomputer has a self-contained
line editor for interactive debugging which fur-
ther speeds program development. In addition the
BASIC/Debug Interpreter allows program execution
on power-up or reset, without operator interven-
tion.
Two kinds of memory exist in the Z8671 device:
on-chip registers and external ROM or RAM. The
BASIC/Debug interpreter is located in the 2K bytes
of on-chip ROM. Maximum addressing capability is
62K bytes of external program memory and 62K bytes
of data memory. In addition, 32 I/O lines, a 144-
byte register file, on-board UART and two coun-
ter/timers are provided.
Pin descr iptions and fund ions are t he same as
those for the Z8601/11 basic microcomputer
(Chapter
6).
1-4
1.7 ROHlESS MICROCOMPUTER (18681/82)
The Z8681 and Z8682 ROM less microcomputers provide
virtually all of the functions of the standard Z8
microcomputer without the need to mask-program
on-chip ROM. This microcomputer is similar to the
Z8601 version except that there is no on-chip pro-
gram memory. Unlike the RoMless development and
Protopack devices the Z8681/82 has no additional
address or address control lines nor does it carry
a plug-in piggyback memory module. Use of exter-
nal memory rather than internal ROM enables this
Z8 device to be used in low volume applications or
where code flexibility is required. The use of
Ports 0 and 1 to interface external memory leaves
16 to 24 lines for I/O.
Since Port 1 is dedicated as an 8-bit multiplexed
Address/Data bus, and Port 0 lines can be pro-
grammed as address bits, the resulting 16-bit
addresses can directly address up to 64K bytes of
memory for the Z8681 and 62K bytes for the Z8682.
(The Z8682 MCU cannot address the lower 2K bytes
of memory).
The address capabil it Y of the Z8681/82 can be
doubled
by programming output P3
4
of Port 3 as
Data Memory (OM) select signal. The two states of
this signal can be used with the 16-bit addresses
to identify two separate external address spaces,
thus increasing ext ernal address space to 128K
bytes for the Z8681 and 124K bytes for the Z8682.
Pin functions and descriptions for the Z8681/82
microcomputer can be found in Chapter 7.
1.8 APPLICATIONS
Z8 microcomputers are most often used in high-per-
formance, dedicated applicat ions. Such special-
ized functions were previously accomplished with
TTL logic, TTL logic plus a low-end MCU, or a
microprocessor and peripherals. Some typical
applications include:
• Disc drive controller
• Printer controller
• Terminals
• Modems
• Industrial controllers
• Key telephones
• Telephone switching systems
• Arcade games and intelligent home games
• Process control
• Intelligent instrumentation
• Automotive mechanisms

"- -
Following are brief descript ions for a few Z8
applications.
Printers. Input data (typically transmitted via a
terminal or computer) can be sent to the Z8 on
either a serial or parallel port. The Z8 then
transfers the data into the external RAM buffer
via another parallel port, where it can operate on
the data before output to the printing mechanism.
I alll~~y VV~.L V.&o,-,"
Disk. Disk operations are read or write, with
input received from either the disk or the compu-
ter. Data is transferred to the buffer memory a
sector (128, 256, 512, 1024 bytes) at a time via
the Z8, operated on as required, and subsequently
output to the disk or computer.
Terminal. Input is received from either the key-
board
or a computer. The Z8 device must maintain
at least an input buffer and often the screen RAM.
1-5