ZisWorks ARTIK-7 User manual

ZisWorks
“UHD TCON for Innolux Panels”
USER GUIDE
Docu ent version : 18 August 2017
“UHD TCON for Innolux Panels” User Guide ZisWorks.co Page 1/11

The latest version of this docu ent and others can be found at:
zisworks.co /downloads
CHANGELOG
Version 1.0 : 19 July 2017 : Beta release (not posted online)
Version 1.1 : 18 August 2017 : Minor changes for public posting
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Table of Contents
CHANGELOG...........................................................................................................................................2
DISCLAIMER...........................................................................................................................................4
OVERVIEW...............................................................................................................................................4
FEATURES AND SPECIFICATIONS......................................................................................................4
PANEL COMPATIBILITY........................................................................................................................5
BOARD OVERVIEW................................................................................................................................5
CONNECTOR PINOUTS.........................................................................................................................5
PIN DESCRIPTIONS................................................................................................................................7
REAR FACING RGB LEDS (NOT IMPLEMENTED YET)...................................................................7
SERIAL CONTROL INPUT.....................................................................................................................8
DEBUG MODE.........................................................................................................................................8
LVDS BIT MAPPING...............................................................................................................................9
LVDS PIXEL MAPPING..........................................................................................................................9
INPUT BEHAVIOR.................................................................................................................................10
ON SCREEN DISPLAY..........................................................................................................................10
FIRMWARE UPDATE (JTAG)...............................................................................................................11
FIRMWARE UPDATE (SOFTWARE) (NOT IMPLEMENTED YET)..................................................11
DISCLAIMER
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The ZWS UHD TCON is a ti ing controller board for select odels of UHD panels fro the
Innolux corporation. ZWS has no relationship with Innolux and has independently developed these
products. Use of the ZWS TCON ay violate so e Innolux design specifications, and as such, will
void any warranties of the panels.
OVERVIEW
The ZWS UHD TCON is an advanced ti ing controller board for select odels of UHD panels
fro the Innolux corporation. With a high-perfor ance Artix7 series FPGA fro Xilinx, the ZWS
UHD TCON offers syte flexibility with so e unique advantages over traditional TCONs. for the
sa e panels. High refresh rate support, an integrated latency-free integer scaling, and
FEATURES AND SPECIFICATIONS
• Two input ports, each with quad-channel LVDS
1• Onscreen display shows an autoscaling scrolling realti e graph of fra erates
1• 3840*2160 @ 120Hz (two input groups)
1• 3840*2160 @ 60Hz (one input group)
1• 3840*1080 @ 240Hz (two input groups)
1• 1920*1080 @ 240Hz (one input group)
1• 3840*720 @ 300Hz (two input groups)
1• 1280*720 @ 300Hz (one input group)
1• 3840*540 @ 480Hz (two input groups)
1• 960*540 @ 480Hz (one input group)
1• Up to 540MHz Pixel clock per input group
1• Up to 276KHz axi u line-rate
1• DE-Only video ti ing si plifies driving require ents
• Active per-bit deskewing of LVDS inputs
• Inter-channel skew of up to 2 pixels is tolerated
• Inter-port skew of up to 3 lines is tolerated
1• Dyna ic PLL reconfiguration for a wide range of video input frequencies
1• 10 bit input (te poral dithering + 8bit panel)
1• 10~14V Input voltage
1• High-quality power supplies with all-cera ic capacitor design
• Fir ware controlled power supplies enable support of ultiple panels of varying types.
• Six layer controlled i pedance PCB for highest signal integrity
• Output video synchronization signal for use with ZWS backlight drivers
• JTAG connection for fir ware update
• Additional connection for dyna ic rear-illu inating RGB LED strips (SK6812 type) (NOT
IMPLEMENTED YET)
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PANEL COMPATIBILITY
BOARD OVERVIEW
Top view:
There are four 41pin FI-RE41HS connectors, labeled INPUT 1~4. Additionally, there is an 8pin
PH2.0 connector on the left edge of the board, labeled “RGB STRIP”. This connection is intended for
use with the optional rear illu ination package. A labeled JTAG interface on the left edge enables
fir ware updates.
CONNECTOR PINOUTS
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PCB VERSION .
RGB STRIP
FI-RE4 HS PIN SIGNAL NAME
POWER INPUT
2 POWER INPUT
3 2.5V
4 ENABLE
5 FRAME_SYNC
6 SERIAL_OUTPUT
7 GROUND
8 GROUND
PANEL COMPATIBILITY
M238DCJ-E50 23.8” 9.5ms AAS WILL NOT WORK
M280DGJ-L30 28” ms TN FULLY SUPPORTED
V390DK -LS 39” 6.5ms MVA FULLY SUPPORTED
M3 5DJJ-K30 3 .5” 9.5ms MVA WILL NOT WORK
V420DK* 42” 9.5ms MVA UNTESTED
V500DK2 50” 6.5ms MVA UNTESTED
V580DK2 58” 6.5ms MVA UNTESTED

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PCB VERSION .
INPUT
FI-RE4 HS PIN SIGNAL NAME
POWER INPUT
2 POWER INPUT
3 POWER INPUT
4 POWER GROUND
5 POWER GROUND
6 POWER GROUND
7 FRAME_SYNC
8 SERIAL_OUTPUT
9 GROUND
0 LVDS EVEN A-
LVDS EVEN A+
2 LVDS EVEN B-
3 LVDS EVEN B+
4 LVDS EVEN C-
5 LVDS EVEN C+
6 GROUND
7 LVDS EVEN CLOCK-
8 LVDS EVEN CLOCK+
9 GROUND
20 LVDS EVEN D-
2 LVDS EVEN D+
22 LVDS EVEN E-
23 LVDS EVEN E+
24 SERIAL_INPUT
25 GROUND
26 LVDS ODD A-
27 LVDS ODD A+
28 LVDS ODD B-
29 LVDS ODD B+
30 LVDS ODD C-
3 LVDS ODD C+
32 GROUND
33 LVDS ODD CLOCK-
34 LVDS ODD CLOCK+
35 GROUND
36 LVDS ODD D-
37 LVDS ODD D+
38 LVDS ODD E-
39 LVDS ODD E+
40 GROUND
4 SHUTDOWN
PCB VERSION .
INPUT 2~4
FI-RE4 HS PIN SIGNAL NAME
POWER INPUT
2 POWER INPUT
3 POWER INPUT
4 POWER GROUND
5 POWER GROUND
6 POWER GROUND
7 FRAME_SYNC
8 NO-CONNECT
9 GROUND
0 LVDS EVEN A-
LVDS EVEN A+
2 LVDS EVEN B-
3 LVDS EVEN B+
4 LVDS EVEN C-
5 LVDS EVEN C+
6 GROUND
7 LVDS EVEN CLOCK-
8 LVDS EVEN CLOCK+
9 GROUND
20 LVDS EVEN D-
2 LVDS EVEN D+
22 LVDS EVEN E-
23 LVDS EVEN E+
24 NO-CONNECT
25 GROUND
26 LVDS ODD A-
27 LVDS ODD A+
28 LVDS ODD B-
29 LVDS ODD B+
30 LVDS ODD C-
3 LVDS ODD C+
32 GROUND
33 LVDS ODD CLOCK-
34 LVDS ODD CLOCK+
35 GROUND
36 LVDS ODD D-
37 LVDS ODD D+
38 LVDS ODD E-
39 LVDS ODD E+
40 GROUND
4 NO-CONNECT

PIN DESCRIPTIONS
Notes:
1) This line is connected to the 2.5V power rail through a 10oh resistor.
2) This line is connected to an FPGA I/O through a 1K oh resistor. Be careful when using this pin.
3) This line is connected to a level shifter. Maxi u input voltage is 16V, VIH in=2v, VIL ax=0.5v.
4) If unused, this signal ay be left open. There is a pulldown resistor on the board.
5) The LVDS video for at is a co bination physical electrical level specifications and an overlying
bit/pixel/line/fra e specification.
LVDS electrical specifications are su arized in the table below. Consult the Artix7 docu entation
for additional details.
REAR FACING RGB LEDS (NOT IMPLEMENTED YET)
The FPGA analyzes the near-edge pixels being sent to the panel and sends an appropriate data
strea for SK6812 type RGB-LED strips. When attached to the back of the LCD panel and allowed to
diffusely reflect off of a wall behind the panel, this a bient lighting appears to extend the screen
beyond the bezel. An optional kit includes the required driver board and LED strips.
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POWER INPUT POWER IN 0~ 4V DC SYSTEM INPUT POWER Notes
POWER GROUND PASSIVE GROUND
GROUND PASSIVE GROUND
2.5V POWER OUT 2.5V DC I/O VOLTAGE FOR THE FPGA
ENABLE OUTPUT 2.5V LOGIC HIGH WHEN THE PANEL IS TURNED ON 2
FRAME_SYNC OUTPUT 2.5V LOGIC LOW DURING VBLANKING, HIGH OTHERWISE 2
SERIAL_OUTPUT OUTPUT 2.5V LOGIC CONTROL SIGNAL FOR SK68 2 RGB LED STRIP 2
SERIAL_INPUT INPUT HV LOGIC SERIAL CONTROL INPUT 3, 4
SHUTDOWN INPUT HV LOGIC DISABLES THE DC/DC REGULATORS IF > 2V. 3, 4
LVDS * INPUT LVDS INPUT VIDEO SIGNALS 5
MIN 0.3V
COMMON MODE MAX .425V
INPUT
TYPICAL .2V
MIN 0. V
DIFFERENTIAL SWING MAX -
TYPICAL -

SERIAL CONTROL INPUT
The SERIAL_INPUT signal is used to set so e syste flags using a single-byte control
sche e. With the serial interface operating at 115200 baud, 8n1 configuration. The default values
correspond to the all-zeroes case.
If the serial input is held high for ore than five seconds without receiving additional bytes, the
syste will enter debug ode. If the input is held low or left floating, the syste will continue
operating with the previously set values, or if none were set, the default configuration. This aspect of
syste configuration is volatile, not being saved through power cycles.
DEBUG MODE
When in debug ode, the syste is turned on using an internal test pattern generator. Video inputs are
ignored. The test pattern generator cycles through the four supported resolutions, resulting in an i age
like this one:
TODO: use a better i age
here
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BIT POSITON BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT BIT 0
FIELD NAME CHECKSUM
DEFAULT OFF ON OFF OFF OFF VESA 0BIT -
FIRMWARE
UPDATE
ENABLE
RGB LED
STRINGS
DISABLE
TARGET
CROSSHAIR
ENABLE
ON SCREEN
DISPLAY
ENABLE
DEBUG
MODE
ENABLE
VESA /
JEIDA
MODE
SELECT
8BIT/ 0BIT
MODE
SELECT

LVDS BIT MAPPING
The apping of bits onto the LVDS signal lanes is shown here for both VESA and JEIDA
odes. For the color channels, bit 9 is the MSB and bit 0 is the LSB. REV signals are reserved and
are ignored by the syste . DE, VSY, and HSY are the standard data-enable, vertical-sync, and
horizontal-sync signals.
LVDS PIXEL MAPPING
There are four input connectors, labeled INPUT1, INPUT2, INPUT3, and INPUT4, with each
input connector containing two LVDS channels. These eight channels can be called E1, O1, E2, O2,
E3, O3, E4, and O4. Within each group, four channels are interleaved to for the inco ing pixel
strea . Beginning with pixel 0 in the upper left, E1 carries pixels 0, 4, 8, 12…, E2 carries 1, 5, 9,
13…, O1 carries 2, 6, 10, 14…, and O2 carries 3, 7, 11, 15... TODO: verify if correct ordering
“UHD TCON for Innolux Panels” User Guide ZisWorks.co Page 9/11

INPUT BEHAVIOR
Inputs E1, O1, E2, and O2 belong to the pri ary group, and inputs E3, O3, E4, and O4 belong
to the secondary group. All clocks within a group ust be atched in frequency, but ay be offset in
phase. If two groups are si ultaneously active, the pri ary group will be displayed on the left hand
side of the screen with the secondary on the right. If only one group is active, it will occupy the entire
screen. If two groups are used si ultaneously, it is absolutely critical that the input strea s be
vertically synchronized within +/- 3 lines of each other.
Integer scaling of 1:1, 1:2, 1:3, and 1:4 is supported. Only exact 1:1, 1:2, 1:3, and 1:4 appings
are allowed vertically. Video strea s which are not exactly 2160, 1080, 720, or 540 lines tall will be
replaced with a test pattern and warning. Video strea s with excessive width will be displayed with a
warning. Nonexact horizontal scaling will result in a horizontally centered i age with unused display
area blacked-out.
Horizontal and vertical scaling are independent of each other, so non-square pixels are allowed.
This situation can be useful, for exa ple, in a 3840*1080@240Hz scenario, if the host syste is ade
aware of the pixel aspect ratio.
If the input is detected as invalid or partially invalid, a test pattern or overlaid warning will be
shown on the screen to alert the user to the proble .
DE-Only ti ing ode is supported, with the HSYNC and VSYNC signals ignored internally.
Any duration of DE being low for ore than 8 clocks is considered the end of the current line, and any
duration of DE staying low for ore than 510 clocks is considered the end of the current fra e. There
is no set li it for the axi u vertical blanking duration. The syste does not require a consistent
blanking interval, variable blanking intervals are accepted.
ON SCREEN DISPLAY
An on-screen-display shows the selected panel, fir ware version, and a realti e autoscaling
scrolling graph of the fra erate of the ost recent 253 fra es, with ini u and axi u values
shown. The OSD is alpha-blended with the video strea and overlaid in the upper left corner of the
display.
e does not require a
consistent blanking
interval, variable
blanking intervals are
accepted.
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