AAC Microtec Sirius TCM User manual

Document number
205065
Version
Rev. N
Issue date
2019-02-04
Sirius OBC and TCM User Manual
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Sirius OBC and TCM User Manual
Rev. N
© ÅAC Microtec 2016-2019
ÅAC Microtec AB owns the copyright of this document which is supplied in confidence and which shall
not be used for any purpose other than for which it is supplied and shall not in whole or in part be
reproduced, copied, or communicated to any person without written permission from the owner.

Document number
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Version
Rev. N
Issue date
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Sirius OBC and TCM User Manual
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REVISION LOG
Rev
Date
Change description
A
2016-10-25
First release, drafted from 204911 Sirius Breadboard User Manual
Rev L
B
2016-12-15
Updated after editorial updates
C
2017-01-03
Release with updates to the following sections:
•Massmem (new API with DMA)
•Error manager (IOCTL API)
•ADC (channel table update, channel limitation)
•Sirius TCM (TM/TC defaults, API updates {errno, MMStatus,
TMTSStatus, }, removed limitations)
•Bootrom (extended description)
•SCET (extended description, new API)
•UART32 (removed)
•CCSDS (interrupt API deprecation)
•NVRAM (EDAC/non-EDAC modes described)
D
2017-02-01
Release with updates to the following sections:
•Sirius TCM (Extra info sections, TMBRSet->TMBRControl)
•Mass memory (IOCTL API, error inject info)
•SCET (Clarify threshold)
E
2017-03-01
Release with updates to the following sections:
•ADC (minor updates to clock div limits)
•Setup and operation (find debugger serial, use of multiple
debuggers)
F
2017-04-18
Release with updates to the following sections:
•CCSDS (new API)
•Sirius TCM (new timesync API, NVRAM table updated, new
segment sizing for partitions)
G
2017-10-31
Release with updates to the following sections:
•Fault tolerant design (new section)
•CCSDS (updated API)
•Mass memory (updated API)
•Sirius TCM (new mass memory partition configuration
behaviour & RMAP API)
•System flash (new)
H
2018-03-07
Release with updates to the following sections:
•Introduction
•Equipment information
•Sirius TCM (updated API and formatting)
•NVRAM (updated API)
I
2018-04-16
Release with updates of the following sections:
•Software upload (new)
•NVRAM (updated EDAC error reporting API)
J
2018-06-28
Release with updates of the following sections:
•SCET, UART, WDT, NVRAM and SpW (updated API)
•Mass Memory Handling (auto-padding)
•Removed chapter with connector pinout

Document number
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Version
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Sirius OBC and TCM User Manual
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K
2018-10-26
Release with updates to the following sections:
•Re-initialising the NVRAM (new)
•Mass Memory (new optional runtime-size API, new chip type
support)
•System flash (deprecate spare area writes without
EDAC/interleaving)
•Sirius TCM (config fallback parameters, direct partition limits,
new PUS 2.2 service, RMAP transid allocation
recommendations, limited direct partition utilisation
recommendations)
M
2018-12-04
Release with updates to the following sections:
•Software development (how to build silent BSP)
•TM/TC-structure and COP-1 (new)
•System-on-Chip defitions (system flash bad block table
reserved location in NVRAM)
•NVRAM (safe/update area address corrections)
•Sirius TCM-S (bit error correction information for
telecommands)
N
2019-02-01
Release with updates to the following sections:
•Sirius TCM (noted possible pointer reset to address 0 on
massmem handler recovery)

Document number
205065
Version
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Issue date
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Sirius OBC and TCM User Manual
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TABLE OF CONTENT
1. INTRODUCTION............................................................................................................... 9
1.1. Applicable releases ........................................................................................................................................ 9
1.2. Intended users ................................................................................................................................................ 9
1.3. Getting support............................................................................................................................................... 9
1.4. Reference documents .................................................................................................................................. 10
2. EQUIPMENT INFORMATION ..........................................................................................11
2.1. System Overview with peripherals ............................................................................................................. 11
2.2. Fault tolerant design .................................................................................................................................... 12
3. SETUP AND OPERATION...............................................................................................14
3.1. User prerequisites ........................................................................................................................................ 14
3.2. Connecting cables to the Sirius products.................................................................................................. 15
3.3. Installation of toolchain ............................................................................................................................... 16
3.3.1. Supported Operating Systems ................................................................................................................. 16
3.3.2. Installation Steps...................................................................................................................................... 16
3.4. Installing the Board Support Package (BSP) ............................................................................................. 17
3.5. Deploying a Sirius application .................................................................................................................... 17
3.5.1. Establish a debugger connection to the Sirius products........................................................................... 17
3.5.2. Setup a serial terminal to the device debug UART................................................................................... 18
3.5.3. Loading an application ............................................................................................................................. 19
3.5.4. Using multiple debuggers on the same PC .............................................................................................. 19
3.6. Programming an application (boot image) to system flash...................................................................... 20
3.7. Re-initialising the NVRAM............................................................................................................................ 21
4. SOFTWARE DEVELOPMENT.........................................................................................21
4.1. RTEMS step-by-step compilation................................................................................................................ 22
4.1.1. Compiling the BSP with debug output removed....................................................................................... 22
4.2. Software disclaimer of warranty ................................................................................................................. 23
5. RTEMS.............................................................................................................................23
5.1. Introduction................................................................................................................................................... 23
5.2. Watchdog ...................................................................................................................................................... 25
5.2.1. Description ............................................................................................................................................... 25
5.2.2. RTEMS API.............................................................................................................................................. 25
5.2.3. Usage description .................................................................................................................................... 26
5.3. Error Manager ............................................................................................................................................... 29
5.3.1. Description ............................................................................................................................................... 29
5.3.2. RTEMS API.............................................................................................................................................. 29
5.3.3. Usage....................................................................................................................................................... 34
5.3.4. Limitations................................................................................................................................................ 35
5.4. SCET.............................................................................................................................................................. 36
5.4.1. Description ............................................................................................................................................... 36
5.4.2. General purpose triggers ......................................................................................................................... 36
5.4.3. Pulse-Per-Second (PPS) signals ............................................................................................................. 36
5.4.4. RTEMS API.............................................................................................................................................. 37
5.4.5. Usage description .................................................................................................................................... 42
5.4.6. Limitations................................................................................................................................................ 45
5.5. UART.............................................................................................................................................................. 46

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5.5.1. Description ............................................................................................................................................... 46
5.5.2. RTEMS API.............................................................................................................................................. 46
5.5.3. Usage description .................................................................................................................................... 50
5.5.4. Limitations................................................................................................................................................ 51
5.6. Mass memory................................................................................................................................................ 51
5.6.1. Description ............................................................................................................................................... 51
5.6.2. Data Structures ........................................................................................................................................ 52
5.6.3. RTEMS API.............................................................................................................................................. 53
5.6.4. Usage description .................................................................................................................................... 61
5.6.5. Error injection........................................................................................................................................... 65
5.6.6. Limitations................................................................................................................................................ 65
5.7. Spacewire...................................................................................................................................................... 66
5.7.1. Description ............................................................................................................................................... 66
5.7.2. RTEMS API.............................................................................................................................................. 66
5.7.3. Usage description .................................................................................................................................... 71
5.8. GPIO............................................................................................................................................................... 73
5.8.1. Description ............................................................................................................................................... 73
5.8.2. RTEMS API.............................................................................................................................................. 73
5.8.3. Usage description .................................................................................................................................... 76
5.8.4. Limitations................................................................................................................................................ 77
5.9. CCSDS........................................................................................................................................................... 78
5.9.1. Description ............................................................................................................................................... 78
5.9.2. Non-blocking ............................................................................................................................................ 78
5.9.3. Blocking ................................................................................................................................................... 79
5.9.4. Buffer data containing TM Space packets................................................................................................ 79
5.9.5. RTEMS API.............................................................................................................................................. 79
5.9.6. Usage description .................................................................................................................................... 86
5.10. ADC.............................................................................................................................................................. 88
5.10.1. Description ............................................................................................................................................. 88
5.10.2. RTEMS API............................................................................................................................................ 89
5.10.3. Usage description .................................................................................................................................. 92
5.10.4. Limitations.............................................................................................................................................. 93
5.11. NVRAM ........................................................................................................................................................ 94
5.11.1. Description ............................................................................................................................................. 94
5.11.2. EDAC mode ........................................................................................................................................... 94
5.11.3. Non-EDAC mode ................................................................................................................................... 94
5.11.4. RTEMS API............................................................................................................................................ 94
5.11.5. Usage description .................................................................................................................................. 97
5.12. System flash ............................................................................................................................................... 99
5.12.1. Description ............................................................................................................................................. 99
5.12.2. Data structure types............................................................................................................................... 99
5.12.3. RTEMS API............................................................................................................................................ 99
5.12.4. Usage description ................................................................................................................................ 104
5.12.5. Debug detect........................................................................................................................................ 106
5.12.6. Limitations............................................................................................................................................ 106
6. SPACEWIRE ROUTER..................................................................................................107
7. SIRIUS TCM...................................................................................................................108
7.1. Description.................................................................................................................................................. 108
7.2. Block diagram............................................................................................................................................. 109
7.3. TCM-S application overview ...................................................................................................................... 109

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7.4. Configuration .............................................................................................................................................. 110
7.4.1. Creating and writing a new configuration ............................................................................................... 114
7.4.2. Fallback NVRAM parameters................................................................................................................. 115
7.5. Telemetry..................................................................................................................................................... 117
7.6. Telecommands ........................................................................................................................................... 117
7.6.1. Pulse commands.................................................................................................................................... 118
7.6.2. COP-1.................................................................................................................................................... 118
7.7. Time Management ...................................................................................................................................... 119
7.7.1. TM time stamps...................................................................................................................................... 119
7.8. Error Management and System Supervision ........................................................................................... 119
7.9. Mass Memory Handling.............................................................................................................................. 119
7.9.1. Partition configuration ............................................................................................................................ 120
7.9.2. Recovery................................................................................................................................................ 124
7.10. ECSS standard services .......................................................................................................................... 125
7.10.1. PUS-1 Telecommand verification service ............................................................................................ 125
7.10.2. PUS-2 Distributing Register Load Command....................................................................................... 125
7.10.3. PUS-2 Device Command Distribution Service ..................................................................................... 125
7.10.4. PUS-2 Distributing Device Command .................................................................................................. 126
7.11. Custom services....................................................................................................................................... 126
7.11.1. PUS-130 Software upload.................................................................................................................... 126
7.12. Spacewire RMAP ...................................................................................................................................... 127
7.12.1. Input..................................................................................................................................................... 127
7.12.2. Output .................................................................................................................................................. 128
7.12.3. Status code in reply messages ............................................................................................................ 129
7.12.4. RMAP input address details................................................................................................................. 129
7.12.5. RMAP output address details............................................................................................................... 144
7.13. Limitations ................................................................................................................................................ 144
8. SYSTEM-ON-CHIP DEFINITIONS .................................................................................145
8.1. Memory mapping........................................................................................................................................ 145
8.2. Interrupt sources ........................................................................................................................................ 146
8.3. SCET timestamp trigger sources .............................................................................................................. 146
8.4. Boot images and boot procedure.............................................................................................................. 147
8.4.1. Description ............................................................................................................................................. 147
8.4.2. Block diagram ........................................................................................................................................ 147
8.4.3. Usage description .................................................................................................................................. 147
8.4.4. Limitations.............................................................................................................................................. 148
8.5. Reset behaviour.......................................................................................................................................... 148
8.6. General synchronize method .................................................................................................................... 148
8.7. Pulse command inputs .............................................................................................................................. 148
8.8. SoC information map ................................................................................................................................. 149
9. SOFTWARE UPLOAD...................................................................................................150
9.1. Description.................................................................................................................................................. 150
9.2. Block diagram............................................................................................................................................. 150
9.3. CCSDS API –custom PUS service 130..................................................................................................... 151
9.3.1. Subtype 1 –Image transfer start............................................................................................................ 152
9.3.2. Subtype 2 –Image data ......................................................................................................................... 152
9.3.3. Subtype 3 –Verify uploaded image ....................................................................................................... 153
9.3.4. Subtype 4 –Write uploaded image ........................................................................................................ 153
9.3.5. Subtype 5 –Calculate CRC in flash....................................................................................................... 154
9.4. Software API ............................................................................................................................................... 155

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9.4.1. int32_t swu_init(…) ................................................................................................................................ 155
9.4.2. int32_t swu_segment_add(…) ............................................................................................................... 155
9.4.3. int32_t swu_check(…)............................................................................................................................ 156
9.4.4. int32_t swu_update(…) .......................................................................................................................... 156
9.4.5. int32_t swu_flash_check(…) .................................................................................................................. 157
9.5. Usage description....................................................................................................................................... 157
9.6. Limitations .................................................................................................................................................. 157
10. TM/TC-STRUCTURE AND COP-1...............................................................................158
10.1. SCID........................................................................................................................................................... 158
10.2. APID........................................................................................................................................................... 158
10.3. Virtual Channel Allocation ....................................................................................................................... 158
10.3.1. Uplink ................................................................................................................................................... 158
10.3.2. Downlink .............................................................................................................................................. 158
10.4. Uplink Channel Coding, Randomization and Synchronization ............................................................ 158
10.4.1. Channel Coding ................................................................................................................................... 158
10.4.2. Randomization ..................................................................................................................................... 158
10.4.3. Channel Synchronization ..................................................................................................................... 158
10.5. Downlink Channel Coding, Randomization and Synchronization........................................................ 158
10.5.1. Channel Coding ................................................................................................................................... 158
10.5.2. Randomization ..................................................................................................................................... 159
10.5.3. Synchronization.................................................................................................................................... 159
10.6. Telecommand format ............................................................................................................................... 159
10.6.1. Telecommand Transfer Frame............................................................................................................. 159
10.6.2. Transfer Frame Header........................................................................................................................ 160
10.6.3. Transfer Frame Data Field ................................................................................................................... 161
10.6.4. Frame Error Control Field .................................................................................................................... 162
10.6.5. Telecommand Packet .......................................................................................................................... 162
10.7. Telemetry Format...................................................................................................................................... 164
10.7.1. Telemetry Transfer Frame ................................................................................................................... 164
10.7.2. Transfer Frame Primary Header .......................................................................................................... 164
10.7.3. Transfer Frame Secondary Header...................................................................................................... 165
10.7.4. Transfer Frame Data Field ................................................................................................................... 166
10.7.5. Operational control field ....................................................................................................................... 166
10.7.6. Frame Error Control Field .................................................................................................................... 167
10.7.7. Telemetry Packet ................................................................................................................................. 167
10.7.8. Telemetry Packet Header .................................................................................................................... 168
10.7.9. Data Field Header................................................................................................................................ 168
10.7.10. Source Data ....................................................................................................................................... 169
10.7.11. Spare ................................................................................................................................................. 169
10.7.12. Packet Error Control........................................................................................................................... 169
10.8. FARM-parameters..................................................................................................................................... 169
10.8.1. FARM_Sliding_Window_Width(W)....................................................................................................... 169
10.8.2. FARM_Positive_Window_Width(PW) .................................................................................................. 169
10.8.3. FARM_Negative_Window_Width(NW)................................................................................................. 169
11. UPDATING THE SIRIUS FPGA...................................................................................170
11.1. Prerequisite hardware.............................................................................................................................. 170
11.2. Prerequisite software ............................................................................................................................... 170
11.3. Generation of encryption key .................................................................................................................. 170
11.4. Step by step guide.................................................................................................................................... 170

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12. MECHANICAL DATA ..................................................................................................172
13. GLOSSARY .................................................................................................................173

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1. Introduction
This manual describes the functionality and usage of the ÅAC Sirius OBC and Sirius TCM
products. The Sirius OBC or Sirius TCM differ in certain areas such as the SoC, interfaces
etc. but can mostly be described with the same functionality and will throughout this
document be referred to as “the Sirius products” when both products are referred at the
same time.
1.1. Applicable releases
This version of the manual is applicable to the following software releases:
Sirius OBC 1.5.0
Sirius TCM 1.5.1
1.2. Intended users
This manual is written for software engineers using the ÅAC Sirius products. The electrical
and mechanical interface is described in more detail in the electrical and mechanical ICD
documents [RD10] and [RD11].
1.3. Getting support
If you encounter any problem using the Sirius products or another ÅAC product please use
the following address to get help:
Email: [email protected]

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1.4. Reference documents
RD#
Document ref
Document name
RD1
https://openrisc.io/architecture
OpenRISC 1000 Architecture
Manual
RD2
ECSS-E-ST-50-12C
SpaceWire –Links, nodes,
routers and networks
RD3
ECSS-E-ST-50-52C
SpaceWire –Remote memory
access protocol
RD4
ECSS-E-70-41A
Ground systems and
operations –Telemetry and
telecommand packet utilization
RD5
SNLS378B
PC16550D Universal
Asynchronous
Receiver/Transmitter with
FIFOs
RD6
AD7173-8, Rev. A
Low Power, 8-/16-Channel,
31.25 kSPS, 24-Bit, Highly
Integrated Sigma-Delta ADC
RD7
Edition 4.11
RTEMS BSP and Device
Driver Development Guide
RD8
CCSDS 132.0-B-2
TM Space Data Link Protocol
RD9
CCSDS 232.0-B-2
TC Space Data Link Protocol
RD10
205088
Sirius OBC electrical and
mechanical ICD
RD11
205089
Sirius TCM electrical and
mechanical ICD
RD12
SS-EN 61340-5-1
Electrostatics - Part 5-1:
Protection of electronic
devices from electrostatic
phenomena - General
requirements
RD13
Edition 4.11
RTEMS POSIX Users Manual
RD14
CCSDS 201.0-B-3
TC Channel Service

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2. Equipment information
The Sirius OBC and Sirius TCM products are depicted in Figure 3-1 and Figure 3-2.
In addition to the external interfaces, the Sirius products also include both a debugger
interface for downloading and debugging software applications and a JTAG interface for
programming the FPGA during manufacturing.
The FPGA firmware implements a SoC centered around a 32 bit OpenRISC Fault Tolerant
processor [RD1] running at a system frequency of 50 MHz and with the following key
peripherals:
•Error manager - error handling, tracking and log of e.g. memory error detection.
•SDRAM controller - 64 MB data + 64 MB EDAC running @100MHz
•Spacecraft Elapsed Timer (SCET) - including a PPS (Pulse Per Second) time
synchronization interface for accurate time measurement with a resolution of 15 µs
•SpaceWire - including a three-port SpaceWire router, for communication with
external peripheral units
•UARTs - RS422 and RS485 line drivers on the board with line driver mode set by
software.
•GPIOs
•Watchdog - a fail-safe mechanism to prevent a system lockup
•System flash - 2 GB of EDAC-protected flash for storing boot images in multiple
copies
•Pulse command inputs - for reset to a specific software image
•NVRAM - for storage of metadata and other data that requires a large number of
writes that shall survive loss of power
For the Sirius TCM the following additional peripherals are included in the SoC:
•CCSDS - communications IP with RS422/LVDS interfaces for radio communication
and an UMBI interface for communication with EGSE
•Mass memory - 16GB of EDAC-protected NAND flash based, for storage of
mission critical data.
For the Sirius OBC, an Analog interface is included for external analog measurements.
The input power supply provided to the Sirius products shall be between +4.5 and +16 VDC.
The power consumption is highly dependent on peripheral loads and ranges from 0.8 W to
2 W.
2.1. System Overview with peripherals
Figure 2-1 depicts a System-on-Chip (SoC) overview including the related peripherals of the
Sirius OBC and Sirius TCM products. The figure shows what parts that are included for
which products.

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FPGA
FPU
OpenRISC
1200FT
I/D Cache
I2C
UART
GPIO
CCSDS
Memory
controller
System
flash
controller
Flash
controller
SpaceWire
DMA
Control
Watchdog
Debug
Unit
SCET
Error
manager
2x 64MB
SDRAM
2 GB System
Flash
Radio Interfaces
RS422/LVDS RS422/RS485 JTAG/DEBUG
Pulse CMDUMBI/EGSEETHERNET GPIO
ADC
(Housekeeping)
Ethernet
10/100
ADC
controller
OBC / TCM
NVRAM
Analog inputs
NVRAM
TCM TCM/OBC Future option
16 GB Flash
OBC
PPS
Figure 2-1 - The Sirius OBC / Sirius TCM SoC Overview
2.2. Fault tolerant design
The Sirius OBC and Sirius TCM are both fault tolerant by design to withstand the
environmental loads that the modules are subjected to when used in space applications.
The following error mitigation techniques are used.
•Continuous EDAC scrubbing of SDRAM data with at least 1 bit error correction and
2 bit error detection for each 16-bit word. Non-correctable errors cause a processor
interrupt to allow the software to handle the error differently depending on in which
section of the memory it appeared, unless the error appear in the execution path
(see below).
•EDAC checking of instructions before execution and on data used in the instruction
(at least 1 bit error correction and 2 bit error detection as described in the previous
point). Non-correctable errors cause automatic reboot.
•Parity checking of Instruction and Data caches when they are enabled. Errors
cause a processor interrupt with a cache reload as the default error handling.
•Parity checking of peripheral FIFOs. Errors cause processor interrupt.
•EDAC checking on system flash with double bit error correction and extended bit
error detection in combination with interleaving that corrects bursts with up to 16
bits in error.
•Triple Modular Redundancy (TMR) on all FPGA flip-flops

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•All software stored in boot flash is, in addition to the EDAC protection of the flash
data, encoded with a header for checksum and length. Each boot image is stored
in three copies to allow for an automatic fallback option if the ECC and/or length
check fails on one copy.
•Watchdog, tripping leads to automatic reboot of the device.
•Advanced Error Manager keeping the detected failures during reset/reboot for later
analysis.

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3. Setup and operation
3.1. User prerequisites
The following hardware and software is needed for the setup and operation of the Sirius
products.
PC computer
•1 GB free space for installation (minimum)
•Debian 8 64-bit with super user rights
•USB 2.0
JTAG debugger
•ÅAC JTAG debugger hardware including harness
Recommended applications and software
•Installed serial communication terminal, e.g. gtkterm or minicom
•GPG for encryption/decryption of files containing sensitive data
•Host build system, e.g. the debian package build-essential
•The following software is installed by the ÅAC toolchain package
oGCC, C compiler for OpenRISC
oGCC, C++ compiler for OpenRISC
oGNU binutils and linker for OpenRISC
oCustom openocd binary designed for OpenRISC
For FPGA update capabilities
•Microsemi FlashPro Express v11.8, http://www.microsemi.com/products/fpga-
soc/design-resources/programming/flashpro#software
•FlashPro5 programmer

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3.2. Connecting cables to the Sirius products
Figure 3-1 –ÅAC Sirius OBC with connector naming
Figure 3-2 - ÅAC Sirius TCM with connector naming
•All products and ingoing material shall be handled with care to prevent damage of
any kind.
JTAG-RTL
DEBUG-SW
SPW1
SPW2
UART0-2
PWR
UART3-4
DIGITAL
ANALOG
JTAG-RTL
DEBUG-SW
UMBI
SPW1
UART0-2
PWR
TRX2-LVDS
TRX1-RS422
DIGITAL
PULSE
SPW2

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•ESD protection and other protective measures shall be considered. Handling
should be performed according to applicable ESD requirement standards such as
[RD12] or equivalent.
•Ensure that all mating connectors have the same zero reference (ground) before
connecting.
•Connect the nano-D connector to the PWR connector with 4.5 - 16 V DC. The units
will nominally draw about 260-300 mA @5V DC.
•The ÅAC debugger is mainly used for development of custom software for the
Sirius OBC or Sirius TCM and has both a debug UART for monitoring and a JTAG
interface for debug capabilities. It is also used for programming an image to the
system flash memory. For further information refer to Chapter 3.6. When it is to be
used, connect the 104452 ÅAC Debugger to the DEBUG-SW connector. Connect
the adapter USB-connector to the host PC.
•For FPGA updating only: Connect a FlashPro5 programmer to the JTAG-RTL
connector using the 104470 FPGA programming cable assembly. For further
information how to update the SoC refer to Chapter 11.
•For connecting the SpaceWire interface, connect the nano-D connector to
connector SPW1 or SPW2.
For more detailed information about the connectors, see [RD10] and [RD11].
3.3. Installation of toolchain
This chapter describes instructions for installing the aac-or1k-toolchain.
3.3.1. Supported Operating Systems
•Debian 8 64-bit
When installing Debian, we recommend using the “netinst” (network install) method. Images
for installing are available via https://www.debian.org/releases/jessie/debian-installer/
In order to install the toolchain below, a Debian package server mirror must be added, either
in the installation procedure (also required during network install) or after installation. For
adding a package server mirror after installation, follow the instructions at
https://www.debian.org/doc/manuals/debian-faq/ch-uptodate.en.html
3.3.2. Installation Steps
1. Add the ÅAC Package Archive Server
Open a terminal and execute the following command:
sudo gedit /etc/apt/sources.list.d/aac-repo.list
This will open a graphical editor; add the following lines to the file and then save and
close it:
deb http://repo.aacmicrotec.com/archive/ aac/
deb-src http://repo.aacmicrotec.com/archive/ aac/
Add the key for the package archive as trusted by issuing the following command:

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wget -O - http://repo.aacmicrotec.com/archive/key.asc | sudo
apt-key add -
The terminal will echo "OK" on success.
2. Install the Toolchain Package
Update the package cache and install the toolchain by issuing the following commands:
sudo apt-get update
sudo apt-get install aac-or1k-toolchain
Note: The toolchain package is roughly 1GB uncompressed, downloading/installing it
will take some time.
3. Setup
In order to use the toolchain commands, the shell PATH variable needs to be set to
include them, this can be done either temporarily for the current shell via
source /opt/aac/aac-path.sh
or permanently by editing the ~/.bashrc (or equivalent) file
gedit ~/.bashrc
and adding the following snippet at the end of the file, and then saving and closing it:
# AAC OR1k toolchain PATH setup
if [ -f /opt/aac/aac-path.sh ]; then
. /opt/aac/aac-path.sh >/dev/null
fi
3.4. Installing the Board Support Package (BSP)
The BSP can be downloaded from http://repo.aacmicrotec.com/bsp. Simply extract the
tarball aac-or1k-xxx-x-bsp-y.tar.bz2 to a directory of your choice (xxx-x depends on your
intended hardware target - Sirius OBC or Sirius TCM and y matches the current version
number of that BSP).
The newly created directory aac-or1k-xxx-x-bsp now contains the drivers for both bare-metal
applications and RTEMS. See the included README and chapter 4.1 for build instructions.
3.5. Deploying a Sirius application
3.5.1. Establish a debugger connection to the Sirius products
The Sirius products are shipped with debuggers who connect to a PC via USB. To interface
the Sirius products, the Open On-Chip Debugger (OpenOCD) software is used. A script
called run_aac_debugger.sh is shipped with the toolchain package which starts an
OpenOCD server for gdb to connect to.
1. Connect the Sirius products according to section 3.2 and switch on the power
supply.

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2. Start the run_aac_debugger.sh script from a terminal.
3. If the printed message is according to Figure 3-3, the connection is working.
Figure 3-3 - Successful OpenOCD connection to the Sirius products
The line
target state: halted
must be displayed in the output, otherwise the OpenOCD connection has failed and the
board must be power-cycled.
3.5.2. Setup a serial terminal to the device debug UART
The device debug UART may be used as a debug interface for printf output etc.
A serial communication terminal such as minicom or gtkterm is necessary to communicate
with the Sirius product, using these settings:
Baud rate: 115200
Data bits: 8
Stop bits: 1
Parity: None
Hardware flow control: Off
On a clean system with no other USB-to-serial devices connected, the serial port will appear
as /dev/ttyUSB1. However, the numbering may change when other USB devices are
connected and you have to make sure you're using the correct device number to
communicate to the board's debug UART.
On Debian 8, a more foolproof way of identifying the terminal to use is the by-id mechanism.
Once you've identified the serial number of your debugger (see 3.5.4.), you can connect to it

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using the autocreated path at /dev/serial/by-id/. The debug UART is identified as
usb-AAC_Microtec_JTAG_Debugger_FTZ7QCMF-if01-port0, where FTZ7QCMF is
the serial number in this case. Make sure you use the if01 number and not if00 as this is
consumed by the OpenOCD server later.
3.5.3. Loading an application
An application can either be loaded only to the volatile memory, which is easier and typically
used during the development stages, or to NAND flash (see section 3.6). This is done using
gdb.
1.a) Start gdb with the following command from a shell for a bare-metal environment
or1k-aac-elf-gdb
or
1.b) Start gdb with the following command from a shell for an RTEMS environment
or1k-aac-rtems4.11-gdb
2. When gdb has opened successfully, connect to the hardware through the
OpenOCD server using the gdb command
target remote localhost:50001
3. To run an executable program in hardware, first specify its name using the gdb
command file. Make sure the application is in ELF format.
file path/to/binary_to_execute
4. Now it needs to be uploaded onto the target RAM
load
5. In the gdb prompt, type cto start to run the application
3.5.4. Using multiple debuggers on the same PC
In order to use multiple debuggers connected to the same PC, each instance of OpenOCD
must be configured to connect to the specific debugger serial number and to use unique
ports. Support for this is included in the run_aac_debugger.sh script.
In order to determine the serial number for a specific device, run the following command
before connecting the debugger
sudo tail -f /var/log/kern.log
which initially prints the last 10 lines of the kernel log file (which can be ignored). When
plugging in the debugger USB cable into the PC, this should produce new output similar to
[363061.959120] usb 1-1.3.3.3: new full-speed USB device number 15
using ehci_hcd
[363062.058152] usb 1-1.3.3.3: New USB device found, idVendor=0403,
idProduct=6010
[363062.058176] usb 1-1.3.3.3: New USB device strings: Mfr=1,
Product=2, SerialNumber=3
[363062.058194] usb 1-1.3.3.3: Product: JTAG Debugger
[363062.058207] usb 1-1.3.3.3: Manufacturer: AAC Microtec
[363062.058220] usb 1-1.3.3.3: SerialNumber: FTZ7QCMF

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where FTZ7QCMF is the serial number for the debugger.
The GDB, telnet and TCL ports must be set to a unique value in the Linux user-available
range 1025-65535, the defaults are GDB: 50001, telnet: 4444, TCL: 6666.
For example, two debuggers with serial numbers FTZ7QCMF and FTZ7IB10 can be setup
via
run_aac_debugger.sh -s FTZ7QCMF -g 50001 -t 4444 -p 6666
run_aac_debugger.sh -s FTZ7IB10 -g 50002 -t 4445 -p 6667
Two instances of GDB can then be opened, and connected to the different debuggers via
target remote localhost:50001
and
target remote localhost:50002
respectively. Only the GDB port is used when connecting from GDB.
3.6. Programming an application (boot image) to system flash
This chapter describes how to program the NAND flash memory with a selected boot image.
To achieve this, the boot image binary is bundled together with the NAND flash
programming application during the latter's compilation. The NAND flash programming
application is then uploaded to the target and started just as an ordinary application using
gdb. The maximum allowed size for the boot image for is 16 MB. The nandflash_program
application can be found in the BSP.
The below instructions assume that the toolchain is in the PATH, see section 3.3 for how to
accomplish this.
1. Compile the boot image binary according to the rules for that program.
2. Ensure that this image is in a binary-only format and not ELF. This can be
accomplished with the help of the GCC objcopy tool included in the toolchain:
Note that Xis to be replaced according to what your application has been compiled
against, either elf for a bare-metal application or rtems4.11 for the RTEMS variant.
or1k-aac-X-objcopy -O binary boot_image.elf boot_image.bin
3. See chapter 3.4 for installing the BSP and enter
cd path/to/bsp/aac-or1k-xxx-x-bsp/src/nandflash_program/src
4. Now, compile the nandflash-program application, bundling it together with the boot image
binary.
make nandflash-program.elf PROGRAMMINGFILE=/path/to/boot_image.bin
5. Load the nandflash-program.elf onto the target RAM with the help of gdb and
execute it, see section 3.5.3. Follow the instructions on screen and when it's ready,
reboot the board by a reset or power cycle.