Achronix PCIe Accelerator-6D Card User manual

Speedster FPGAs www.achronix.com 1
PCIe Accelerator-6D Card
User Guide (UG074)
Speedster FPGAs

PCIe Accelerator-6D Card User Guide (UG074)
2www.achronix.com Speedster FPGAs
Copyrights, Trademarks and Disclaimers
Copyright © 2017 Achronix Semiconductor Corporation. All rights reserved. Achronix, Speedcore, Speedster,
and ACE are trademarks of Achronix Semiconductor Corporation in the U.S. and/or other countries All other
trademarks are the property of their respective owners. All specifications subject to change without notice.
NOTICE of DISCLAIMER: The information given in this document is believed to be accurate and reliable.
However, Achronix Semiconductor Corporation does not give any representations or warranties as to the
completeness or accuracy of such information and shall have no liability for the use of the information contained
herein. Achronix Semiconductor Corporation reserves the right to make changes to this document and the
information contained herein at any time and without notice. All Achronix trademarks, registered trademarks,
disclaimers and patents are listed at http://www.achronix.com/legal.
Achronix Semiconductor Corporation
2953 Bunker Hill Lane, Suite 101
Santa Clara, CA 95054
USA
Phone : 855.GHZ.FPGA (855.449.3742)
E-mail : [email protected]

PCIe Accelerator-6D Card User Guide (UG074)
Speedster FPGAs www.achronix.com 3
Table of Contents
Chapter - 1: PCIe Accelerator-6D Kit Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
PCIe Accelerator-6D Kit Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
PCIe Accelerator-6D Kit Uses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
PCIe Accelerator-6D Board Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Achronix CAD Environment (ACE) Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Chapter - 2: General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
PCIe Accelerator-6D Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
User Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Standalone Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
In-system (Plug-in) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
On-Board Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
On-Board Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Board-Specific Design Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Chapter - 3: Development Environment Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Installing Achronix Software (ACE plus Synopsys Synplify Pro) and Licenses . . . . . . . . . . 13
Running ACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Setting up the PCIe Accelerator-6D Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Standalone Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
In-system Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Getting started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Downloading a Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Configuring the Board for the Appropriate Bitstream Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Connecting the Board to the Host PC and Running the Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Chapter - 4: Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Networking and Communications Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
System Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

PCIe Accelerator-6D Card User Guide (UG074)
4www.achronix.com Speedster FPGAs
PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
USB (J7, J8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
JTAG (J6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
SO-DIMM Sockets (J10, J11, J12, J13, J14, J15, J16, J17, J18, J19, J20, J21) . . . . . . . . . . . . . . . . . . . . 25
User Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
FTDI CLI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Bitporter CLI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
ACE GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
SMP Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Miscellaneous Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Chapter - 5: PCIe Accelerator-6D Card Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Chapter - 6: Board Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Chapter - 7: Miscellaneous Diagrams and Figures . . . . . . . . . . . . . . . . . . . . . . . . 36
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

PCIe Accelerator-6D Card User Guide (UG074)
Speedster FPGAs www.achronix.com 5
Chapter - 1: PCIe Accelerator-6D Kit Overview
Figure 1: Achronix PCIe Accelerator-6D Board
PCIe Accelerator-6D Kit Contents
The Achronix PCIe Accelerator-6D kit contents are as follows:
One PCIe Accelerator-6D board
Two micro-USB cable
PCIe Accelerator-6D Quick Start User Guide
Achronix CAD Environment (ACE) license
PCIe Accelerator-6D Kit Uses
This PCIe Accelerator-6D board is designed to achieve a number of functions:
Demonstrate the capabilities of the HD1000 FPGA to potential customers that will ultimately build their
own custom hardware.
Accelerate compute-intensive tasks within a standard PC/server.
Add Gigabit Ethernet capability to a host (a combination of 10G and 40G ports)
Provide a debugging platform for internal Achronix use
PCIe Accelerator-6D Board Features
The PCIe Accelerator-6D board offers the industry’s highest memory bandwidth between the Speedster22i
HD1000 FPGA, which contains 700,000 LUTs, and six independent, dual-slot DDR3 memory interfaces. Each
interface can support single, dual, or quad rank functionality. The DDR3 memory configuration supports up to
192 gigabytes of total memory and can run as fast as 1600 MT/s, which equates to 690 Gbps of total memory
bandwidth.

PCIe Accelerator-6D Card User Guide (UG074)
6www.achronix.com Speedster FPGAs
The PCIe Accelerator-6D's four QSFP+ modules support either four 40 gigabit Ethernet ports or sixteen 10
Gigabit Ethernet ports using breakout cables giving a total bandwidth of 160 Gbps. The card also supports PCI
Express Gen3 by 8, thus providing 64 Gbps bandwidth.
The Accelerator-6D is the perfect platform for building network and compute acceleration applications such as
line-rate deep packet inspection, encryption and decryption algorithms; image processing, machine learning and
database acceleration.
FPGA
Achronix 22-nm, AC22iHD1000F53C2
Functional Blocks
1 million equivalent LUTs (700k programmable LUTs + hard IP)
86 Mb of on-chip memory (82 Mb BRAM, 4 Mb LRAM)
756 28 × 28 multiply/accumulate blocks
960 programmable user I/O
Network and Communications
Hard Ethernet MACs: 100GE, 40GE, 10GE
64 SerDes lanes (1 to 12.75 Gbps)
Hard Interlaken ports, each running up to 11.3 Gbps
System
Hard PCI Express Gen1/2/3 ×1, ×4, ×8
Hard DDR3 controllers: six ×72 at 1600 MT/s
Board
PCI Express pluggable form factor
Three SMP connectors to provide differential and single-ended FPGA external clock
Twelve DDR3 SO-DIMM socket
Four 40 GE QSFP module ports
Power supply modules
Power-on reset circuitry
Oscillators/crystals/clock modules and synthesizers
Power and temperature measurement sensors
SPI header for flash memory access
Flash memory for device configuration
LEDs, switches, headers
JTAG header for bitstream programming via Bitporter pod and/or access to FPGA internal registers

PCIe Accelerator-6D Card User Guide (UG074)
Speedster FPGAs www.achronix.com 7
Two micro-USB connectors for bitstream programing via FTDI and to allow access to FPGA internal
registers via ACE demo command and control (DDC) connection
Note
Component numbers mentioned in this guide refer to PCIe Accelerator-6D Board component or device
markings. Board schematics can be made available upon signing an NDA with Achronix.
Achronix CAD Environment (ACE) Software
Achronix provides ACE software together with an Achronix-optimized version of Synplify-Pro from Synopsys (a
node-locked or floating version of the license is needed to use the ACE software for development). See PCIe
for more details about installation and Accelerator-6D Card Development Environment Setup (see page 13)
use.
Figure 2: ACE Development Environment

PCIe Accelerator-6D Card User Guide (UG074)
8www.achronix.com Speedster FPGAs
Save

PCIe Accelerator-6D Card User Guide (UG074)
Speedster FPGAs www.achronix.com 9
Chapter - 2: General Description
PCIe Accelerator-6D Board
The development board has a PCIe form-factor having a dimension of Length:310 mm × Width:97.5 mm. It also
has dedicated power connectors.The figure below shows the PCIe Accelerator-6D Board Details (see page 9)
PCIe Accelerator-6D board with many of the key components annotated.
Figure 3: PCIe Accelerator-6D Board Details
User Modes
There are two use modes for this development board, standalone and in-system (plug-in). In both modes, the
user must provide power to the board through the dedicated power connectors using an external power supply
as shown in the figure below.
Standalone Mode
In this mode, the development board is placed on a bench, with control and data signals coming from the
surrounding interfaces, which may include the DIP switches, SMP connectors, I C header, Maxim temperature
2
sensor, DCC mcro-USB connector, nicro-USB connector for programming the FPGA over FTDI in JTAG mode,
etc.

PCIe Accelerator-6D Card User Guide (UG074)
10 www.achronix.com Speedster FPGAs
Figure 4: PCIe Accelerator-6D Board Connected in Standalone Mode
In-system (Plug-in) Mode
The PCIe Accelerator-6D board is inserted into a PCIe Gen3 ×8 slot of a PC. In addition to the capabilities
highlighted in the standalone mode, data traffic can be supplied over the PCIe interface in this mode, assuming
the PCIe interface of the FPGA is configured appropriately. This mode is shown in the figure below:

PCIe Accelerator-6D Card User Guide (UG074)
Speedster FPGAs www.achronix.com 11
Figure 5: PCIe Accelerator-6D Board Connected in In-system Mode
Note
Power must still be provide to the board via an external power supply rather than the PCIe connector
and the dedicated power connectors on the board.
On-Board Memory
The development board has the following memories available for system design.
Twelve 204-pin DDR3 SO-DIMM connectors to allow for loading of 12 DDR3 SO-DIMMs each of which
has a performance of 12.8 Gbps or 1600 MT/s. This memory serves as the primary off-chip memory for all
applications, supplementing the on-chip BRAM. This memory also demonstrates the embedded DDR3
controller capability.
An 512 Mb SPI flash device used to store configuration bitstreams on board.

PCIe Accelerator-6D Card User Guide (UG074)
12 www.achronix.com Speedster FPGAs
On-Board Temperature Sensor
The PCIe Accelerator-6D card comes with an on-board Maxim temperature sensor which can be accessed via
the I C interface to measure the temperature captured by the onchip temperature diode of in the HD1000 FPGA.
2
Board-Specific Design Issues
The PCIe Accelerator-6D board is optimized for networking and compute acceleration applications. As such,
Achronix has configured the SerDes and the I/O at specific pins on the HD1000 device. This configuration must
maintain during any changes made to the design hosted in the FGPA. Achronix provides a template for ACE to
avoid inadvertent changes to the configuration. The clocking structure implemented on the board must also be
maintained during any design changes.

PCIe Accelerator-6D Card User Guide (UG074)
Speedster FPGAs www.achronix.com 13
1.
a.
b.
c.
d.
2.
3.
4.
5.
6.
Chapter - 3: Development Environment Setup
Installing Achronix Software (ACE plus Synopsys Synplify Pro)
and Licenses
Achronix provides ACE and Achronix's OEM version of Synopsys Synplify Pro licenses for design. Achronix
(UG002) provides detailed information about acquiring and installing ACE and Software & License User Guide
Synplify Pro licenses and software. A download account is required in order to download the software and
request a license. Below is a quick summary of steps to install the Achronix software and licenses:
From download the following files, depending on the host setup:https://downloads.achronix.com
Windows node locked/Windows client software
Floating (Windows license server)
Linux node locked/Linux client software
Windows node locked/Windows client software
Install licenses e-mailed by Achronix on the license server.
Modify the license servers for floating licenses only (cases b, c, e, and f)
Run the license servers (not needed for case a, Windows node-locked)
Set the client machine environment variables
Run the software
For more details on Steps 1 through 6 refer to the .Achronix Software & License User Guide
Running ACE
After installation and licensing, run the executable file to start using ACE. For more information about getting
started with ACE, refer to (UG001).ACE User Guide
Setting up the PCIe Accelerator-6D Board
Depending on the evaluation requirements, choose either the standalone or the in-system (plug-in) mode of
operation for the board.
Standalone Mode
The board must be connected the host PC and an external power source. The connections are shown in Figure
below.Standalone Board Connections (see page 14)

PCIe Accelerator-6D Card User Guide (UG074)
14 www.achronix.com Speedster FPGAs
1.
2.
3.
Figure 6: Standalone Board Connections
Connecting the Host PC
Based on the system requirements, the following are the connections needed to the host PC:
Connect the supplied micro-USB cable the to the "USB Connector for FTDI" (see figure: PCIe Accelerator-
) for programming the FPGA and/or accessing HD1000's internal 6D Board Details (see page 9)
registers via FTDI over JTAG.
Connect the second supplied micro-USB cable to the "DCC Micro-USB Connector" (see figure: PCIe
) for accessing the HD1000's internal registers via DCC.Accelerator-6D Board Details (see page 9)
Connect the extended Gen3 ×8 PCIe connector to the PCIe edge connector on the board (see figure:
).PCIe Accelerator-6D Board Details (see page 9)
Connecting the Power Supply
Although the individual components on the board use different voltage levels, each of these is generated on the
board using a single 12V power supply input.

PCIe Accelerator-6D Card User Guide (UG074)
Speedster FPGAs www.achronix.com 15
In-system Mode
For in-system mode, plug the Accelerator-6D board into an available PCIe ×8 slot of the host PC. Make sure the
adjacent slot is also vacant to accommodate the clearance requirements for the component side of the board.
Figure shows the connections for this mode.In-System Board Connections (see page 15)
Figure 7: In-System Board Connections
Connecting the Power Supply
Although the individual components on the board use different voltage levels, each of these is generated on the
board using a single 12V power supply input. A spare 12V supply connector from the host PC power supply can
be used.

PCIe Accelerator-6D Card User Guide (UG074)
16 www.achronix.com Speedster FPGAs
1.
2.
Getting started
Power Sequencing
The power sequencing on the board is pre-configured and is controlled by Linear Technology's LTM2987 power
system manager. After connecting the power supply and the POWER GOOD LED (DS3000) is steady green, the
board is fully powered up and has initialized all the components in the right order.
Initialization
As mentioned above, the power to all devices on the board is controlled by the pre-configured LTM2987 power
system manager which acts as the I C master initially during power-up. This device then drives and manages the
2
various other LTM switching regulators which provide power to the various power rails of the HD1000 FPGA.
Once the board is powered-up, a set of LEDs light. Refer to the PCIe Accelerator-6D Card Quick Start User
for details on default power-up behavior.Guide
Following power-up the various clock are then brought up. The clocks on the board come pre-configured and
generated by IDT clock device. The various devices on the board can be controlled via the I C bus by either the
2
on board HD1000 FPGA or through an external device via the DC1613A I C programming connector, either of
2
which can act as the I C bus master. After power-up and initialization, the HD1000 becomes the default I C bus
2 2
master.
Downloading a Design
Typically, the following steps are needed to download a design to the board and start debugging an application.
Configuring the Board for the Appropriate Bitstream Source (see page 16)
Connecting the Host PC (see page 14) and Running the application
The following sources are currently supported for the FPGA bitstream on this board:
Bitstream download via JTAG using the on-board FTDI device its corresponding micro-USB port using the
provided micro-USB cable which connect to the host PC.
Bitstream download via JTAG using a Bitporter pod which connects to the host PC.
Bitstream programming using the on-board flash SPI (×1, ×4) memory and CPU programming mode (may
be made available in future release).
Configuring the Board for the Appropriate Bitstream Source
The board is pre-configured with switch SW3000 set to "Disable SPI" to accept bitstreams from the JTAG
interface. The following is SW3000 switch configuration for the various programming interface modes:

PCIe Accelerator-6D Card User Guide (UG074)
Speedster FPGAs www.achronix.com 17
1.
2.
3.
Table 1: SW3000 Programming Interface Switch Connections
P1 P2 Function
Off On SPI ×1
On Off SPI ×4
Others Disable SPI
Connecting the Board to the Host PC and Running the Application
When programming via the JTAG interface:
Via FTDI – connect the micro-USB cable to the "USB Connector for FTDI" (see figure: PCIe Accelerator-
) port on the board and the other end to the USB port of the host PC.6D Board Details (see page 9)
– connect the Bitporter pod using the ribbon cable to the "JTAG Header" (see figure:Via Bitporter PCIe
). Connect the USB end of Bitporter pod to USB port of the Accelerator-6D Board Details (see page 9)
host PC.
Power up the board.
Run ACE and switch to "Programming and Debug Perspective" or "HW Demo Perspective" to program the
bitstream.
Once the FPGA is programmed and the CONFIG_DONE LED light is green, the configuration has successfully
completed, and the FPGA has transitioned to user mode. At this point, run any application as desired.
For more details refer to the board and PCIe Accelerator-6D Card Quick Start User Guide Bitstream
.Programming and Debug Interface User Guide

PCIe Accelerator-6D Card User Guide (UG074)
18 www.achronix.com Speedster FPGAs
Chapter - 4: Interfaces
There are various interfaces available on the HD1000 FPGA and the Accelerator-6D board. These interfaces are
discussed in more detail in the following sections:
Networking and Communications Interface (see page 19)
System Interfaces (see page 22)
Memory Interface (see page 25)
User Interfaces (see page 26)
Miscellaneous Interfaces (see page 31)
Figure 8: PCIe Accelerator-6D Card Interfaces

PCIe Accelerator-6D Card User Guide (UG074)
Speedster FPGAs www.achronix.com 19
1.
2.
3.
Networking and Communications Interface
The four QSFP ports provide a primary high-speed networking data interface for the board, enabling the 10G
/40G capabilities of HD1000. For the data path, the four 40G QSFP ports together provide a total duplex
bandwidth of 320 Gb/s bandwidth (160 Gb/s transmit and 160 Gb/s receive). These ports can used to support
any of of the following Ethernet data rates:
1 × 100G (10 × 10G with split-out cables )
4 × 40G (4 QSFP transceiver modules)
16 × 10G (with split-out cables)
The four-port QSFP cage is directly connected to 16 bidirectional 12.5 G SerDes lanes. These are designated in
quads as SerDes CH0 [8:11], CH1 [16:19], CH2 [24:27], CH3 [28:31] as shown in the figure above. Table below
shows the pin assignment for the QSFP interface to the HD1000 SerDes pin.
Table 2: Accelerator-6D Rev C QSFP Interface Pins
QSFP Module Pin Name QSFP CH No./HD1000 SerDes No. Pin on HD1000 (U1)
RIGHT_TX1_N
CH 0
8 - 11
B19
RIGHT_TX1_P C19
RIGHT_TX2_N A20
RIGHT_TX2_P B20
RIGHT_TX3_N C21
RIGHT_TX3_P B21
RIGHT_TX4_N B22
RIGHT_TX4_P A22
RIGHT_RX1_N E19
RIGHT_RX1_P F19
RIGHT_RX2_N F20
RIGHT_RX2_P G20
RIGHT_RX3_N E21
RIGHT_RX3_P F21
RIGHT_RX4_N F22
RIGHT_RX4_P G22

PCIe Accelerator-6D Card User Guide (UG074)
20 www.achronix.com Speedster FPGAs
QSFP Module Pin Name QSFP CH No./HD1000 SerDes No. Pin on HD1000 (U1)
R_MID_TX1_N
CH 1
16 - 19
C27
R_MID_TX1_P B27
R_MID_TX2_N B28
R_MID_TX2_P A28
R_MID_TX3_N C29
R_MID_TX3_P B29
R_MID_TX4_N B30
R_MID_TX4_P A30
R_MID_RX1_N E27
R_MID_RX1_P F27
R_MID_RX2_N F28
R_MID_RX2_P G28
R_MID_RX3_N E29
R_MID_RX3_P F29
R_MID_RX4_N F30
R_MID_RX4_P G30
L_MID_TX1_N
CH 2
24 - 27
C35
L_MID_TX1_P B35
L_MID_TX2_N B36
L_MID_TX2_P A36
L_MID_TX3_N C37
L_MID_TX3_P B37
L_MID_TX4_N B38
L_MID_TX4_P A38