AcSiP EK-AI7933CLD User manual

Version
A
Doc No
912-13903
Date
2022/04/29
EK-AI7933CLD
User Guide
AcSiP Technology Corp
www.acsip.com.tw
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Document History
Date
Revised Contents
Revised By
Version
2022/04/29
Initial Version
Ivan
A
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INDEX
1. Introduction ......................................................................................4
1.1 General Description .......................................................................................................... 4
2. Get started with the HDK...................................................................5
2.1 Configuring the EK-AI7933CLD ........................................................................................ 5
2.2 Installing the FTDI drivers on Microsoft Windows .......................................................... 6
3. Hardware Features ............................................................................8
3.1 Features Description ........................................................................................................ 8
4. Hardware Feature Configuration......................................................10
4.1 Microcontroller ............................................................................................................... 10
4.2 Power supply .................................................................................................................. 10
4.3 Audio ............................................................................................................................... 13
4.4 Buttons ............................................................................................................................ 14
4.5 RGB LED........................................................................................................................... 14
4.6 SD card ............................................................................................................................ 15
4.7 Extension connectors ...................................................................................................... 16
4.8 RTC................................................................................................................................... 26
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Lists of Tables and Figures
Table 1 Jumper settings for system power input through USB connection............................. 11
Table 2 Audio related function .................................................................................................. 13
Table 3 Buttons ........................................................................................................................... 14
Table 4 GPIO pin-out extension connectors .............................................................................. 17
Table 5 GPIO pin multi-function definition................................................................................ 18
Figure 1. Front view of EK-AI7933CLD ......................................................................................... 4
Figure 2. Jumpers and connectors on the EK-AI7933CLD ........................................................... 5
Figure 3. COM port associated with the EK-AI7933CLD ............................................................. 7
Figure 4. Default power jumper plot ......................................................................................... 10
Figure 5. Power up the HDK using an AA or AAA Battery (J25)............................................... 12
Figure 6 . Audio Jumper and connector Locations .................................................................... 13
Figure 7. RGB LED ....................................................................................................................... 14
Figure 8. SD card slot rework ..................................................................................................... 15
Figure 9. GPIO pin-out extension connectors .............................................................................. 16
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1. Introduction
1.1 General Description
AI7933CLD is a highly integrated IoT module that features an ARM® Cortex-M33 application processor,
a low power 1x1 802.11a/b/g/n/ac/ax dual-band Wi-Fi subsystem, a Bluetooth v5.0 subsystem, an
Audio subsystem with Cadence Tensilica HiFi4 processor and a Power Management Unit (PMU). The
Wi-Fi subsystem and a Bluetooth v5.0 subsystem offer feature-rich wireless connectivity at high
standards, and deliver reliable, cost-effective throughput from an extended distance. The AI7933CLD
is designed to support standard based features in the areas of security, quality of service and
international regulations, giving end users the greatest performance any time and in any
circumstance.
The AI7933CLD is based on ARM® Cortex-M33 with floating point microcontroller (MCU) including
SRAM/ROM memory. The module also supports rich peripheral interfaces, including USB2.0, SDIO, SPI
master, I2C, I2S, IR input, UART, AUXADC, PWM, and GPIOs.
These features are used to download and debug a project on EK-AI7933CLD.
The front view of the EK-AI7933CLD including AI7933CLD module in Figure 1.
Figure 1. Front view of EK-AI7933CLD
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2. Get started with the HDK
Before commencing the application development, you need to configure the development platform.
2.1 Configuring the EK-AI7933CLD
The top view of the EK-AI7933CLD is shown in Figure 2.
Figure 2. Jumpers and connectors on the EK-AI7933CLD
The description of pins (Figure 2) and their functionality is provided below.
1) CON8 transfer USB interface to UART interface, can debug through UART, transmit, and receive a signal
form PC.
2) CON8 is a USB 5V power for EK-AI7933CLD, or you can use external 5V power at J1.
3) CON6 is a USB OTG function com port.
4) Press SW1 to reset the system. For SW2~SW5 more detail, please see “section 4.4”.
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5) For Wi-Fi and BT function AI7933CLD module reserve a Wi-Fi + BT IPEX connector. Please connect external
antenna to transmit and receive RF signals.
6) U8 and U9 are on-board AMICs which can catch voice command.
7) U54/U56 are RGB LEDs and these RGB LED will be controlled by SPIM interface.
8) J28 and J87 support multifunction GPIO interface, for more detail please refer to “section 4.7”.
9) J10 and J11 is audio speaker pin header which can connect 8ohm/2W speaker to achieve voice assistant
function.
2.2 Installing the FTDI drivers on Microsoft Windows
To configure the EK-AI7933CLD:
1) Connect the EK-AI7933CLD CON8 to the computer using a micro-USB cable.
2) Check your PC is x86 or x64 system. And download and install FTDI Windows serial port driver from Here.
(The red block showed the download file at below figure)
3) If your OS is Windows7 or 10, please open Windows Control Panel then click System and enter Device
Manager.
4) In Device Manager, navigate to Ports (COM & LPT) (see Figure 3).
5) A new COM device should appear under Ports (COM & LPT) in Device Manager, as shown in Figure 3. Note
the COMx port number of the serial communication port, this information is needed to send command
and receive logs from the COM port.
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Due to the com port numbers (COMx) are different at different PC. As red block in Figure 3. showed,
means “CM33 UART”.
Figure 3. COM port associated with the EK-AI7933CLD
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3. Hardware Features
This section provides the main supported features of the EK-AI7933CLD. The detailed description of
the features isprovided in the upcoming sections.
3.1 Features Description
3.1.1 Technology and Package
• AI7933CLD LGA-104 module, 32mm X 32mm X 2.7mm (Typ.)
3.1.2 Power Management and Clock Source
• Integrates high efficiency power management unit with single 3.3V power supply input
• Integrates 26MHz crystal clock with low power operation in idle mode
• Integrates 32KHz crystal oscillator or low power sleep mode
3.1.3 Platform
• ARM® Cortex-M33 MCU with FPU with up to 300MHz clock speed
• Embedded 1MB SRAM and 8MB PSRAM
• Embedded 16MB serial flash with eXecute In Place (XIP) and on-the-fly AES
• Supports Hardware crypto engines including AES, DES/3DES, SHA, ECC, TRNG for network security
• Supports up to 46 General Purpose IOs, which are multiplexed with SDIO, SPI, UART, I2C, I2S,
AUXADC, PWM and GPIO interfaces
• Supports 12 DMA channels
• Support USB2.0 OTG
• Support RTC Mode
3.1.4 Audio
• Cadence® Tensilica® HiFi4 processor with 600MHzclock speed
• Audio Codec with 2 ADC and 1 DAC channels
• Embedded 256KB SRAM memory
• Supports Voice Activity Detection (VAD) and Keyword detection
• On-board headphone jack for external active speaker
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3.1.5 Wi-Fi
• IEEE 802.11 1T1R a/b/g/n/ax 5GHz and 2.4GHz
• Supports 1x1 20MHz bandwidth, MCS0~8(256-QAM) in 2.4G/5GHz band
• Support uplink MU-OFDMA TX and downlink MU-OFDMA RX
• Support Tx LDPC (Low-density parity check)
• Support Rx STBC
• Wi-Fi security WFA WPA/WPA2/WPA3 personal, WPS2.0
• QOS supports of WFA WMM, WMM PS
• Support 11ax TWT low power
• Support CSI (Channel Signal Information)
• Support antenna diversity
3.1.6 Bluetooth
• BT5.0 2M_PHY / Long Range / Advertising Extension / SAM / CS#2 / High Duty Cycle
Non-Connectable ADV
• BT4.2 Link Layer Privacy / LE Secure Connection / LE Data Packet Length Extension / Link Layer
Extended Scanner Filter Policies
• BT4.1 Link Layer Topology / Secure Connection
• BT4.0 and below BR/EDR
• BR/EDR and BLE dual mode concurrent
• Scatternet support: Up to 7 piconets simultaneously with background inquiry/page scan
• Up to 4 BT link + 8 BLE link
• Support SCO and eSCO link with re-transmission
• Packet loss concealment
• Channel quality driven data rate adaptation
• Channel assessment and WB RSSI for AFH
• Supports BT/Wi-Fi coexistence
3.1.7 Miscellaneous
• Embedded eFuse to store specific device information and RF calibration data
• Advanced TDD mode Wi-Fi/Bluetooth coexistence scheme
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4. Hardware Feature Configuration
4.1 Microcontroller
The AI7933CLD features an ARM® Cortex-M33 processor, which is the most energy efficient ARM®
processor currently available. It supports the clock rates up to 200MHz when core power is 0.7V and
300MHz when core power is 0.8V. The MCU executes the Thump-2 instruction set for optimal
performance and code size, including hardware division, single cycle multiplication and bit-field
manipulation. The AI7933CLD includes a Memory Protection Unit (MPU) in Cortex-M33 MCU to detect
unexpected memory access and provides other memory protection features. The AI7933CLD also
includes FPU in Cortex-M33 MCU.
4.2 Power supply
EK-AI7933CLD supports two types of power supply.
1) Power up with a micro-USB connector.
An on-board switching regulator provides voltage of 3.3V for the EK-AI7933CLD, if the power is
supplied from an on-board micro-USB connector CON8 (Figure 2). This supply can be isolated from the
switching regulator using the jumpers.
Note: that the jumpers J2, J3, J4, J5, J27 pin1 and pin2. JP1, JP2, JP5 pin1 and pin2 are required to be
set on. More details on the jumpers can be found in Table 1.
Figure 4. Default power jumper plot
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Table 1 Jumper settings for system power input through USB connection
Jumper
Usage
Comments
J1
External 5V power supply
Use external power source to supply 5V voltage toEK-AI7933CLD
PCB. Pin 1 is 5V source. Pin2 is GND.
J2
DC-5V transfer to DC-3V3 current
source
J3
Current measurement (3V3)
Measures the current flow in AI7933CLD module.
J4
3V3 for EEPROM power
EEPROM has no parts.
J5
3V3 for external components
J25
AVDD33_VRTC battery power supply
Use AA or AAA battery for RTC 3V3 power. Pin1 is positive
endpoint, Pin2 is GND.
J26
Current measurement in RTC mode
Measures the current flow in RTC mode for EK-AI7933CLD.
J27
3V3 for SD_CARD power
JP1
Switch VCCIO_L to 3V3 power domain
or 1V8 power domain
Select pin 1 & 2, means VCCIO_L use 3V3 power domain
Select pin 2 & 3, means VCCIO_L use 1V8 power domain
JP2
Switch VCCIO to 3V3 power domain or
1V8 power domain
Select pin 1 & 2, means VCCIO use 3V3 power domain
Select pin 2 & 3, means VCCIO use 1V8 power domain
Caution: The flash of AI7933CLD default using3V3 power domain,
if you want to change VCCIO to 1V8 power domain please rework
flash to 1V8 power domain flash (eq. W25Q128JWPIQ)
JP3
Switch 1V8 VCCIO from internal
PHYLDOor external LDO
Select pin 2 & 3, means 1V8 VCCIO from internal PHYLDO
Select pin 1 & 2, means 1V8 VCCIO from external Buck
component
JP5
Switch RTC 3V3 from DC-3V3 or
AVDD33_VRTC
Select pin 1 & 2, means RTC_3V3 use DC-3V3
Select pin 2 & 3, means RTC_3V3 use AVDD33_VRTC
JP7
Switch SD Card to 3V3 power domain
or 1V8 power domain
Select pin 1 & 2, means SD_CARD power use 1V8 power domain
Select pin 2 & 3, means SD_CARD power use 3V3 power domain
JP9
Switch EEPROM(NC) to 3V3 power
domain or 1V8 power domain
Select pin 1 & 2, means EEPROM power use 3V3 power domain
Select pin 2 & 3, means EEPROM power use 1V8 power domain
J88
5V for (U10) Audio AMP power
Pin 1 is EXUSB_5V
J89
5V for (U10) Audio AMP using
Pin 1 is EXUSB_5V
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2) Power up using an AA or AAA battery.
Connect an external AA or AAA battery to battery pin header (J25) to supply power to the system, as
shown in Figure 5. When using RTC mode, please note that remove jumper J2 and plug in jumper J26.
Jumper JP5 should be switched to pin2 and pin3.
Figure 5. Power up the HDK using an AA or AAA Battery (J25)
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4.3 Audio
The EK-AI7933CLD has onboard audio connector associated with different functionalities of the
board. The detail of audio related function can refer to Table 2.
Table 2 Audio related function
item
Detail
J8
3.5mm audio jack for external active speaker.
J6
Audio-Left_P switch , Pin(3,2,1) Pin define (Amp_L_in_P , Module_audio_out_L, Audio jack_L_in)
Select pin 2 & 1, The audio is output by audio jack. Select pin 3 & 2, The audio is output by speaker (J10)
J24
Audio-Right_P switch, Pin(3,2,1) Pin define (Audio jack_R_in , Module_audio_out_R ,Amp_R_in_P)
Select pin 3 & 2, The audio is output by audio jack. Select pin 2 & 1, The audio is output by speaker (J11)
J85
Audio-Left_N , Pin(1,2) Pin define (Audio_L_N,GND)
J86
Audio-Right_N, Pin(1,2) Pin define (GND, Audio_R_N)
J10
Audio header for left speaker
J11
Audio header for right speaker
U8
AMIC for left channel (the microphone hole is set at back side of EK-AI7933CLD )
U9
AMIC for right channel (the microphone hole is set at back side of EK-AI7933CLD )
SW2
Audio volume up button
SW3
Audio volume down button
Figure 6 . Audio Jumper and connector Locations
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4.4 Buttons
The EK-AI7933CLD is equipped with buttons with the following functionality.
The push buttons are shown in Figure 2. The detail of buttons can refer to Table 3.
Table 3 Buttons
Button
Name
Detail
SW1
SYSRST
Press SW1 to restart the EK-AI7933CLD
SW2
Vol+
Audio volume up button
SW3
Vol-
Audio volume down button
SW4
RTC_EINT
Press SW4 to enable RTC mode
SW5
Force DL mode
Press SW5 to trigger strapping mode (download mode…)
4.5 RGB LED
As Figure7 showed, the EK-AI7933CLD has on-board RGB LEDs (U54/U56) which be controlled by SPIM
interface. Please note that ensure jumper J79 and J80 are connected before using RGB LED function If
you want to cascade more RGB LED, you can connect to J78
Figure 7. RGB LED
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4.6 SD Card
The EK-AI7933CLD reserve a SD card slot to provide user to save data into a SD card. And note that there
are some registers which placed need to be reworked before using SD card. Please refer to figure.6 and
switch R756 to R757; switch R745 to R751; switch R744 to R750; switch R746 to R747; switch R748 to
R749; switch R754 to R755; switch R752 to R753.
Figure 8. SD card slot rework
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4.7 Extension connectors
The EK-AI7933CLD provides similar pin-out extension connectors for various sensor and device
connectivity, as shown in Figure.7 and described in Table 4.
The board has 46 GPIOs multiplexed with other interfaces. Depending on the use case, user can
configure each I/O functionality.
Note: GPIO-12 & GPIO-C_12 is the same circuit
GPIO-39 Default to NC
Figure 9. GPIO pin-out extension connectors
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Table 4 GPIO pin-out extension connectors
Signal Name
Connector Pin Number
Signal Name
Connector Pin Number
GPIO_0
Reserve for flash
GPIO_27
J87 - 18
GPIO_1
Reserve for flash
GPIO_28
J87 - 20
GPIO_2
Reserve for flash
GPIO_29
J28 - 15
GPIO_3
Reserve for flash
GPIO_30
J28 - 17
GPIO_4
Reserve for flash
GPIO_31
J28 - 19 Reserve for USB OTG
GPIO_5
Reserve for flash
GPIO_32
J28 - 21 Reserve for USB OTG
GPIO_6
J28 - 2 Reserve for Arduino: SPI0_SCK
GPIO_33
J28 - 23 Reserve for USB OTG
GPIO_7
J28 - 4 Reserve for Arduino: SPI0_CSN
GPIO_34
J28 - 25 Reserve for USB OTG
GPIO_8
J28 - 6 Reserve for Arduino: SPI0_MISO
GPIO_35
J28 - 18
GPIO_9
J28 - 8 Reserve for Arduino: SPI0_MOSI
GPIO_36
J28 - 20
GPIO_10
J28 - 10
GPIO_37
J28 - 22
GPIO_11
J28 - 12
GPIO_38
J28 - 24
GPIO_12
J87 - 5
GPIO_39
J28 - 29 Default for AU_AMP_MUTE
GPIO_13
J87 - 7
GPIO_40
J28 - 27
GPIO_14
J87 - 9
GPIO_41
J28 - 1
GPIO_15
J87 - 11
GPIO_42
J28 - 30 Reserve for Arduino: UART1_RX
GPIO_17
J87 - 13
GPIO_43
J28 - 3
GPIO_18
J87 - 15
GPIO_44
J28 - 28 Reserve for Arduino: UART1_TX
GPIO_19
J87 - 17 Reserve for Arduino: I2C1_SDA
GPIO_45
J28 - 5
GPIO_20
J87 - 19 Reserve for Arduino: I2C1_SCL
GPIO_46
J28 - 7
GPIO_21
J87 - 21
GPIO_47
J87 - 2
GPIO_22
J87 - 23
GPIO_48
J87 - 6 Reserve for CM33 UART
GPIO_23
J87 - 25
GPIO_49
J87 - 4
GPIO_24
J87 - 12
GPIO_50
J87 - 8 Reserve for CM33 UART
GPIO_25
J87 - 14
GPIO_51
J28 - 9
GPIO_26
J87 - 16
GPIO_52
J28 - 11
Note: GPIO_39 is AU_AMP_MUTE by default. When using pin headers J28-29pin, resistor R161 needs to be switched to Location of
R160.
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Table 5 GPIO pin multi-function definition
IO Name
CR Value Default*
Name
Dir
Default
Description
Dir
PU/PD
PAD_SYSRST_B
NA
PAD_SYSRST_B
PU
Chip hardware
fundamental reset pin
SDIO_CLK
0000
GPIO[6]
I/O
I
PD
GPIO 6
0001 *
SDIO_CLK
I
SDIO Clock
0010
MSDC0_CLK
O
MSDC Clock
0011
SPIM0_SCK
O
SPI0 (Master) Clock
0100
CM33_GPIO_EINT0
I
CA33 EINT0
0101
DEBUG_0
O
Debug signal
0110
ANT_SEL0
O
Antenna Select 0
0111
BGF_EINT_10_B
I
SDIO_CMD
0000
GPIO[7]
I/O
I
PU
GPIO 7
0001 *
SDIO_CMD
I/O
SDIO Command
0010
MSDC0_CMD
I/O
0011
SPIM0_CS_N
O
SPI0 (Master) Chip Select
0100
CM33_GPIO_EINT1
I
CA33 EINT1
0101
DEBUG_1
O
Debug signal
0110
ANT_SEL1
O
Antenna Select 1
0111
PINMUX_EXT_INT_N_IN
I
SDIO_DAT0
0000
GPIO[8]
I/O
I
PU
GPIO 8
0001 *
SDIO_DAT0
O
SDIO Data[0]
0010
MSDC0_DAT0
I/O
MSDC0 data0
0011
SPIM0_MISO
I
SPI0 (Master) Input
0100
UART0_RTS
O
0101
DEBUG_2
O
Debug signal
0110
ANT_SEL2
O
Antenna Select 2
0111
CM33_GPIO_EINT0
I
CA33 EINT0
SDIO_DAT1
0000
GPIO[9]
I/O
I
PU
GPIO 9
0001 *
SDIO_DAT1
I/O
SDIO Data[1]
0010
MSDC0_DAT1
I/O
MSDC0 data1
0011
SPIM0_MOSI
O
SPI0 (Master) Output
0100
UART0_CTS
I
UART0 Control
0101
DEBUG_3
O
Debug signal
0110
ANT_SEL3
O
Antenna Select 3
0111
CM33_GPIO_EINT1
I
CA33 EINT1
SDIO_DAT2
0000
GPIO[10]
I/O
I
PU
GPIO 10
0001 *
SDIO_DAT2
I/O
SDIO Data[2]
0010
MSDC0_DAT2
I/O
MSDC0 data2
0011
I2SIN_DAT0
I
0100
UART0_RX
I
UART0 RX
0101
DEBUG_4
O
Debug signal
0110
I2C0_SCL
I/O
0111
CM33_GPIO_EINT2
I
CA33 EINT2
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IO Name
CR Value Default*
Name
Dir
Default
Description
Dir
PU/PD
SDIO_DAT3
0000
GPIO[11]
I/O
I
PU
GPIO 11
0001 *
SDIO_DAT3
I/O
SDIO Data[3]
0010
MSDC0_DAT3
I/O
0011
I2SO_DAT0
O
I2SO Data
0100
UART0_TX
O
UART0 TX
0101
DEBUG_5
O
Debug signal
0110
I2C0_SDA
I
I2C0 Data
0111
CM33_GPIO_EINT3
I
CA33 EINT3
GPIO_B_0
0000
GPIO[12]
I/O
O
PU
GPIO 12
0001 *
CONN_BGF_UART0_TXD
O
0010
MSDC0_RST
O
MSDC0 reset
0011
CONN_BT_TXD
O
0100
WIFI_TXD
O
0101
DEBUG_6
O
Debug signal
0110
ANT_SEL3
O
Antenna Select 3
0111
CM33_GPIO_EINT4
I
CA33 EINT4
GPIO_B_1
0000
GPIO[13]
I/O
I
PU
GPIO 13
0001 *
USB_IDDIG
I
USB OTG ID pin
0010
SPIM1_SCK
O
SPIM1 (Master) Clock
0011
I2SO_BCK
O
I2SO BCK
0100
UART1_RX
I
UART1 RX
0101
DEBUG_7
O
0110
ANT_SEL4
O
Antenna Select 4
0111
CM33_GPIO_EINT5
I
CA33 EINT5
GPIO_B_2
0000
GPIO[14]
I/O
O
PD
GPIO 14
0001 *
USB_DRV_VBUS
O
USB OTG host mode
driving enable output
0010
SPIM1_MOSI
O
SPI1 (Master) Output
0011
I2SO_LRCK
O
I2SO LRCK
0100
0101
DEBUG_8
O
Debug signal
0110
ANT_SEL5
O
Antenna Select 5
0111
CM33_GPIO_EINT6
I
CA33 EINT6
GPIO_B_3
0000
GPIO[15]
I/O
I
PD
GPIO 15
0001 *
USB_OC
I
USB Host mode over-
current input notify
0010
SPIM1_MISO
I
SPI1 (Master) Input
0011
I2SO_MCK
O
I2STX MCLK
0100
I2SIN_MCK
O
I2SRX MCK
0101
DEBUG_9
O
Debug signal
0110
ANT_SEL6
O
Antenna Select 6
0111
CM33_GPIO_EINT7
I
CA33 EINT7
GPIO_B_5
0000
GPIO[17]
I/O
I
PU
GPIO 17
0001 *
CONN_BGF_UART0_RXD
I
0010
UART0_RX
I
UART0 RX
0011
TDMIN_MCLK
I
0100
DMIC_CLK0
O
DMIC CLK0
0101
DEBUG_11
O
Debug signal
0110
ANT_SEL8
O
Antenna Select 8
0111
CM33_GPIO_EINT9
I
CA33 EINT9
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