Actions ATJ2135 Operating instructions

Actions ATJ2135 Product
Programming Guide
Latest Version: 1.1
Jan 2007

ATJ2135 PROGRAMMING GUIDE
Copyright ©Actions Semiconductor Co., Ltd. 2006. All rights reserved.
Ver 1.1 Page 1 2007-1-29
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ATJ2135 PROGRAMMING GUIDE
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Contents
Declaration......................................................................................................................1
Contents ..........................................................................................................................3
List of Figures .............................................................................................................. 11
List of Tables ................................................................................................................ 12
Revision History ........................................................................................................... 18
1Introduction........................................................................................................... 19
2Pin Description ..................................................................................................... 20
2.1 Pin Assignment ..............................................................................................................20
2.2 Pin Definition..................................................................................................................21
3Functional Block and Memory Map ................................................................... 28
3.1 Functional Block Diagram ............................................................................................ 28
3.2 Memory Map ..................................................................................................................29
4Clock Management Unit (CMU) ...........................................................................31
4.1 CMU/HOSC Description ................................................................................................31
4.2 CMU/HOSC Register List ..............................................................................................35
4.2.1 CMU_COREPLL...........................................................................................................35
4.2.2 CMU_DSPPLL .............................................................................................................36
4.2.3 CMU_AUDIOPLL .........................................................................................................36
4.2.4 CMU_BUSCLK .............................................................................................................38
4.2.5 CMU_SDRCLK.............................................................................................................39
4.2.6 CMU_NANDCLK..........................................................................................................39
4.2.7 CMU_SDCLK ...............................................................................................................40
4.2.8 CMU_UARTxCLK .........................................................................................................40
4.2.9 CMU_MHACLK ............................................................................................................41
4.2.10 CMU_DMACLK ............................................................................................................ 41
4.2.11 CMU_FMCLK ...............................................................................................................42
4.2.12 CMU_MCACLK ............................................................................................................43

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4.2.13 CMU_DEVCLKEN ........................................................................................................43
4.2.14 CMU_DEVRST .............................................................................................................45
4.3 RTC/LOSC/Watch Dog/timers Block Description ....................................................46
4.4 RTC/LOSC/Watch Dog Register List........................................................................... 47
4.4.1 RTC_CTL ......................................................................................................................48
4.4.2 RTC_DHMS..................................................................................................................49
4.4.3 RTC_YMD ....................................................................................................................50
4.4.4 RTC_DHMSALM..........................................................................................................50
4.4.5 RTC_YMDALM.............................................................................................................51
4.4.6 RTC_WDCTL................................................................................................................51
4.4.7 RTC_T0CTL..................................................................................................................52
4.4.8 RTC_T0 ........................................................................................................................53
4.4.9 RTC_T1CTL..................................................................................................................53
4.4.10 RTC_T1 ........................................................................................................................53
5Interrupt Controller............................................................................................... 55
5.1 Interrupt Controller Description...................................................................................55
5.2 Interrupt Controller Register List.................................................................................56
5.2.1 INTC_PD ......................................................................................................................56
5.2.2 INTC_MSK ...................................................................................................................57
5.2.3 INTC_CFGx ..................................................................................................................58
5.2.4 INTC_EXTCTL ..............................................................................................................59
6PMU/DC-DC Converter..........................................................................................61
6.1 Description...................................................................................................................... 61
6.2 Register List....................................................................................................................62
6.3 Register Description......................................................................................................62
6.3.1 PMU_CTL.....................................................................................................................62
6.3.2 PMU_LRADC...............................................................................................................64
6.3.3 PMU_CHG....................................................................................................................65
732-BIT RISC Core.................................................................................................. 68
7.1 Coprocessor 0 Description ...........................................................................................68
7.2 Coprocessor 0 Register List .........................................................................................68
7.2.1 IntCtl Register (CP0 Register 12, Select1) ............................................................69
7.2.2 SRSCtl Register (CP0 Register 12, Select 2).........................................................70
7.2.3 SRSMap Register (CP0 Register 12, Select 3)...................................................... 71
7.2.4 Processor Identification (CP0 Register 15, Select 0)........................................... 71

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7.2.5 EBase Register (CP0 Register 15, Select 1)..........................................................72
7.2.6 Config Register (CP0 Register 16, Select 0)..........................................................72
7.2.7 Config1 Register (CP0 Register 16, Select1) ........................................................73
7.2.8 Config2 Register (CP0 Register 16, select2)......................................................... 74
7.2.9 Config3 Register (CP0 Register 16, select3)......................................................... 74
7.3 Performance Counters Description.............................................................................75
7.4 Performance Counters Register List...........................................................................75
7.4.1 PCNT_CTL.................................................................................................................... 76
7.4.2 PCNT_PCx ...................................................................................................................77
7.5 Other Reference.............................................................................................................78
8SDRAM Interface.................................................................................................. 79
8.1 SDRAM Interface Description ......................................................................................79
8.2 SDRAM Interface Register List ....................................................................................79
8.2.1 SDR_CTL .....................................................................................................................80
8.2.2 SDR_EN.......................................................................................................................81
8.2.3 SDR_CMD ...................................................................................................................81
8.2.4 SDR_STAT ...................................................................................................................82
8.2.5 SDR_AUTORFC ...........................................................................................................83
8.2.6 SDR_MODE.................................................................................................................83
8.2.7 SDR_MOBILE..............................................................................................................84
9SRAM on Chip....................................................................................................... 85
9.1 Description......................................................................................................................85
9.2 Register List....................................................................................................................85
9.2.1 SRAMOC_CTL .............................................................................................................85
9.2.2 SRAMOC_STAT ...........................................................................................................86
10 DMA/Bus Arbiter ...............................................................................................87
10.1 Description...................................................................................................................... 87
10.2 Register List.................................................................................................................... 87
10.2.1 DMA_CTL.....................................................................................................................88
10.2.2 DMA_IRQEN................................................................................................................88
10.2.3 DMA_IRQPD ...............................................................................................................90
10.2.4 DMA_MODEx ..............................................................................................................91
10.2.5 DMA_SRCx..................................................................................................................93
10.2.6 DMA_DSTx ..................................................................................................................93
10.2.7 DMA_CNTx ..................................................................................................................94

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10.2.8 DMA_REMx .................................................................................................................94
10.2.9 DMA_CMDx.................................................................................................................94
11 24-BIT DSP Core ............................................................................................... 96
11.1 Description...................................................................................................................... 96
11.2 Register List....................................................................................................................96
11.2.1 DSP_HDR0..................................................................................................................97
11.2.2 DSP_HDR1.................................................................................................................. 97
11.2.3 DSP_HDR2.................................................................................................................. 97
11.2.4 DSP_HDR3..................................................................................................................98
11.2.5 DSP_HDR4..................................................................................................................98
11.2.6 DSP_HDR5..................................................................................................................98
11.2.7 DSP_HSR6..................................................................................................................99
11.2.8 DSP_HSR7..................................................................................................................99
11.2.9 DSP_CTL......................................................................................................................99
12 Media Hardware Accelerator (MHA)............................................................. 101
12.1 Description....................................................................................................................101
12.2 Register List and Memory Map .................................................................................102
12.2.1 MHA_CTL...................................................................................................................102
12.2.2 MHA_CFG ..................................................................................................................104
12.2.3 MHA_DCSCL01 ........................................................................................................106
12.2.4 MHA_DCSCL23 ........................................................................................................106
12.2.5 MHA_DCSCL45 ........................................................................................................106
12.2.6 MHA_DCSCL67 ........................................................................................................107
12.2.7 MHA_QSCL................................................................................................................107
13 Motion Compensation Accelerator (MCA) ................................................... 108
13.1 Description....................................................................................................................108
13.2 Register List and Memory Map .................................................................................108
13.2.1 MCA_CTL ...................................................................................................................109
14 NAND FLASH Interface ..................................................................................111
14.1 Description....................................................................................................................111
14.2 Register List..................................................................................................................111
14.2.1 NAND_CTL................................................................................................................ 112
14.2.2 NAND_STATUS..........................................................................................................114
14.2.3 NAND_FIFOTIM.........................................................................................................115
14.2.4 NAND_CLKCTL..........................................................................................................116

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14.2.5 NAND_BYTECNT.......................................................................................................116
14.2.6 NAND_ADDRLO1234..............................................................................................117
14.2.7 NAND_ADDRLO56...................................................................................................117
14.2.8 NAND_ ADDRHI1234..............................................................................................117
14.2.9 NAND_ ADDRHI56.................................................................................................. 118
14.2.10 NAND_BUF0 ........................................................................................................ 118
14.2.11 NAND_BUF1 ........................................................................................................ 118
14.2.12 NAND_CMD ..........................................................................................................119
14.2.13 NAND_ECCCTL .................................................................................................... 122
14.2.14 NAND_HAMECC0................................................................................................ 123
14.2.15 NAND_HAMECC1................................................................................................ 125
14.2.16 NAND_HAMECC2................................................................................................ 126
14.2.17 NAND_HAMCEC ...................................................................................................127
14.2.18 NAND_RSE0 .........................................................................................................127
14.2.19 NAND_RSE1 ........................................................................................................ 128
14.2.20 NAND_RSE2 ........................................................................................................ 128
14.2.21 NAND_RSE3 ........................................................................................................ 129
14.2.22 NAND_RSPS0...................................................................................................... 129
14.2.23 NAND_RSPS1.......................................................................................................130
14.2.24 NAND_RSPS2.......................................................................................................130
14.2.25 NAND_FIFODATA..................................................................................................131
14.2.26 NAND_DEBUG ......................................................................................................131
15 SD/MMC Interface..........................................................................................132
15.1 Description....................................................................................................................132
15.2 Register List..................................................................................................................132
15.2.1 SD_CTL ......................................................................................................................133
15.2.2 SD_CMDRSP.............................................................................................................133
15.2.3 SD_RW ......................................................................................................................134
15.2.4 SD_FIFOCTL ..............................................................................................................135
15.2.5 SD_CMD ....................................................................................................................136
15.2.6 SD_ARG.....................................................................................................................137
15.2.7 SD_CRC7...................................................................................................................137
15.2.8 SD_RSPBUF0 ...........................................................................................................137
15.2.9 SD_RSPBUF1 ...........................................................................................................137
15.2.10 SD_RSPBUF2 .......................................................................................................138
15.2.11 SD_RSPBUF3 .......................................................................................................138
15.2.12 SD_RSPBUF4 .......................................................................................................138
15.2.13 SD_DAT..................................................................................................................138
15.2.14 SD_CLK .................................................................................................................139

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15.2.15 SD_BYTECNT ........................................................................................................139
16 YUV2RGB Interface.........................................................................................140
16.1 Description....................................................................................................................140
16.2 Register List..................................................................................................................140
16.2.1 YUV2RGB_CTL..........................................................................................................140
16.2.2 YU2RGB_DAT............................................................................................................143
16.2.3 YUV2RGB_CLKCTL ...................................................................................................143
16.2.4 YUV2RGB_FrameCount...........................................................................................143
17 USB2.0 SIE.......................................................................................................145
17.1 General Description.....................................................................................................145
18 I2C (2) Interface.............................................................................................. 146
18.1 Description....................................................................................................................146
18.2 Register List..................................................................................................................146
18.2.1 I2Cx_CTL ...................................................................................................................147
18.2.2 I2Cx_CLKDIV.............................................................................................................148
18.2.3 I2Cx_STAT .................................................................................................................148
18.2.4 I2Cx_ADDR ...............................................................................................................150
18.2.5 I2Cx_DAT ...................................................................................................................150
19 UART Interface ................................................................................................ 152
19.1 Description....................................................................................................................152
19.2 Register List..................................................................................................................152
19.2.1 UART2_CTL ...............................................................................................................153
19.2.2 UART2_RXDAT..........................................................................................................155
19.2.3 UART2_TXDAT ..........................................................................................................155
19.2.4 UART2_STAT .............................................................................................................155
20 IR Interface...................................................................................................... 157
20.1 Description....................................................................................................................157
20.2 Register List..................................................................................................................157
20.2.1 IR_PL .........................................................................................................................158
20.2.2 IR_RBC ......................................................................................................................158
21 Key Scan ..........................................................................................................159
21.1 Description....................................................................................................................159
21.2 Register List..................................................................................................................162

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21.2.1 KEY_CTL ....................................................................................................................162
21.2.2 KEY_DAT0 .................................................................................................................163
21.2.3 KEY_DAT1 .................................................................................................................164
21.2.4 KEY_DAT2 .................................................................................................................164
21.2.5 KEY_DAT3 .................................................................................................................164
22 GPIO and Multi-function Configuration ........................................................ 165
22.1 Description....................................................................................................................165
22.1.1 GPIO/Function Pin...................................................................................................165
22.1.2 Multi-function ...........................................................................................................165
22.1.3 Pad with Built-in Resistance ..................................................................................165
22.2 Register List..................................................................................................................166
22.2.1 GPIO_AOUTEN ..........................................................................................................166
22.2.2 GPIO_AINEN .............................................................................................................166
22.2.3 GPIO_ADAT ...............................................................................................................167
22.2.4 GPIO_BOUTEN ..........................................................................................................167
22.2.5 GPIO_BINEN .............................................................................................................167
22.2.6 GPIO_BDAT ...............................................................................................................168
22.2.7 GPIO_MFCTL0 ..........................................................................................................168
22.2.8 GPIO_MFCTL1 ..........................................................................................................169
22.2.9 PAD_DRV...................................................................................................................171
23 DAC and Headphone Driver........................................................................... 173
23.1 Description....................................................................................................................173
23.2 Register List.................................................................................................................. 174
23.2.1 DAC_CTL....................................................................................................................175
23.2.2 DAC_FIFOCTL............................................................................................................176
23.2.3 DAC_DAT ...................................................................................................................178
23.2.4 DAC_Debug...............................................................................................................178
23.2.5 DAC_Analog..............................................................................................................178
24 ADC................................................................................................................... 181
24.1 Description....................................................................................................................181
24.2 Register List..................................................................................................................181
24.2.1 ADC_CTL....................................................................................................................181
24.2.2 ADC_FIFOCTL........................................................................................................... 183
24.2.3 ADC_DAT .................................................................................................................. 184
24.2.4 ADC_Analog............................................................................................................. 185
24.2.5 ADC_Debug ............................................................................................................. 186

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25 Appendix..........................................................................................................188
25.1 Acronym and Abbreviations ...................................................................................... 188

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List of Figures
Figure 1: ATJ2135 Functional Block Diagram .....................................................................28
Figure 2: ATJ2135 Clock Diagram........................................................................................32
Figure 3: CMU Framework.....................................................................................................33
Figure 4: SPECIAL CLK Framework ......................................................................................34
Figure 5: Watch Dog/RTC/Timers Block Diagram..............................................................47
Figure 6: Performance Counters Block Diagram ................................................................75
Figure 7: How to Use MHA in a System..............................................................................101
Figure 8: Application Example of MCA...............................................................................108
Figure 9: NAND_RSPS0 Parity............................................................................................130
Figure 10: I2C Interface Timing..........................................................................................146
Figure 11: Max Key Scan Matrix in Parallel Mode ............................................................159
Figure 12: 8*8 Key Scan Matrix in Serial Mode................................................................160
Figure 13: One Line Scan Timing .......................................................................................161
Figure 14: The Whole Key Scan Timing .............................................................................161
Figure 15: DAC Block Diagram...........................................................................................173
Figure 16: ADDA Analog diagram ......................................................................................174

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List of Tables
Table 1: ATJ2135 Pin Definition ...........................................................................................21
Table 2: ATJ2135 Physical Memory Map .............................................................................29
Table 3: CMU Base Address ..................................................................................................35
Table 4: HOSC/CMU Register Address.................................................................................35
Table 5: CMU_COREPLL Bit Field Description .....................................................................35
Table 6: CMU_DSPPLL Bit Field Description........................................................................36
Table 7: CMU_AUDIOPLL Bit Field Description ....................................................................37
Table 8: CMU_BUSCLK Bit Field Description .......................................................................38
Table 9: CMU_SDRCLK Bit Field Description.......................................................................39
Table 10: CMU_NANDCLK Bit Field Description..................................................................40
Table 11: CMU_SDCLK Bit Field Description .......................................................................40
Table 12: CMU_UARTxCLK Bit Field Description .................................................................41
Table 13: CMU_MHACLK Bit Field Description ....................................................................41
Table 14: CMU_DMACLK Bit Field Description ....................................................................41
Table 15: CMU_FMCLK Bit Field Description.......................................................................42
Table 16: CMU_MCACLK Bit Field Description ....................................................................43
Table 17: CMU_DEVCLKEN Bit Field Description .................................................................43
Table 18: CMU_DEVRST Bit Field Description .....................................................................45
Table 19: RTC Base Address.................................................................................................47
Table 20: HOSC/CMU Register Address...............................................................................48
Table 21: RTC_CTL Bit Field Description..............................................................................48
Table 22: RTC_DHMS Bit Field Description .........................................................................49
Table 23: RTC_YMD Bit Field Description............................................................................50
Table 24: RTC_DHMSALM Bit Field Description..................................................................50
Table 25: RTC_YMDALM Bit Field Description.....................................................................51
Table 26: RTC_WDCTL Bit Field Description........................................................................51
Table 27: RTC_T0CTL Bit Field Description..........................................................................52
Table 28: RTC_T0 Bit Field Description................................................................................53
Table 29: RTC_T1CTL Bit Field Description .........................................................................53
Table 30: RTC_T1 Bit Field Description................................................................................54
Table 31: Interrupt Controller Connects to CPU...................................................................55
Table 32: Interrupt Sources...................................................................................................55
Table 33: INTC Base Address................................................................................................56
Table 34: INTC Register Address ..........................................................................................56

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Table 35: INTC_PD Bit Field Description..............................................................................57
Table 36: INTC_MSK Bit Field Description...........................................................................57
Table 37: INTC_CFGx List.......................................................................................................58
Table 38: INTC_CFGx Bit Field Description ..........................................................................58
Table 39: INTC_EXTCTL Bit Field Description ......................................................................59
Table 40: CMU Block Base Address .....................................................................................62
Table 41: Configuration Registers Offset.............................................................................62
Table 42: DC/DC Converter and Regulator’s Register Description....................................62
Table 43: Low Resolution ADC Data Register Description .................................................64
Table 44: PMU Charger Control and Status Register Description......................................65
Table 45: Coprocessor 0 Registers.......................................................................................68
Table 46: IntCtl Register Format ..........................................................................................70
Table 47: IntCtl Bit Field Description ....................................................................................70
Table 48: SRSCtl Bit Field Description.................................................................................70
Table 49: PRId Register Format ...........................................................................................71
Table 50: PRId Bit Field Description.....................................................................................71
Table 51: EBase Bit Field Description ..................................................................................72
Table 52: Config Bit Field Description..................................................................................72
Table 53: Config1 Bit Field Description — Select 1 .............................................................73
Table 54: Config2 Bit Field Description — Select 2.............................................................74
Table 55: Config3 Bit Field Description ...............................................................................74
Table 56: PC Base Address ...................................................................................................75
Table 57: Performance Counters Registers.........................................................................75
Table 58: PCNT_CTL Bit Field Description ...........................................................................76
Table 59: PCNT_PCx Bit Field Description ...........................................................................77
Table 60: SDR Base Address ................................................................................................79
Table 61: SDRAM Interface Configuration Registers..........................................................79
Table 62: SDR_CTL Bit Field Description .............................................................................80
Table 63: SDR_EN Bit Field Description...............................................................................81
Table 64: SDR_CMD Bit Field Description ...........................................................................81
Table 65: SDR_STAT Bit Field Description ...........................................................................82
Table 66: SDR_AUTORFC Bit Field Description ...................................................................83
Table 67: SDR_MODE Bit Field Description .........................................................................83
Table 68: SDR_MOBILE Bit Field Description......................................................................84
Table 69: SRAMOC Base Address ........................................................................................85
Table 70: SRAM Interface Configuration Registers ............................................................85
Table 71: SRAMOC_CTL Bit Field Description .....................................................................85
Table 72: SRAMOC_STAT Bit Field Description ...................................................................86
Table 73: DMA Base Address ...............................................................................................87
Table 74: Bus Controller and DMA Control Register Address.............................................87

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Table 75: General DMA Channel Registers Block Base Address.......................................87
Table 76: General DMA Channel Configuration Registers..................................................87
Table 77: DMA_CTL Bit Field Description.............................................................................88
Table 78: DMA_IRQEN Bit Field Description........................................................................89
Table 79: DMA_IRQPD Bit Field Description .......................................................................90
Table 80: DMA_MODEx Bit Field Description ......................................................................91
Table 81: DMA_SRCx Bit Field Description..........................................................................93
Table 82: DMA_DSTx Bit Field Description..........................................................................94
Table 83: DMA_CNTx Bit Field Description..........................................................................94
Table 84: DMA_CNTx Bit Field Description..........................................................................94
Table 85: DMA_CMDx Bit Field Description.........................................................................94
Table 86: DSP Base Address ................................................................................................96
Table 87: DSP Register Address ...........................................................................................96
Table 88: DSP_HDR0 Bit Field Description .........................................................................97
Table 89: DSP_HDR1 Bit Field Description .........................................................................97
Table 90: DSP_HDR2 Bit Field Description .........................................................................98
Table 91: DSP_HDR3 Bit Field Description .........................................................................98
Table 92: DSP_HDR4 Bit Field Description .........................................................................98
Table 93: DSP_HDR5 Bit Field Description .........................................................................98
Table 94: DSP_HSR6 Bit Field Description..........................................................................99
Table 95: DSP_HSR7 Bit Field Description..........................................................................99
Table 96: DSP_CTL Bit Field Description .............................................................................99
Table 97: Functions and Application of MHA.....................................................................101
Table 98: MHA Base Address..............................................................................................102
Table 99: MHA IO Registers ................................................................................................102
Table 100: MHA Memory ....................................................................................................102
Table 101: MHA_CTL Bit Field Description ........................................................................102
Table 102: Q Table Mapping ...............................................................................................103
Table 103: B1/B2 Mapping ................................................................................................103
Table 104: MHA_CFG Bit Field Description .......................................................................104
Table 105: MHA_DCSCL0 Bit Field Description ................................................................106
Table 106: MHA_DCSCL1 Bit Field Description ................................................................106
Table 107: MHA_DCSCL2 Bit Field Description.................................................................107
Table 108: MHA_DCSCL3 Bit Field Description ................................................................107
Table 109: MHA_QSCL Bit Field Description .....................................................................107
Table 110: MCA Base Address............................................................................................108
Table 111: MCA IO Registers ..............................................................................................108
Table 112: MCA Memory.....................................................................................................108
Table 113: MCA_CTL Bit Field Description ........................................................................109
Table 114: NAND FLASH Block Base Address...................................................................111

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Table 115: NAND FLASH Register Address .......................................................................111
Table 116: NAND_CTL Bit Field Description......................................................................112
Table 117: NAND_STATUS Bit Field Description................................................................114
Table 118: NAND_FIFOTIM Bit Field Description ..............................................................115
Table 119: NAND_CLKCTL Bit Field Description ...............................................................116
Table 120: NAND_BYTECNT Bit Field Description.............................................................116
Table 121: NAND_ADDRLO1234 Bit Field Description ....................................................117
Table 122: NAND_ADDRLO56 Bit Field Description.........................................................117
Table 123: NAND_ ADDRHI1234 Bit Field Description ....................................................117
Table 124: NAND_ ADDRHI56 Bit Field Description.........................................................118
Table 125: NAND_BUF0 Bit Field Description ...................................................................118
Table 126: NAND_BUF1 Bit Field Description ...................................................................119
Table 127: NAND_CMD (General Mode) Bit Field Description .........................................119
Table 128: NAND_CMD (Spare Mode) Bit Field Description ............................................120
Table 129: NAND_ECCCTL Bit Field Description ...............................................................122
Table 130: NAND_HAMECC0 Bit Field Description...........................................................123
Table 131: NAND_HAMECC1 Bit Field Description ...........................................................125
Table 132: NAND_HAMECC2 Bit Field Description...........................................................126
Table 133: NAND_HAMCEC Bit Field Description .............................................................127
Table 134: NAND_RSE0 Bit Field Description...................................................................127
Table 135: NAND_RSE1 Bit Field Description...................................................................128
Table 136: NAND_RSE2 Bit Field Description...................................................................128
Table 137: NAND_RSE3 Bit Field Description ...................................................................129
Table 138: NAND_RSPS0 Bit Field Description ................................................................130
Table 139: NAND_RSPS1 Bit Field Description ................................................................130
Table 140: NAND_RSPS2 Bit Field Description ................................................................130
Table 141: NAND_RSPS2 Bit Field Description.................................................................131
Table 142: NAND_DEBUG Bit Field Description ................................................................131
Table 143: SD/MMC Block Base Address .........................................................................132
Table 144: SD/MMC Register Address ..............................................................................132
Table 145: SD_CTL Bit Field Description ...........................................................................133
Table 146: SD_CMDRSP Bit Field Description ..................................................................134
Table 147: SD_RW Bit Field Description............................................................................134
Table 148: SD_FIFOCTL Bit Field Description....................................................................135
Table 149: SD_CMD Bit Field Description .........................................................................136
Table 150: SD_ARG Bit Field Description ..........................................................................137
Table 151: SD_CRC7 Bit Field Description ........................................................................137
Table 152: SD_RSPBUF0 Bit Field Description .................................................................137
Table 153: SD_RSPBUF1 Bit Field Description .................................................................137
Table 154: SD_RSPBUF2 Bit Field Description .................................................................138

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Table 155: SD_RSPBUF3 Bit Field Description .................................................................138
Table 156: SD_RSPBUF4 Bit Field Description .................................................................138
Table 157: SD_DAT Bit Field Description ...........................................................................139
Table 158: SD_CLK Bit Field Description...........................................................................139
Table 159: SD_BYTECNT Bit Field Description..................................................................139
Table 160: YUV2RGB Registers Block Base Address........................................................140
Table 161: YUV2RGB Registers Offset Address ................................................................140
Table 162: YUV2RGB_CTL Bit Field Description................................................................141
Table 163: YU2RGB_DAT Bit Field Description .................................................................143
Table 164: YUV2RGB_CLKCTL Bit Field Description .........................................................143
Table 165: YUV2RGB_FrameCount Bit Field Description .................................................143
Table 166: I2C Register Block Base Address ....................................................................146
Table 167: I2C Registers Offset Address ...........................................................................146
Table 168: I2Cx_CTL Bit Field Description.........................................................................147
Table 169: I2Cx_CLKDIV Bit Field Description ..................................................................148
Table 170: I2Cx_STAT Bit Field Description .......................................................................148
Table 171: I2Cx_ADDR Bit Field Description .....................................................................150
Table 172: I2Cx_DAT Bit Field Description.........................................................................151
Table 173: UART Registers Block Base Address ...............................................................152
Table 174: UART Registers Offset Address ........................................................................152
Table 175: UART2_CTL Bit Field Description.....................................................................153
Table 176: UART2_RXDAT Bit Field Description................................................................155
Table 177: UART2_TXDAT Bit Field Description.................................................................155
Table 178: UART2_STAT Bit Field Description...................................................................155
Table 179: IR Interface Modes............................................................................................157
Table 180: IR Registers Block Base Address ....................................................................157
Table 181: IR Registers Offset Address .............................................................................158
Table 182: IR_PL Bit Field Description ..............................................................................158
Table 183: IR_RBC Bit Field Description ...........................................................................158
Table 184: Key Scan Registers Block Base Address ........................................................162
Table 185: Key Scan Registers Offset Address.................................................................162
Table 186: KEY_CTL Bit Field Description .........................................................................162
Table 187: KEY_DAT0 Bit Field Description.......................................................................163
Table 188: KEY_DAT1 Bit Field Description.......................................................................164
Table 189: KEY_DAT2 Bit Field Description.......................................................................164
Table 190: KEY_DAT3 Bit Field Description.......................................................................164
Table 191: GPIO Registers Block Base Address................................................................166
Table 192: GPIO Registers Offset Address........................................................................166
Table 193: GPIO_AOUTEN Bit Field Description................................................................166
Table 194: GPIO_AINEN Bit Field Description ...................................................................166

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Table 195: GPIO_ADAT Bit Field Description.....................................................................167
Table 196: GPIO_BOUTEN Bit Field Description................................................................167
Table 197: GPIO_BINEN Bit Field Description ...................................................................167
Table 198: GPIO_BDAT Bit Field Description.....................................................................168
Table 199: GPIO_MFCTL0 Bit Field Description ................................................................168
Table 200: GPIO_MFCTL1 Bit Field Description ................................................................170
Table 201: PAD Driver Bit Field Description ......................................................................171
Table 202: DAC Registers Block Base Address.................................................................174
Table 203: DAC Registers Offset Address .........................................................................174
Table 204: DAC_CTL Bit Field Description .........................................................................175
Table 205: DAC_FIFOCTL Bit Field Description .................................................................176
Table 206: DAC_DAT Bit Field Description.........................................................................178
Table 207: DAC_Debug Bit Field Description.....................................................................178
Table 208: DAC_Analog Bit Field Description ...................................................................178
Table 209: ADC Registers Block Base Address.................................................................181
Table 210: ADC Registers Offset Address .........................................................................181
Table 211: ADC_CTL Bit Field Description.........................................................................181
Table 212: ADC_FIFOCTL Bit Field Description .................................................................183
Table 213: ADC_DAT Bit Field Description.........................................................................185
Table 214: ADC_Analog Bit Field Description ...................................................................185
Table 215: ADC_Debug Bit Field Description ....................................................................186

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Revision History
Date Revision Description Author
Dec 2006 1.0 Initial release; Fionawx
Jan 2007 1.1 Updated based on SD Spec 0.40M
(061124) Fionawx

ATJ2135 PROGRAMMING GUIDE
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1Introduction
Overview
The Actions ATJ2135 is a highly integrated 32bit RISC-based SoC for digital media
solution. The RISC architecture and high speed bus controller are capable of achieving high
performance with low power consumption. With a built-in JPEG co-processor, this media
platform is capable of processing both JPEG and MJPEG format with higher efficiency. The
integrated high-speed USB 2.0 SIE enables the platform to act as a mass storage device at
the speed up to 480Mbps. The audio codec in the SoC is based on sigma-delta modulation,
providing high performance with low power consumption as well as allowing the flexible
adjustment of sample rates from 8k to 96k. The built-in audio codec is able to switch inputs
within headphones, microphones, FM radios and direct drive for low impedance earphones.
The ATJ2135 also provides integrated SDRAM and Flash interfaces; IIC, IR and UART etc.
interfaces for changeable control and transfer modes. The ATJ2135 therefore provides a true
“ALL-IN-ONE” solution that is ideally suited for highly optimized digital media devices.
Features
Audio playing support: MP3, WMA, OGG, APE, WAV
Audio recording support: ADPCM, MP3
Video playing support: AMVB, XVID, MJPEG QVGA 25fp
Image view support: JPEG, BMP, GIF
USB 2.0 Device
High Speed NAND I/F
Supports SLC & MLC device
Multi-bit Error Correction
Supports SD/MMC FLASH Card
OLED, TFT, STN support
Integrated stereo DAC & ADC
Li-Ion battery charger
11-16V backlight driver for LED
6bit battery monitoring ADC