Active Silicon PHOENIX User manual
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PHOENIX
USER MANUAL
Active Silicon
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Revision History
Version Comments
v1.0 14-Oct-2005 First Release.
v1.1 25-Oct-2005 Updated the Acquisition Trigger Control section.
v1.2 28-Mar-2007 Added PCI Express boards. Added block diagrams to Camera Control section.
v1.3 2-May-2008 Added PoCL LED section.
v1.4 16-Jul-2008 Updated some example code.
v1.5 05-Jan-2010 Updated Phoenix board overview. New US address.
v1.6 14-Sep-2010 New US address.
Disclaimer
While every precaution has been taken in the preparation of this manual, Active Silicon assumes no responsibility
for errors or omissions. Active Silicon reserves the right to change the specification of the product described within
this manual and the manual itself at any time without notice and without obligation of Active Silicon to notify any
person of such revisions or changes.
Copyright Notice
Copyright ©2005-2010 Active Silicon. All rights reserved. This document may not in whole or in part, be
reproduced, transmitted, transcribed, stored in any electronic medium or machine readable form, or translated into
any language or computer language without the prior written consent of Active Silicon.
Trademarks
All trademarks and registered trademarks are the property of their respective owners.
Part Information
Part Number: PHX-MAN-USER
Version v1.6 14-Sep-2010
Contact Details
Web
Sales
Support
www.activesilicon.com
Europe:
Active Silicon Limited
Pinewood Mews, Bond Close, Iver,
Bucks, SL0 0NA, UK.
Tel: +44 (0)1753 650600
Fax: +44 (0)1753 651661
North America:
Active Silicon, Inc.
479 Jumpers Hole Road, Suite 301
Severna Park, MD 21146, USA
Tel +1 410-696-7642
Fax +1 410-696-7643
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Phoenix User Manual Introduction v
Table of Contents
Introduction................................................................................................................................................................... 1
Scope......................................................................................................................................................................... 1
Document Structure .................................................................................................................................................. 1
Documentation Overview ............................................................................................................................................. 2
GETTING STARTED .............................................................................................................................................. 2
FRAME GRABBER DATASHEETS ...................................................................................................................... 2
HARDWARE MANUALS....................................................................................................................................... 3
SOFTWARE MANUALS ........................................................................................................................................ 3
Phoenix Board Overview .............................................................................................................................................. 4
VARIANTS AND FORM FACTORS...................................................................................................................... 4
FEATURE LIST ....................................................................................................................................................... 4
THE THREE LEDs (1, 2, 3) ..................................................................................................................................... 5
THE PoCL LEDs (4, 5)............................................................................................................................................. 5
BLOCK DIAGRAM ................................................................................................................................................. 6
SDK Overview............................................................................................................................................................ 10
SDK Examples............................................................................................................................................................ 11
INITIALISING THE PHOENIX BOARD ............................................................................................................. 11
PCI BANDWIDTH MEASUREMENT ................................................................................................................. 11
SINGLE ACQUISITION WITH FILE SAVE ....................................................................................................... 11
LIVE ACQUISITION............................................................................................................................................. 11
BUFFER CONTROL.............................................................................................................................................. 12
IMAGE CONVERSION......................................................................................................................................... 12
SERIAL I/O ............................................................................................................................................................ 12
LUT CONTROL ..................................................................................................................................................... 12
TRIGGER CONTROL............................................................................................................................................ 12
MISCELLANEOUS ............................................................................................................................................... 12
Phoenix Board Control................................................................................................................................................ 13
CONFIGURING PHOENIX................................................................................................................................... 13
Camera handle..................................................................................................................................................... 13
Phoenix Configuration File ................................................................................................................................. 13
Configuration Options......................................................................................................................................... 13
Error Handler ...................................................................................................................................................... 14
Examples............................................................................................................................................................. 14
CAMERA TAP CONFIGURATION ..................................................................................................................... 15
Single tap............................................................................................................................................................. 15
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Phoenix User Manual Introduction vi
Dual horizontal taps.............................................................................................................................................15
Dual horizontal and dual vertical taps .................................................................................................................16
SDK Concepts .............................................................................................................................................................17
USING THE PHX_CACHE_FLUSH PARAMETER............................................................................................17
PHOENIX ERROR HANDLING ...........................................................................................................................17
Error Status Codes...............................................................................................................................................17
Error Information.................................................................................................................................................19
Error Handler Function........................................................................................................................................19
Decoding Error Codes .........................................................................................................................................19
I/O PORT ACCESS ................................................................................................................................................20
Absolute / Relative I/O Port Access ....................................................................................................................20
etPhxIoMethod for I/O Port Access ....................................................................................................................20
Examples .............................................................................................................................................................21
HOW TO USE THE DISPLAY LIBRARY............................................................................................................21
Speed and data rate issues ...................................................................................................................................21
Double Buffering.................................................................................................................................................22
Display buffer destinations..................................................................................................................................22
PHX_EVENTCOUNT / PHX_EVENTCOUNT_AT_GATE ................................................................................23
HOW TO CREATE A SMALLER EXECUTABLE BY LINKING FIRMWARE OBJECT FILES ....................23
Phoenix Firmware Object Files ...........................................................................................................................23
Extract the Firmware Object File(s) ....................................................................................................................24
Link the Application to the Required Firmware Object File(s)...........................................................................24
Camera Control ...........................................................................................................................................................26
EXPOSURE CONTROL.........................................................................................................................................26
Exposure Control Output Signals ........................................................................................................................26
Exposure Control Methods..................................................................................................................................27
Exposure Control Output Block Diagram ...........................................................................................................27
Exposure Control Internal Timers .......................................................................................................................28
Initiating an Exposure..........................................................................................................................................28
Exposure Trigger Block Diagram........................................................................................................................29
ACQUISITION TRIGGER CONTROL .................................................................................................................30
External Trigger Source.......................................................................................................................................30
Acquisition Trigger Block Diagram ....................................................................................................................31
Internal Control ...................................................................................................................................................31
LINE SCAN CONTROL ........................................................................................................................................32
Acquisition Control .....................................................................................................................................................33
USING A CALLBACK ..........................................................................................................................................33
Implementation ....................................................................................................................................................33
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Phoenix User Manual Introduction vii
Example .............................................................................................................................................................. 34
SEQUENCE CONTROL........................................................................................................................................ 35
Examples............................................................................................................................................................. 36
HOW PHOENIX USES MEMORY BUFFERS..................................................................................................... 37
Internal Memory.................................................................................................................................................. 37
Retrieving the Buffer Details .............................................................................................................................. 37
Virtual Memory................................................................................................................................................... 37
Physical Memory ................................................................................................................................................ 38
IMAGE CORRUPTION (FIFO OVERFLOW)...................................................................................................... 39
Image Slip ........................................................................................................................................................... 39
Severe Image Corruption .................................................................................................................................... 40
Image Control ............................................................................................................................................................. 42
IMAGE DATA CONTROL.................................................................................................................................... 42
Camera image data .............................................................................................................................................. 42
Destination buffer ............................................................................................................................................... 43
LOOK-UP TABLE CONTROL ............................................................................................................................. 44
LUT identifiers.................................................................................................................................................... 44
LUT settings........................................................................................................................................................ 44
User allocated LUT data ..................................................................................................................................... 45
Setting the Brightness of an Internal LUT .......................................................................................................... 45
Using a Custom LUT .......................................................................................................................................... 45
DISPLAYING IMAGES WITH GREATER THAN 8-BIT DATA....................................................................... 46
SAVING IMAGES WITH GREATER THAN 8-BIT DATA................................................................................ 46
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Phoenix User Manual Introduction 1
Introduction
SCOPE
This document provides overview information regarding the Phoenix series of frame grabbers and answers
DOCUMENT STRUCTURE
The document is broken down into the following major sections
•Documentation Overview
•Phoenix Board Overview
•SDK Overview
•SDK Examples
•Phoenix Board Control
•SDK Concepts
•Camera Control
•Acquisition Control
•Image Control
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Phoenix User Manual Documentation Overview 2
Documentation Overview
GETTING STARTED
•Quickstart Guide. There are a number of quickstart guides for using Phoenix on various operating
systems.
•Installation Guide (part number PHX-MAN-IG). This document describes how to install the software,
configure your computer and get your Phoenix board running.
•User Manual (part number PHX-MAN-USER). This document!
FRAME GRABBER DATASHEETS
•D24CL PCI Camera Link. The Phoenix-D24CL is a PCI board for the acquisition of digital data from
a variety of Camera Link sources, including digital frame capture and line scan cameras. It supports all
the formats of Base configuration, i.e. single 8 to 16 bit data, through 8 bit RGB, to dual tap 12 bit
sources.
•D24CL PMC Camera Link. This is the PMC version of the above board.
•D24CL PC/104-Plus Camera Link. This is the PC/104-Plus version of the above board.
•D24CL PCI Express Camera Link. This is the PCI Express version of the above board.
•D36 PCI LVDS. The Phoenix-D36 is a PCI board for the acquisition of digital data from a variety of
sources, including digital frame capture and line scan cameras. It has 36 bits used for input data, with 4
bits for control. This provides support for a single 12 bit RGB or 32 bit mono data source, including
multi-tap cameras. The 4 bit control inputs are dedicated as Frame Enable, Line Enable, Data Enable
and Pixel Clock. Alternatively four of the data inputs can be re-assigned as an additional control port,
thus allowing two independent 16 bit mono cameras to be supported. Data widths up to the above
maximums are also handled, i.e. 8, 10 or 12 bit RGB and 8, 10, 12, 14, 16 or 32 bit mono.
•D36 PCI Express . This is the PCI Express version of the above board.
•D48CL PCI Camera Link. The Phoenix-D48CL is a PCI board for the acquisition of digital data from
a variety of Camera Link sources, including digital frame capture and line scan cameras. It supports all
the formats of the Base and Medium configurations, i.e. single 8 to 16 bit data, through 12 bit RGB, to
four tap 12 bit sources, as well as dual Base configuration, i.e. acquisition from two asynchronous Base
cameras.
•D48CL CPCI Camera Link. This is the CompactPCI version of the above board.
•D48CL PCI Express Camera Link. This is the PCI Express version of the above board.
•D48CL PCI/104-Express Camera Link. This is a PCI/104-Express version of the above board.
•D64CL PCI Express Camera Link. The Phoenix-D64CL is a PCI Express board which supports
acquisition from Base, Medium and Full Camera Link configurations, i.e. single tap 8 to 16 bit data,
through 12-bit RGB to eight tap 8 bit sources, as well as ten tap 8-bit and eight tap 10-bit configurations.
•D10HDSDI PCI Express HD-SDI. The Phoenix-D10HDSDI is a PCI Express board for the
acquisition of SDI and HD-SDI data from a variety of sources. It supports HD-SDI video sources up to
and including 1080i@60 data rates.
•D20HDSDI PCI Express HD-SDI. This is a dual channel version of the above boards. It supports two
HD-SDI video sources up to and including 1080i@60 data rates.
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Phoenix User Manual Documentation Overview 3
HARDWARE MANUALS
•Interface Guide (part number PHX-MAN-IFG). This manual describes how to interface a Phoenix
Digital product to cameras and other external devices, i.e. acquisition trigger sources, shaft encoders,
PLCs, etc. It details information on product pinouts, standard available cables and electrical
specifications.
•Hardware Guide PC/104-Plus. This document explains the issues involved when using Phoenix in a
PC/104-Plus system.
•Approvals Manual (part number PHX-MAN-APPR). This document contains EMC statements and
Compliance notices.
•Hardware Failure Report Form.
SOFTWARE MANUALS
•Phoenix Library API Reference Manual (part number PHX-MAN-API). This document describes the
functional specification of the PHOENIX software library. This library provides a platform independent
interface to the acquisition and control features of a Phoenix image capture device.
•Buffer Library API Reference Manual (part number PBL-MAN-API). This document describes the
functional specification of the Phoenix Buffer Library (PBL). This library allows the user to easily
control the data buffers involved when using a Phoenix image capture device.
•Image Library API Reference Manual (part number PIL-MAN-API). This document describes the
functional specification of the Phoenix Image Library (PIL). This library allows the user to easily
process the data buffers involved when using a Phoenix image capture device.
•Display Library API Reference Manual (part number PDL-MAN-API). This document describes the
functional specification of the Phoenix Display Library (PDL). This library allows the user to easily
display images captured using a Phoenix image capture device. PDL is closely coupled to the Phoenix
image capture library (PHX), configuring itself using the parameters of the associated Phoenix instance.
•Control Class API Reference Manual (part number PCC-MAN-API). This document describes the
functional specification of the Phoenix Control Class (PCC). This class provides a property sheet
control, which allows the user to easily control the Phoenix image capture device.
•VxWorks Library Developer’s Manual (part number PHX-MAN-VXW). This manual describes the
low-level functions of the VxWorks driver library for the Phoenix series of acquisition cards. This
library provides a hardware platform independent method of accessing Phoenix cards, but allows the
user to add enhanced functionality specific to a particular platform via a set of installable callout
functions.
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Phoenix User Manual Phoenix Board Overview 4
Phoenix Board Overview
VARIANTS AND FORM FACTORS
The following products are available in the Phoenix range:
•D24CL : Base only Camera Link frame grabber,
•D48CL : Base, Dual Base and Medium Camera Link frame grabber,
•D10HDSDI : Single input HD-SDI frame grabber,
•D20HDSDI : Dual input HD-SDI frame grabber,
•D36 : 36-bit LVDS frame grabber
The Phoenix boards are available in PCI Express, PCI, CompactPCI, PMC, PCI/104-Express and PC/104-
Plus form factors.
FEATURE LIST
PHX-D24CL PHX-D48CL PHX-D64CL DxHDSDI PHX-D36
PCI Express (x1) 33- 33
PCI Express (x4) - 333
PCI (32-bit / 33MHz) 3- 3- 3
LVDS Input - - - - 36-bit
Camera Link Base 1 2 1 - -
Camera Link Medium - 1 1 - -
Camera Link Full - - 1 - -
HD-SDI up to
1080i60.
- - - 3-
Max Pixel Clock 85MHz 85MHz 60MHz - 60MHz
LVDS I/O 4 4 4 4 4
Camera Link Controls 4 8 - - -
24V Opto-isolated I/O 4 4 4 4 4
TTL I/O 16 16 16 16 16
Serial Ports 1 2 2 2 2
Stereo Cameras - 3333
DMA to Host or
Display
33333
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THE THREE LEDS (1, 2, 3)
•LED1 : Indicates that the board has powered up. When the board is inactive, it stays illuminated.
For each PCI access to Phoenix, this LED will briefly extinguish.
•LED2 : Flashes to indicate that captured image data from channel ‘A’ is being transferred across
the PCI bus. Note that it can appear dimly lit when flashing at a sufficiently high rate.
•LED3 : This LED performs the same function as LED2, but applies to channel ‘B’.
THE POCL LEDS (4, 5)
The Phoenix Camera Link boards support the Power over Camera Link (PoCL) functionality and are able to
provide power to PoCL enabled cameras via the Camera Link data cable thereby removing the need for a
separate power supply. In addition to this the Phoenix implements SafePower, an intelligent sense
mechanism which detects the presence of a PoCL camera before applying power to it. This safety
mechanism ensures that power is not applied to conventional non-PoCL cameras. Phoenix can supply up to
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Phoenix User Manual Phoenix Board Overview 6
4W at a nominal 12V +/- 1V, as required by the PoCL specification. The PoCL specification also makes
allowance for up to a 1V drop in the cable, thus providing 10V to 13V at the camera input. The LEDs
operate as follows:
•Flashing Amber : Non PoCL camera or cable detected (i.e. pins 1/26 shorted to pins 13/14), but
no clock output from the camera.
•Solid Amber : Non PoCL camera or cable detected, but with a valid clock output from the camera.
•Flashing Green : PoCL cable and camera have been detected (i.e. a 52uA sense current developed
a 0.52V voltage across pins 1/26 and 13/14), and 12V power output enabled to the camera, but no
valid camera clock yet received.
•Solid Green : PoCL cable and camera detected, 12V power output applied to the camera, and a
valid clock output from the camera detected.
•No LEDs : Sensing mode, whereby the Phoenix board is scanning for any PoCL or non-PoCL
camera to be connected.
Note that if the clock is lost whilst the board is in the solid Amber or Green states, Phoenix will revert back
to sensing mode to allow users to change between PoCL and non-PoCL cameras.
BLOCK DIAGRAM
The following block diagram shows the Phoenix D48CL board as an example.
CONNECTORS
CAMERA
LIN
K
B
CHANNEL B
CHANNEL A
CAMERA
LINK
I/F
ROI
DATAMAPPER
& LUT
ACQUISITION
CONTROL
CAMERA
FIFO
TRIG
SEL
PCI FIFO
BUS MASTER
CONTROL
EIA-644
CTRL
I/O
EXPOSURE
CONTROL REF
CLK
TTL I/O
UART
OPTO I/O
& EIA-644 IN
CONFIGURATION
INFO
EIA-644
BUFFERS
PCI
INTERFACE
CAMERA
LINK A
TTL
OPTO
&
EIA-644
CHAIN
COUNTER
TIMERS
N
ote: This is a simplified block diagram that only shows the main data and control paths.
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Camera Clock: Phoenix supports effective clock rates from DC to the Camera Link maximum of
85MHz, using the Camera Link Strobe (STB) and Data Valid (DVAL) signals.
Camera FIFO: Data from the video source is stored in a FIFO prior to being processed by Phoenix.
Acquisition
Control:
The acquisition trigger control module is used to determine which video frames to
acquire from the camera. The system can be configured for a single trigger event to
acquire all subsequent frames, a trigger event per frame, or continuous acquisition
irrespective of the trigger condition. The trigger event is programmable between either
level or edge sensing on one of the opto-isolated or EIA-644 control inputs.
When running in linescan mode, there is an additional mode that uses the active trigger
input as an envelope signal. In this mode all lines are acquired whilst the trigger input is
asserted. The hardware can also delay the trigger event by a fixed time period or
number of lines, and allows the trigger event transducer to be located remotely from the
camera.
Region of Interest: The Region Of Interest (ROI) controls which part of the camera output data to acquire.
In areascan mode, this is a rectangular region with software programmable width,
height and x / y offset. Linescan mode is similar, allowing control of the width and x
offset, with the height control being used to package the data into pseudo frames for
subsequent processing by the user’s application. Phoenix supports an additional mode
(DataStream) whereby data is acquired based upon the control inputs, e.g. all data is
acquired when Frame Valid (FVAL) and Line Valid (LVAL) are both asserted. This is
necessary for cameras that output their own arbitrary ROIs within a single video frame,
or those that vary the amount of data output on each line.
Sub-Sampling: Software controlled hardware sub-sampling is also supported. A factor of x1, x2, x4 or
x8 can be independently selected for both x and y directions, e.g. a horizontal factor of
x4 and a vertical factor of x2 would acquire every 4th pixel across a line and every 2nd
line down the frame.
DataMapper: The raw camera data can be reformatted in hardware for ease of subsequent processing.
For example, a mono data source can be converted into 32 bit colour data, ready to be
sent directly to graphics card memory, thus reducing the host processor overhead. The
optimum use of system resources is determined by the user’s application, e.g. packing
mono data into 32 bit colour reduces the host processor overhead at the expense of
increasing the amount of data transferred across the PCI bus.
The output formats supported include, 8, 16 and 32 bit mono, as well as 15, 16, 24, 32
and 48 bit colour in both RGB and BGR ordering, thus supporting big and little endian
processor formats. The data is also pre-packed into a 64 bit stream, prior to being sent
across the PCI bus, for maximum transfer performance.
LUT: A 16 bit in, 16 bit out (i.e. 65,536 by 16) LUT per channel allows arbitrary mappings
between the input data from the video source and the output data to the destination
memory. This allows functions such as gamma correction, brightness, contrast and
thresholding to be performed in real time in hardware on a per colour or per camera
basis. The LUT may also be used to shift the LSB aligned video data to MSB alignment
ready for processing.
PCI FIFO: PCI64 version: A 1024 by 64 bit FIFO per channel provides buffering between the
camera and the PCI bus. If the board is being used in single camera mode, then both
channels are used providing a 2048 by 64 FIFO.
PCI64U version: Similarly, 512 by 64 bit per channel, or 1024 by 64 bit in single
camera mode.
Note that this is not a frame store; Phoenix uses high speed Bus Mastering (DMA) to
transfer the camera data into system memory, and therefore the image size is only
limited by the amount of memory available on the host.
Bus Master Bus Master Control is provided by a dedicated RISC processor and a highly optimised
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Control: PCI Bus Master (DMA) engine. The RISC processor reads transfer length and
destination address instructions across the PCI bus from host memory, and loads these
into the PCI Bus Master engine with no host CPU overhead.
The DMA engine then transfers the video data at the full PCI bus rate into host memory,
thus achieving the maximum burst rate of 533MBytes/sec. When the current instruction
has completed, the RISC processor optionally generates a PCI interrupt to signal that the
transfer has completed, before either halting or retrieving the next instruction.
The RISC processor also supports jump instructions that allow a single piece of RISC
code to continuously loop without any CPU intervention.
Interrupts: An interrupt signal is available, and can be configured via software to interrupt on a
number of different events, including acquisition complete, FIFO overflow, Start/End of
Frame/Line, etc.
Counter Timers: Four 32 bit counter timers are available for each channel of the Phoenix. The counter
timers are dedicated for the following functions:
1. Astable timer used as a line rate generator for linescan cameras, or as an acquisition
trigger for areascan cameras, thus controlling the overall frame rate. The period of
the astable can be set from 1μs up to 70 minutes in 1μs increments.
2. Dual monostables for generating two exposure output signals, e.g. ExSync and
PRIN. Both monostables are triggered by the same software selectable event but
can be programmed with different time periods, once again to 1μs resolution. This
provides a flexible exposure control system.
3. Trigger delay counter used to postpone acquisition triggering by a programmable
time delay or line count. This allows the acquisition trigger sensor to be mounted
remotely from the camera. (Note: As the counter is non-retriggerable, subsequent
trigger events will be ignored until a pending event has completed its delay).
4. A versatile event counter is provided to count a number of different events types -
Lines (LVAL), Frames (FVAL) or microseconds, within a specified gate condition
- Line (LVAL), Frame (FVAL), Acquisition Trigger or Entire Acquisition. The
event count provides readings for both the current value, as well as the final value
at the end of the previous gate condition. For example the event counter can be
configured to provide the current line number within a frame, as well as the total
number of lines in the previous frame. Other uses include providing the frame
period, the number of lines in the previous acquisition trigger envelope – and hence
how much data there is to process, or the number of images processed so far.
Camera Control
Outputs:
Two 4 bit EIA-644 (LVDS) output ports are provided to interface with the camera.
Each bit can be individually set to a logical “1” or “0” under software control or used to
drive the camera with exposure control pulses from the counter timer module.
The ports are on the Camera Link connectors.
Opto-Isolated I/O: 4 bits of opto-isolated I/O are provided to interface to external systems. As standard,
Phoenix is configured with 2 bits of input and 2 bits of output, but this can be varied as
factory build option. The outputs are designed to sink up to 20mA, and will withstand
24V when “off”. The inputs sense voltages between 3.3V and 24V as a logic high input.
A 4.7kΩcurrent limiting series resistor is fitted on all inputs. The outputs can be
individually set and cleared via software, controlled from the internal timer resources, or
fed from other input events, e.g. acquisition triggers, etc.
EIA-644 Control
In:
Two 2 bit EIA-644 (LVDS) input ports are provided to interface with other systems.
can be used as additional acquisition trigger sources, or as inputs from shaft encoders,
etc.
TTL I/O: Two 8 bit TTL I/O ports are provided to interface with other systems. Each 8 bit port
can be independently configured as all input or all output under software control. When
used as outputs, each bit can source 24mA at min 2.2V or sink 24mA at max 0.55V.
When used as inputs, an applied voltage of between 2V and 5V is read as a logical “1”
and an applied voltage of between 0V and 0.8V as a logical “0”.
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Serial Port: Phoenix is fitted with a dual channel Universal Asynchronous Receiver Transmitter
(UART), containing 64 character hardware transmit and receive FIFOs for each channel
(the software libraries buffer both the transmit and receive data to provide larger user
FIFOs). Each channel independently supports 1, 1.5 or 2 stop bits; 5, 6, 7 or 8 data bits;
and odd, even or no parity. The baudrate can be configured with standard values from
300 baud up to 115,200 baud. Phoenix also supports software (XON, XOFF) flow
control within the UART without host CPU intervention.
Connectors: Phoenix is fitted with the 26 way 3M MDR connectors and screwlocks as specified in
the Camera Link v1.1 specification.
For opto-isolated, EIA-644 & TTL I/O there are internal 20 & 26 way 0.1” IDC headers,
with the option to bring these out to a 50 way mini D on an adjacent PCI slot.
A 10 way 0.1” IDC header (“Chain”) allows two Phoenix boards to be used together to
simultaneously acquire from wider sources.
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Phoenix User Manual SDK Overview 10
SDK Overview
The Phoenix software architecture diagram (below) shows how the various library components interact.
A
PPLICATION LAYER
H
IGH LEVEL LIBRARY LAYER
D
RIVER LAYER
P
HOENIX HARDWAR
E
L
OW LEVEL LIBRARY LAYER
S
APPLICATION SOFTWARE
PHOENIX CONTROL CLASS
LIBRARY (PCC)
PHOENIX SUPPORT
LIBRARIES (PDL, PBL, PIL)
PHOENIX IMAGE CAPTURE LIBRARY (PHX)
PHOENIX FIRMWARE LIBRARY (PFW)
PHOENIX HARDWARE DRIVER (CDA)
•The Phoenix library (PHX) provides acquisition and control features for the Phoenix image capture
boards.
•The Phoenix Firmware library (PFW) contains the firmware designs and is used by the PHX library to
allow the Phoenix board’s functionality to be upgraded with new SDK releases.
•The Phoenix Buffer library (PBL) provides method of allocating the destination memory buffers for
images acquired from the Phoenix using the PHX library.
•The Phoenix Imaging library (PIL) provides various image format conversion routines as well as Bayer
processing.
•The Phoenix Display Library (PDL) allows captured images to be displayed quickly and easily.
•The Phoenix Control Class library (PCC) provides a high level layer which allows applications requiring
user control of the Phoenix hardware to be developed quickly and easily.
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Phoenix User Manual SDK Examples 11
SDK Examples
Example application code is supplied as part of the Phoenix SDK. These examples illustrate how the
Phoenix libraries can be used in various user applications. They are listed in ascending order of complexity,
hence the user will benefit by working through them in sequence.
INITIALISING THE PHOENIX BOARD
phxinfo This example shows how to initialise the Phoenix board and display the board property
information. It shows how to programmatically determine board settings, as well as
being a useful tool to check the hardware and device driver are correctly installed.
phxconfig This example continually configures and releases the board resources. This is used
under operating systems such as VxWorks, which may require custom platform
specific initialisation code, to ensure all the low level read and write caches are
configured correctly. If all the firmware data is not correctly sent to the board, it will
fail the PHX_CameraConfigLoad call.
PCI BANDWIDTH MEASUREMENT
phxrate This example calculates the maximum sustainable data rate across the PCI bus
segment. The Phoenix hardware is configured to always transfer data across the PCI
bus, irrespective of whether there is any data available from the video source.
Additionally the hardware is configured to transfer data irrespective of whether the
software has finished processing the previous buffer. This ensures that the Phoenix
hardware transfers the maximum amount of data in the shortest possible time.
SINGLE ACQUISITION WITH FILE SAVE
phxsnap This example shows how to acquire a single image from the Phoenix board and save to
an output file in raw data format.
LIVE ACQUISITION
phxsimple This example shows how to initialise the Phoenix board and use the Phoenix library
(PHX) to run live acquisition, using a callback function.
phxlive This example shows how to initialise the Phoenix board and use the display library
(PDL) to run live double buffered (also known as ping-pong) acquisition, using a
callback function.
phxstereo This example shows how to use the Phoenix libraries to configure two independent
cameras into a single board. For simplicity the code here assumes two identical
cameras, though this is NOT a restriction of the libraries. The code does not assume or
require any synchronisation between the two channels. Once again the images are
displayed using the display library (PDL), as an example of how and where to process
the image data. This example uses an application specific structure to contain
information about each channel, and hence allow common code to be used for
initialisation, data processing, and destruction. This dual channel feature can be
regarded as having two virtual frame grabbers on a single piece of hardware.
phxcheckandwait This example shows how to initialise the Phoenix board and run continuous acquisition
using polling. If the camera is turned off or disconnected, a timeout is detected and
displayed.
phxtimeout This example shows how to initialise the Phoenix board and run continuous acquisition
using a callback function. If the camera is turned off or disconnected, a timeout is
detected and displayed.
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6
Table of contents
