Advantech Qseven SOM-3567 User manual

０
SOM-3567
R101 2018’05’03

０
Contents
1. Introduction.................................................................................................４
1.1 About This Document...............................................................................４
1.2 Signal Table Terminology.........................................................................４
1.3 Terminology..............................................................................................４
1.4 Reference Documents..............................................................................７
1.5 Revision History .......................................................................................８
1.6 SOM-3567 Block Diagram........................................................................９
2. Qseven Interfaces ......................................................................................１０
2.1 Qseven Connector Layout........................................................................１０
2.2 Qseven 2.1 Connector Pin-out.................................................................１２
2.3 PCI Express .............................................................................................１７
2.3.1 COM Express A-B Connector and C-D Connector PCIe Groups.......................１７
2.3.2 General Purpose PCIe Signal Definitions..........................................................１７
2.3.3 PCI Express* Trace Length Guidelines .............................................................２２
2.4 LAN Interface ...........................................................................................２４
2.4.1 LAN Signal Definitions ......................................................................................２４
2.4.2 LAN Implementation Guidelines ........................................................................２６
2.4.3 LAN Magnetics Modules ...................................................................................２７
2.4.4 LAN Component Placement..............................................................................２７
2.4.5 LAN Ground Plane Separation..........................................................................２７
2.4.6 LAN Link Activity and Speed LED .....................................................................２８
2.4.7 LAN Trace Length Guidelines ...........................................................................２９
2.4.8 Reference Ground Isolation and Coupling.........................................................３０
2.5 SATA ........................................................................................................３１
2.5.1 SATA Signal Definitions ....................................................................................３１
2.5.2 SATA Routing Guidelines..................................................................................３３
2.5.2.1 General SATA Routing Guidelines.........................................................３３
2.5.3 SATA Trace Length Guidelines .........................................................................３４
2.6 USB2.0 Ports............................................................................................３５
2.6.1 USB2.0 Signal Definitions .................................................................................３６
2.6.1.1 USB Over-Current Protection (USB_x_y_OC#) ......................................３９

１
2.6.1.2 Powering USB devices during S5...........................................................３９
2.6.2 USB2.0 Routing Guidelines...............................................................................４０
2.6.2.1 USB 2.0 General Design Considerations and Optimization....................４０
2.6.2.2 USB 2.0 Port Power Delivery .................................................................４０
2.6.2.3 USB 2.0 Common Mode Chokes ...........................................................４１
2.6.2.4 EMI / ESD Protection .............................................................................４２
2.6.2.5 USB Client Considerations.....................................................................４３
2.6.3 USB2.0 Trace Length Guidelines ......................................................................４４
2.7 USB3.0 .....................................................................................................４６
2.7.1 USB3.0 Signal Definitions .................................................................................４６
2.7.1.1 USB Over-Current Protection (USB_x_y_OC#) ......................................４８
2.7.1.2 EMI / ESD Protection .............................................................................４９
2.7.2 USB3.0 Trace Length Guidelines ......................................................................４９
2.8 SDIO Interface..........................................................................................５０
2.8.1 SDIO Signal Definitions.....................................................................................５０
2.8.2 SDIO Interface Routing Guidelines....................................................................５３
2.9 High Definition Audio / AC97 / I?S Audio Signals ....................................５４
2.9.1 Audio Codec Signal Descriptions ......................................................................５４
2.9.2 Audio Routing Guidelines..................................................................................５５
2.9.3 Audio Trace Length Guidelines .........................................................................５６
2.10 LVDS ......................................................................................................５７
2.10.1 Signal Definitions ............................................................................................５７
2.10.1.1 Display Timing Configuration ...............................................................６１
2.10.1.2 Backlight Control..................................................................................６２
2.10.2 LVDS Routing Guidelines................................................................................６２
2.10.3 LVDS Trace Length Guidelines .......................................................................６３
2.11 Embedded DisplayPort (eDP) *SOM-3567 is not support......................６４
2.11.1 eDP Signal Definitions.....................................................................................６４
2.11.2 eDP Implementation Guidelines ......................................................................６６
2.11.3 eDP Trace Length Guidelines .........................................................................６６
2.12 DisplayPort Interfaces ............................................................................６７
2.12.1 DisplayPort Interface Signals (from Module) ...................................................６７
2.12.2 DisplayPort Interfaces Routing Guidelines ......................................................７０
2.12.2.1 DisplayPort Routing Guidelines............................................................７０
2.12.2.2 HDMI / DVI Routing Guidelines............................................................７３

２
2.12.3 HDMI / DVI Level Shifter Requirements ..........................................................７４
2.12.4 ESD Protection................................................................................................７５
2.13 LPC Bus –Low Pin Count Interface.......................................................７６
2.13.1 LPC Signal Definition ......................................................................................７７
2.13.2 LPC Routing Guidelines ..................................................................................７８
2.13.2.1 General Signals ...................................................................................７８
2.13.2.2 Bus Clock Routing ...............................................................................７８
2.13.3 LPC Trace Length Guidelines .........................................................................７８
2.14. CAN Interface *SOM-3567 is not support CAN Interface......................８０
2.14.1 CAN interface Signal Definitions .....................................................................８０
2.14.2 CAN interface Routing Guidelines...................................................................８０
2.14.3 CAN interface Trace Length Guidelines ..........................................................８１
2.15 SPI –Serial Peripheral Interface Bus.....................................................８２
2.15.1 SPI Signal Definition .......................................................................................８２
2.15.2 SPI Routing Guidelines ...................................................................................８３
2.15.3 SPI Trace Length Guidelines...........................................................................８３
2.16 General Purpose I2C Bus Interface .......................................................８４
2.16.1 Signal Definitions ............................................................................................８５
2.16.2 I2C Routing Guidelines ...................................................................................８６
2.16.3 I2C Trace Length Guidelines...........................................................................８６
2.16.4 Connectivity Considerations............................................................................８６
2.17 System Management Bus (SMBus) .......................................................８７
2.17.1 SMB Signal Definitions....................................................................................８８
2.17.2 SMB Routing Guidelines .................................................................................８８
2.17.3 SMB Trace Length Guidelines.........................................................................８９
2.18 UART......................................................................................................９０
2.18.1 UART interface Signal Definitions ...................................................................９０
2.18.2 Serial interface Routing Guidelines .................................................................９０
2.18.3 Serial interface Trace Length Guidelines.........................................................９０
2.19 Miscellaneous Signals............................................................................９１
2.19.1 Miscellaneous Signals.....................................................................................９１
2.19.1.1 Watchdog Control Signals....................................................................９２
2.19.1.2 PC Speaker Output..............................................................................９３
2.19.2 Miscellaneous Signals Routing Guidelines......................................................９３
2.19.3 Miscellaneous Signals Trace Length Guidelines .............................................９３

３
2.20 Thermal Signals .....................................................................................９３
2.20.1 Thermal Interface............................................................................................９３
2.20.2 Thermal Signals Routing Guidelines ...............................................................９４
2.20.3 Thermal Signals Trace Length Guidelines.......................................................９４
2.21 Fan Control Implementation ...................................................................９４
2.21.1 Fan Control Interface ......................................................................................９４
2.21.2 Fan Control Signals Routing Guidelines..........................................................９５
2.21.3 Fan Control Signals Trace Length Guidelines .................................................９５
3. Power .........................................................................................................９６
3.1 General Power requirements ...................................................................９６
3.1.1 Power Management Signals .............................................................................９７
3.2 Power Up Control .....................................................................................９９
3.2.1 ATX and AT Power Sequencing Diagrams........................................................１００
3.3 RTC Battery..............................................................................................１０３
3.3.1 RTC Battery Lifetime.........................................................................................１０３
4. Electrical Characteristics ............................................................................１０４
4.1. Absolute Maximum Ratings.....................................................................１０４
4.2. DC Characteristics ..................................................................................１０４
4.3. Inrush Current .........................................................................................１０４

４
1. Introduction
1.1 About This Document
This document provides information for designing a custom system carrier board for
Qseven
®
modules. It includes Signal Descriptions, Routing Guidelines and Trace Length
Guidelines. The main purpose is designing Carrier Board for helping customers fast and
easy using the module of Advantech to be designed.
1.2 Signal Table Terminology
Table 1 below describes the terminology used in this section for the Signal Description
tables.
The “#”symbol at the end of the signal name indicates that the active or asserted state
occurs when the signal is at a low voltage level. When “#”is not present, the signal is
asserted when at a high voltage level.
The terms “Input”and “Output”and their abbreviations in Table 1 below refer to the
Module's view, i.e. an input is an input for the Module and not for the Carrier-Board.
1.3 Terminology
Table 1: Conventions and Terminology
Terminology
Description
X86
The term x86 refers to a family of instruction set architectures
based on the Intel 8086.
PCI Express (PCIe)
Peripheral Component Interface Express. Next-generation high
speed serialized I/O bus
PCI Express Lane
One PCI Express Lane is a set of 4 signals that contains two
differential lines for Transmitter and two differential lines for

５
Receiver. Clocking information is embedded into the data
stream.
x1, x2, x4
x1 refers to one PCI Express Lane of basic bandwidth; x2 to a
collection of two PCI Express Lanes; etc.. Also referred to as x1,
x2, x4 link.
DDC
Display Data Channel is an I2C bus interface between a display
and a graphics adapter.
DVI
Digital Visual Interface is a video interface standard developed
by the Digital Display Working Group (DDWG).
GBE
Gigabit Ethernet
USB
Universal Serial Bus
SATA
Serial AT Attachment: serial interface standard for hard disks.
HDA
High Definition Audio
I2S
Integrated Interchip Sound (I2S) is an electrical serial bus
interface standard used for connecting digital audio devices
together.
HDMI
High Definition Multimedia Interface. HDMI supports standard,
enhanced, or
high-definition video, plus multi-channel digital audio on a single
cable.
TMDS
Transition Minimized Differential Signaling. TMDS is a signaling
interface defined by Silicon
Image that is used for DVI and HDMI.
DP
eDP
(embedded) DisplayPort (DP/eDP) is a digital display interface
developed by the Video Electronics Standards Association
(VESA).
LPC
Low Pin-Count Interface: a low speed interface used for
peripheral circuits such as Super I/O controllers, which typically
combine legacy-device support into a single IC.
CAN
Controller Area Network
SPI
Serial Peripheral Interface
SDIO
Secure Digital Input Output
SMB
System Management Bus
LVDS
Low-Voltage Differential Signaling
ACPI
Advanced Control Programmable Interface
RoHS
Restriction on Hazardous Substances: The Directive on the
Restriction of the Use of Certain Hazardous Substances in

６
Electrical and Electronic Equipment 2002/95/EC.
N.C.
Not connected
N.A.
Not available
T.B.D.
To be determined
EDID
Extended Display Identification Data
EDP
Embedded DisplayPort (eDP) is a digital display interface
standard produced by the Video Electronics Standards
Association (VESA) for digital interconnect of Audio and Video.
EEPROM
Electrically Erasable Programmable Read-Only Memory
EFT
Electrical Fast Transient
EMI
Electromagnetic Interference
ESD
Electrostatic Discharge
ExpressCard
A PCMCIA standard built on the latest USB 2.0 and PCI
Express buses.
FR4
A type of fiber-glass laminate commonly used for printed circuit
boards.
GPI
General Purpose Input
GPIO
General Purpose Input Output
GPO
General Purpose Output
DE
Integrated Device Electronics –parallel interface for hard disk
drives –also known as PATA
Legacy Device
Relics from the PC-AT computer that are not in use in
contemporary PC systems: primarily the ISA bus, UART-based
serial ports, parallel printer ports, PS-2 keyboards, and mice.
Definitions vary as to what constitutes a legacy device. Some
definitions include IDE as a legacy device.
LS
Least Significant
PCB
Printed Circuit Board
PD
Pull Down
PP
Push Pull
I
Input Pin
O
Output Pin
OD
Open Drain
P
Power Pin
PHY
Ethernet controller physical layer device
PEG
PCI Express Graphics
PS2
“Personal System 2”- an IBM trademark term used to refer to

７
PS2 Keyboard
PS2 Mouse
Intel x86 based personal computers in the 1990s. The term
survives as a reference to the style of mouse and keyboard
interface that were introduced with the PS2 system.
RTC
Real Time Clock –battery backed circuit in PC-AT systems
that keeps system time and dateas well as certain system setup
parameters
S0, S1, S2, S3, S4,
S5
Sleep States defined by the ACPI specificationS0 Full power, all
devices powered
S1Sleep State, all context maintained
S2 Sleep State, CPU and Cache context lost
S3 Suspend to RAM System context stored in RAM; RAM is in
standby
S4 Suspend to Disk System context stored on disk
S5 Soft Off Main power rail off, only standby power rail present
TMDS
Transition Minimized Differential Signaling - a digital signaling
protocol between the graphics subsystem and display. TMDS is
used for the DVI digital signals. DC coupled
TPM
Trusted Platform Module, chip to enhance the security features
of a computer system.
VESA
Video Electronics Standards Association
WDT
Watch Dog Timer
1.4 Reference Documents
Document
Qseven Design Guide Rev. 2.0
Qseven Specification 2.0 and Qseven Specification 2.1
Intel EDS Document
Intel Layout Guide Document
ATX12V Power Supply Design Guide Rev. 2.01

８
1.5 Revision History
Revision
Date
PCB
Rev.
Changes
1.00
Oct 14, 2015
A101-2
SOM-3567 design for Q7 R2.0
1.10
May 03, 2018
A101-2
Update Table 18 LVDS impedance to 85

９
1.6 SOM-3567 Block Diagram
PCIe Port 3 (optional)
SPI
SPI BIOS
UART(Optional)
Q7 Gold Finger
DDR3L Channel 2
1066 /1333 MHz up to 4GB
eMMC 4.51
Up to 32GB
Intel Atom/ Celeron
DDR3L Channel 1
1066 /1333 MHz up to 4GB
SATA Port 0, 1
HDA
DDI0
eDP to LVDS
NXP3460 LVDSDDI1
USB 2.0 Port 0~2
USB 3.0 Port 0
USB Hub
SMSC2514B USB 2.0 Port 3~5
USB 2.0
Port 3
SoC
(Optional ports while remove Ethernet)
FPC Conn. 36P
PCIe Port 0~2
Ethernet
Giga LAN
WDT/ I2C/ FAN/ UART
Embedded
Controller
LPC BUS
SMBus
SD 3.0

１０
2. Qseven Interfaces
2.1 Qseven Connector Layout
Figure 1: Qseven Connector Layout

１１

１２
2.2 Qseven 2.1 Connector Pin-out
Table 2: Qseven 2.1 Pin-out
Connector
Pin
Signal
Pin
Signal
1
GND
2
GND
3
GBE_MDI3-
4
GBE_MDI2-
5
GBE_MDI3+
6
GBE_MDI2+
7
GBE_LINK100#
8
GBE_LINK1000#
9
GBE_MDI1-
10
GBE_MDI0-
11
GBE_MDI1+
12
GBE_MDI0+
13
GBE_LINK#
14
GBE_ACT#
15
GBE_CTREF
16
SUS_S5#
17
WAKE#
18
SUS_S3#
19
GPO0
20
PWRBTN#

１３
21
SLP_BTN# / GPII1
22
LID_BTN# / GPII0
23
GND
24
GND
KEY
KEY
25
GND
26
PWGIN
27
BATLOW# / GPII2
28
RSTBTN#
29
SATA0_TX+
30
SATA1_TX+
31
SATA0_TX-
32
SATA1_TX-
33
SATA_ACT#
34
GND
35
SATA0_RX+
36
SATA1_RX+
37
SATA0_RX-
38
SATA1_RX-
39
GND
40
GND
41
BIOS_DISABLE# /
BOOT_ALT#
42
SDIO_CLK#
43
SDIO_CD#
44
reserved
45
SDIO_CMD
46
SDIO_WP
47
SDIO_PWR#
48
SDIO_DAT1
49
SDIO_DAT0
50
SDIO_DAT3
51
SDIO_DAT2
52
reserved
53
reserved
54
reserved
55
reserved
56
USB_OTG_PEN
57
GND
58
GND
59
HDA_SYNC / I2S_WS
60
SMB_CLK / GP1_I2C_CLK
61
HDA_RST# / I2S_RST#
62
SMB_DAT / GP1_I2C_DAT
63
HDA_BITCLK / I2S_CLK
64
SMB_ALERT#
Pin
Signal
Pin
Signal
65
HDA_SDI / I2S_SDI
66
GP0_I2C_CLK
67
HDA_SDO / I2S_SDO
68
GP0_I2C_DAT
69
THRM#
70
WDTRIG#
71
THRMTRIP#
72
WDOUT
73
GND
74
GND
75
USB_P7- / USB_SSTX0-
76
USB_P6- / USB_SSRX0-
77
USB_P7+ / USB_SSTX0+
78
USB_P6+ / USB_SSRX0+
79
USB_6_7_OC#
80
USB_4_5_OC#
81
USB_P5- / USB_SSTX2-
82
USB_P4- / USB_SSRX2-
83
USB_P5+ / USB_SSTX2+
84
USB_P4+ / USB_SSRX2+

１４
85
USB_2_3_OC#
86
USB_0_1_OC#
87
USB_P3-
88
USB_P2-
89
USB_P3+
90
USB_P2+
91
USB_VBUS
92
USB_ID
93
USB_P1-
94
USB_P0-
95
USB_P1+
96
USB_P0+
97
GND
98
GND
99
eDP0_TX0+ / LVDS_A0+
100
eDP1_TX0+ / LVDS_B0+
101
eDP0_TX0- / LVDS_A0-
102
eDP1_TX0- / LVDS_B0-
103
eDP0_TX1+ / LVDS_A1+
104
eDP1_TX1+ / LVDS_B1+
105
eDP0_TX1- / LVDS_A1-
106
eDP1_TX1- / LVDS_B1-
107
eDP0_TX2+ / LVDS_A2+
108
eDP1_TX2+ / LVDS_B2+
109
eDP0_TX2- / LVDS_A2-
110
eDP1_TX2- / LVDS_B2-
111
LVDS_PPEN
112
LVDS_BLEN
113
eDP0_TX3+ / LVDS_A3+
114
eDP1_TX3+ / LVDS_B3+
115
eDP0_TX3- / LVDS_A3-
116
eDP1_TX3- /
LVDS_B3-
117
GND
118
GND
119
eDP0_AUX+ / LVDS_A_CLK+
120
eDP1_AUX+ / LVDS_B_CLK+
121
eDP0_AUX- / LVDS_A_CLK-
122
eDP1_AUX- / LVDS_B_CLK-
123
LVDS_BLT_CTRL /
P_PWM_OUT0
124
GP_1-Wire_Bus / HDMI_CEC
125
GP2_I2C_DAT /
LVDS_DID_DAT
126
eDP0_HPD# /
LVDS_BLC_DAT
127
GP2_I2C_CLK /
LVDS_DID_CLK
128
eDP1_HPD# /
LVDS_BLC_CLK
129
CAN0_TX
130
CAN0_RX
131
DP_LANE3+ / TMDS_CLK+
132
USB_SSTX1-
133
DP_LANE3- / TMDS_CLK-
134
USB_SSTX1+
135
GND
136
GND
Pin
Signal
Pin
Signal
137
DP_LANE1+ / TMDS_LANE1+
138
DP_AUX+
139
DP_LANE1- / TMDS_LANE1-
140
DP_AUX-
141
GND
142
GND
143
DP_LANE2+ / TMDS_LANE0+
144
USB_SSRX1-

１５
145
DP_LANE2- / TMDS_LANE0-
146
USB_SSRX1+
147
GND
148
GND
149
DP_LANE0+ / TMDS_LANE2+
150
HDMI_CTRL_DAT
151
DP_LANE0- / TMDS_LANE2-
152
HDMI_CTRL_CLK
153
HDMI_HPD#
154
DP_HPD#
155
PCIE_CLK_REF+
156
PCIE_WAKE#
157
PCIE_CLK_REF-
158
PCIE_RST#
159
GND
160
GND
161
PCIE3_TX+
162
PCIE3_RX+
163
PCIE3_TX-
164
PCIE3_RX-
165
GND
166
GND
167
PCIE2_TX+
168
PCIE2_RX+
169
PCIE2_TX-
170
PCIE2_RX-
171
UART0_TX
172
UART0_RTS#
173
PCIE1_TX+
174
PCIE1_RX+
175
PCIE1_TX-
176
PCIE1_RX-
177
UART0_RX
178
UART0_CTS#
179
PCIE0_TX+
180
PCIE0_RX+
181
PCIE0_TX-
182
PCIE0_RX-
183
GND
184
GND
185
LPC_AD0 / GPIO0
186
LPC_AD1 / GPIO1
187
LPC_AD2 / GPIO2
188
LPC_AD3 / GPIO3
189
LPC_CLK / GPIO4
190
LPC_FRAME# / GPIO5
191
SERIRQ / GPIO6
192
LPC_LDRQ# / GPIO7
193
VCC_RTC (3.3V)
194
SPKR / GP_PWM_OUT2
195
FAN_TACHOIN /
GP_TIMER_IN
196
FAN_PWMOUT /
GP_PWM_OUT1
197
GND
198
GND
199
SPI_MOSI
200
SPI_CS0#
201
SPI_MISO
202
SPI_CS1#
203
SPI_SCK
204
MFG_NC4
205
VCC_5V_SB (5V)
206
VCC_5V_SB (5V)
Pin
Signal
Pin
Signal
207
MFG_NC0
208
MFG_NC2
209
MFG_NC1
210
MFG_NC3

１６
211
NC* / VCC (5V)
212
NC* / VCC (5V)
213
NC* / VCC (5V)
214
NC* / VCC (5V)
215
NC* / VCC (5V)
216
NC* / VCC (5V)
217
NC* / VCC (5V)
218
NC* / VCC (5V)
219
VCC (5V)
220
VCC (5V)
221
VCC (5V)
222
VCC (5V)
223
VCC (5V)
224
VCC (5V)
225
VCC (5V)
226
VCC (5V)
227
VCC (5V)
228
VCC (5V)
229
VCC (5V)
230
VCC (5V)
Notes:
1. Q7 R2.0 and Q7 R2.1 difference table
Pin
R2.0
Connector Pinout
R2.1
Connector
Pinout
Pin
R2.0
Connector Pinout
R2.1
Connector
Pinout
19
SUS_STAT#
GPO0
22
LID_BTN#
LID_BTN# /
GPII0
21
SLP_BTN#
SLP_BTN# /
GPII1
44
SDIO_LED
reserved
27
BATLOW#
BATLOW# /
GPII2
52
SDIO_DAT5
reserved
53
SDIO_DAT4
reserved
54
SDIO_DAT7
reserved
55
SDIO_DAT6
reserved
56
USB_DRIVE_VBUS
USB_OTG_PEN
81
USB_P5- /
USB_SSTX1-
USB_P5- /
USB_SSTX2-
82
USB_P4- /
USB_SSRX1-
USB_P4- /
USB_SSRX2-
83
USB_P5+ /
USB_SSTX1+
USB_P5+ /
USB_SSTX2+
84
USB_P4+ /
USB_SSRX1+
USB_P4+ /
USB_SSRX2+
153
DP_HDMI_HPD#
HDMI_HPD#
124
GP_1-Wire_Bus
GP_1-Wire_Bus
/ HDMI_CEC
211
VCC
NC
132
RSVD
USB_SSTX1-
213
VCC
NC
134
RSVD
USB_SSTX1+
215
VCC
NC
144
RSVD
USB_SSRX1-
217
VCC
NC
146
RSVD
USB_SSRX1+
212
VCC
NC
214
VCC
NC
216
VCC
NC
218
VCC
NC

１７
2.3 PCI Express
2.3.1 COM Express A-B Connector and C-D Connector PCIe Groups
PCI Express provides a scalable, high-speed, serial I/O point-to-point bus connection. A
PCI Express lane consists of dual simplex channels, each implemented as a low-voltage
differentially driven transmit pair and receive pair. They are used for simultaneous
transmission in each direction. The bandwidth of a PCI Express link can be scaled by
adding signal pairs to form multiple lanes between two devices. The Qseven modules can
optionally provide configurations with x1 and x4 link widths. Each single lane has a raw
data transfer rate of 2.5Gbps @ 1.25GHz.
The PCI Express interface of the Qseven module consists of a minimum of 0 [ARM] resp.
1 [x86] and up to 4 lanes, each with a receive and transmit differential signal pair
designated from PCIE0_RX (+ and -) to PCIE3_RX (+ and -) and correspondingly from
PCIE0_TX (+ and -) to PCIE3_TX (+ and -). According to the PCI Express specification,
these four lanes can be configured as several PCI Express x1 links or to a combined x4
link. These configuration possibilities are based on the Qseven module's chipset
capabilities. Refer to the vendor specific Qseven module documentation for the module
that you are using for additional information about this subject.
2.3.2 General Purpose PCIe Signal Definitions
Table 3: General Purpose PCI Express Signal Descriptions
Signal
Pin#
Description
I/O
Note
PCIE0_RX+
PCIE0_RX-
180
182
PCIe channel 0. Receive Input differential
pair.
Carrier Board:
Device - Connect AC Coupling cap 0.1uF
near Qseven to PCIE0 x1 device PETp0.
Slot - Connect to PCIE0 x1 Conn pin A16,
A17 PERp0.
N/C if not used.
I PCIE
PCIE0_TX+
PCIE0_TX-
179
181
PCIe channel 0. Transmit Output
differential pair.
Module has integrated AC Coupling
Capacitor.
Carrier Board:
Device - Connect to PCIE0 x1 device
PERp0.
O PCIE

１８
Slot - Connect to PCIE0 x1 Conn pin B14,
B15 PETp0.
N/C if not used
Signal
Pin#
Description
I/O
Note
PCIE1_RX+
PCIE1_RX-
174
176
PCIe channel 1. Receive Input differential
pair.
Carrier Board:
Device - Connect AC Coupling cap 0.1uF
near to PCIE1 x1 device PETp/n0.
Slot - Connect to PCIE1 x1 Conn pin A16,
A17 PERp/n0.
N/C if not used.
I PCIE
PCIE1_TX+
PCIE1_TX-
173
175
PCIe channel 1. Transmit Output
differential pair.
Module has integrated AC Coupling
Capacitor.
Carrier Board:
Device - Connect to PCIE1 x1 device
PERp/n0.
Slot - Connect to PCIE1 x1 Conn pin B14,
B15 PETp/n0.
N/C if not used.
O PCIE
PCIE2_RX+
PCIE2_RX-
168
170
PCIe channel 2. Receive Input differential
pair.
Carrier Board:
Device - Connect AC Coupling cap 0.1uF
near COME to PCIE2 x1 device PETp/n0.
Slot - Connect to PCIE2 x1 Conn pin A16,
A17 PERp/n0.
N/C if not used.
I PCIE
PCIE2_TX+
167
PCIe channel 2. Transmit Output
O PCIE