Aeroflex UT8MR8M8-EVB User manual

1
Standard Products
UT8MR8M8-EVB 64Megabit Non-
Volatile MRAM Evaluation Board
User Manual
July 2012
www.aeroflex.com/memories
1.0 INTRODUCTION
The Aeroflex 64Megabit Non-Volatile magnetoresistive random access memory (MRAM) is a high-
performance memory multichip module (MCM) compatible with traditional asynchronous SRAM
operations, organized as four individual 16,777,216 words by 8 bits. The MRAM is equipped with five
chip enables (/En), a single write enable (/W), and a single output enable (/G) pin, allowing for significant
system design flexibility without bus contention. Data is non-volatile for > 15 years at temperature and
data is automatically protected against power loss by a low voltage write inhibit.
The UT8MR8M8-EVB allows the user access to most all the features of the 64Mb MRAM via bench top
evaluation or using the UT699 LEON-3FT evaluation board.
2.0 SCOPE
This document describes the features and necessary steps to set-up and operate the Aeroflex Colorado Springs
64Megabit Non-Volatile MRAM Evaluation Board. Users must be familiar with the UT699 LEON-3FT Processor
and the 64Megabit Non-Volatile MRAM datasheets.
3.0 REFERENCE DOCUMENTS
Aeroflex Colorado Springs, “UT8MR8M8 64Megabit Non-Volatile MRAM” Datasheet,
www.aeroflex.com/memories
Aeroflex Gaisler “GR-CPCI-UT699 LEON3-FT CPCI Development Board” User Manual,
www.aeroflex.com/LEON
Aeroflex Colorado Springs, “UT699 32-bit Fault Tolerant SPARCTM V8/LEON3FT Processor” Datasheet,
www.aeroflex.com/LEON

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4.0 FUNCTIONAL DIAGRAM
UT8MR8M8
64M Non-Volatile MRAM
(64-Lead FP MCM)
Figure 1. Notional UT8MR8M8-EVB block diagram

3
5.0 FEATURES AND GENERAL OPERATION
The Aeroflex 64Megabit Non-Volatile MRAM Evaluation Board provides the user with a flexible means to
configure, control, access, and read/write data to the UT8MR8M8 device. Power to the board may be provided
through the J9 connector on the GR-UT699 CPCI Development Board or through the 100 mil connector J8 on the
UT8MR8M8-EVB. Only one power source should be used at a time.
5.1 Power
5.1.1 External Power
Power to the UT8MR8M8-EVB may be provided externally using 3.3V if using in a bench top only
configuration.
Figure 2. External Power Jumper Configuration Settings

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5.1.2 Aeroflex Gaisler Board Power
Power to the UT8MR8M8-EVB is also provided from the J9 connector on the GR-CPCI-UT699 LEON3-
FT CPCI Development Board. J7, the 120 pin connector, is located on the back side of the EVB.
Use caution when mating the 64Megabit Non-Volatile MRAM Evaluation Board to the LEON-3FT
evaluation board. Ensure that the mating connectors are lined up and that the power is removed from the
GR-cPCI-UT699 eval board prior to plugging in the MRAM evaluation board.
Table 1. LEON-3FT-EVB Power Pins (J9) Table 2. LEON-3FT-EVB Ground pins (J9)
LEON-3FT connector LEON-3FT connector
Pin Signal Pin Signal
10 3.3V 1 VSS
20 3.3V 3 VSS
30 3.3V 5 VSS
40 3.3V 7 VSS
51 3.3V 11 VSS
71 3.3V 21 VSS
81 3.3V 31 VSS
91 3.3V 41 VSS
101 3.3V 50 VSS
111 3.3V 60 VSS
61 VSS
70 VSS
80 VSS
90 VSS
100 VSS
110 VSS
114 VSS
116 VSS
118 VSS
120 VSS

5
Figure 3. Aeroflex Gaisler LEON-3FT J7 to J9 connector

6
5.2 Address Inputs
Table 3. Address Inputs J7 pin out
LEON-3FT connector
(J9) UT8MR8M8 Device (J7)
Pin Signal Pin Signal
45 A0 10 A0
76 A1 9 A1
44 A2 8 A2
77 A3 7 A3
43 A4 6 A4
78 A5 28 A5
42 A6 27 A6
79 A7 26 A7
39 A8 25 A8
82 A9 24 A9
38 A10 41 A10
83 A11 40 A11
37 A12 39 A12
84 A13 38 A13
36 A14 37 A14
85 A15 58 A15
35 A16 57 A16
86 A17 56 A17
34 A18 55 A18
87 A19 11 A19
33 A20 59 A20
88 A21 22 A21
32 A22 23 A22

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5.3 Data I/O
The UT8MR8M8 has eight bidirectional data lines, DQ[7:0]. The data inputs/outputs are connected to J7
as shown in table 4.
Table 4. Data I/O J7 pin out
LEON-3FT connector
(J9) UT8MR8M8 Device (J7)
Pin Signal Pin Signal
95 D24 46 DATA0
97 D25 47 DATA1
99 D26 50 DATA2
103 D27 51 DATA3
105 D28 14 DATA4
107 D29 15 DATA5
109 D30 18 DATA6
113 D31 19 DATA7

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5.4 Chip Enable
Asserting /E_All allows the device to be addressed as a single, 64Mb memory using address bits A21 and
A22 to decode and select 1 of 4 MRAM die.
Table 5. Enable Signals LEON-3FT (J5)
LEON-3FT connector
(J9) UT8MR8M8 Device (J7)
Pin Signal Pin Signal
48 ROMSN0 21 Can be jumpered to /E_ALL for LEON-3FT to control the
UT8MR8M8
74 IOSN 21 Can be jumpered to /E_ALL
The user can exercise either the IOSN or ROMSN0 pin on the LEON-3FT to exercise the /E_All pin on the
MRAM. There is a three pin header, J5, that allows the user to select IOSN or ROMSN0 to control the
/E_All pin.
Figure 6. /E_All header control
5.4.1 Use as an External Memory with LEON
Set J5 to ROMSN0 on the UT8MR8M8-EVB and uninstall JP6 on the UT699-EVB.
5.4.2 Use as IO Space
Set J5 to IOSN option on the UT8MR8M8-EVB and install JP6 on the UT699-EVB.
5.5 Write Enable (/W)

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/W controls read and write operation. During a read cycle, /G must be asserted to enable the outputs.
Table 6. Write Enable LEON-3FT J7 to J9 connector
LEON-3FT connector
(J9) UT8MR8M8 Device (J7)
Pin Signal Pin Signal
46 WEB 42 /W
5.6 Output Enable (/G)
/W controls read and write operation. During a read cycle, /G must be asserted to enable the outputs.
Table 7. Output Enable LEON-3FT J7 to J9 connector
LEON-3FT connector
(J9) UT8MR8M8 Device (J7)
Pin Signal Pin Signal
47 OEB 53 /G
5.7 Deep Sleep Power Down (ZZ)
ZZ controls the sleep mode operation. Enabling sleep mode causes all other inputs to be do not cares. ZZ
places all die into internal low power even while system power is still applied to VDD. Pin 12 on the
UT8MR8M8 are routed to a three pin header J2. The center pin on the three pin J2 header is tied to the ZZ
pin, the other pins are tied to VDD and VSS. Please refer to the UT8MR8M8 datasheet for further
information.
Deep PowerDown
UT8MR8M8
Figure 7. ZZ pin
5.8 Multi-Bit Error Flag (MBE)

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The open drain MBE pin drives low when ECC logic detects two bit errors during the current read cycle. It
allows for wired-or of multiple MBE signals when using multiple MRAMs. The MBE signal is routed to
the one pin J6 header. This pin can be monitored if the user chooses to do so.
UT8MR8M8
MBE
Figure 8. MBE pin
6.0 Quick Start Guide
The following steps describe how the user to get the UT8MR8M8-EVB up and running with the
UT699 LEON-3FT EVB.
1. Connect J5to the UT8MR8M8-EVB to ROMSN0 for using MRAM as PROM
- or -
Connect J5to the UT8MR8M8-EVB to IOSN for using MRAM as IO Space
2. Disconnect power to the UT699-EVB
3. Plug the UT8MR8M8-EVB J7 to J9 on the UT699-EVB
4. Configure DIP switches S3 and S4 as shown in Table 9 and 10.
5. Reference Section 3 “SETTING UP AND USING THE BOARD” in the user’s manual for
the GR-UT699 board. Install the jumpers as indicated in Table 11.

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Table 8. Quick Start LEON-3FT S3 8-bit mode Configuration
DIP Switch S3
Switch Function Value Comment
1 PIO0 0 8-bit Mode (Closed)
2 PIO1 0 8-bit Mode (Closed)
3 PIO2 0 PROM EDAC disabled (Closed)
4 PIO3 1 (Open)
5 PIO4 1 (Open)
6 PIO5 1 (Open)
7 PIO6 1 (Open)
8 PIO7 1 (Open)
Table 9. Quick Start LEON-3FT S4 Configuration
DIP Switch S4
Switch Function Value Comment
1 PIO8 1 (Open)
2 PIO9 1
(Open)
3 PIO10 1
(Open)
4 PIO11 1
(Open)
5 PIO12 1
(Open)
6 PIO13 1
(Open)
7 PIO14 1
(Open)
8 PIO15 1
(Open)

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Table 10. Quick Start LEON-3FT Jumper settings for ROMSN0 or IOSN
Jumper Jumper Setting Comment
JP1 1-2: Do Not Install
3-4: Do Not Install
5-6: Do Not Install
7-8: Do Not Install
ASIC TEST mode pin not enabled DSU is enabled JTAG
interface is enabled.
Watchdog output can cause board rese
t
JP2 Do Not Install Ethernet MDIO interface interrupt is not connected to GPIO4
JP3 1-3: Install End-stub termination enabled – see sect ion 2.4. 1
JP4 1-3: Install End-stub termination enabled – see sect ion 2.4. 1
JP5 1-2: Install
3-4: Install
5-6: Install
7-8: Install Connects RAMSN0 and RAMSN1 to on board SRAM banks
JP6 Do Not Install
1-2: Install
Connects ROMSN0 to on board MRAM on UT8MR8M8-EVB
Connects IOSN to on board MRAM on UT8MR8M8-EVB
JP7 1-2: Install
3-4: Install PCI Host Mode clocks to backplane – see section 2.11
JP8
1-2: Install
3-4: Install
5-6: Install
7-8: Install
9-10: Install
11-12: Install
13-14: Install
15-16: Install
17-18: Install
19-20: Install
PCI Host Mode- Pull ups enabled – see section 2.11
JP9 1-2: Install
3-4: Install PCI Host Mode – see section 2.11
JP10 1-2: Install
3-4: Install PCI Host Mode – see section 2.11
JP11 Inst all Connects to Fron
t
Panel LED indicators
JP12 1-2: Install See section 2.9
JP13 1-2: Install See section 2.9
JP14 Inst all Can be used as current measure point f or Vcore supply to ASI C
JP15 Inst all Can be used as current measure point f or 3.3V supply to ASI C
JP16 Inst all Connected to Front Panel push buttons f or RESET and B RE AK
JP17 1-2: Install Main Processor Clock is also source f or SPW _CLK
JP18 1-2: Install
Board RESETN also generated
P CI_RS T N for PCI Host
6. Power on the UT699-EVB
7. Using GRMON:
a. MRAM as PROM: The following commands need to be run to set up memory
configuration register 1 to allow reading and writing the MRAM when it is
configured as the PROM for the UT699.
i. wmem 0x80000000 0x1803c811
ii. mcfg1 0x1803c811
iii. User code

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b. MRAM as I/O space: The following commands need to be run to set up memory
configuration register 1 to allow reading and writing the MRAM when it is
configured as I/O space for the UT699.
i. wmem 0x80000000 0x001BC811
ii. mcfg1 0x001BC811
iii. User code
7.0 COMPATIBILITY WITH GR-UT699 EVALUATION BOARD
The UT8MR8M8-EVB can plug directly into the J9 connector on the LEON-3FT evaluation board. J9
on the GR-UT699 evaluation board is pinned out as listed in table 12 below.
For further information on interfacing the UT8MR8M8-EVB with the GR-UT699 Evaluation board
please see the Aeroflex Gaisler GR-UT699 Development Board User Manual.
Table 11. UT8MR8M8-EVB to UT699-3FT LEON connections
LEON-3FT connector UT8MR8M8 Device
Pin Signal Pin Signal
1 VSS
2 +5V NC
3 VSS
4 -12V NC
5 VSS
6 +12V NC
7 VSS
8 D15 NC
9 D7 NC
10 3.3V
11 VSS
12 D14 NC
13 D6 NC
14 D13 NC
15 D5 NC
16 D12 NC
17 D4 NC
18 D11 NC
19 D3 NC
20 3.3V
21 VSS
22 D10 NC
23 D2 NC
24 D9 NC
25 D1 NC

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26 D8 NC
27 D0 NC
28 A26 NC
29 A14 NC
30 3.3V
31 VSS
32 A22 23 A22
33 A20 59 A20
34 A18 55 A18
35 A16 57 A16
36 A14 37 A14
37 A12 39 A12
38 A10 41 A10
39 A8 25 A8
40 3.3V
41 VSS
42 A6 27 A6
43 A4 6 A4
44 A2 8 A2
45 A0 10 A0
46 WEB 42 WEB
47 OEB 53 OEB
48 ROMSN0 ROMSN0
49 RAMSN4 NC
50 VSS
51 3.3V
52 RAMSN3 NC
53 RAMSN2 NC
54 RAMSN1 NC
55 RAMSN0 NC
56 RWEN2 NC
57 RWEN0 NC
58 BRDYN NC
59 RESETN NC
60 VSS
61 VSS
62 CLK NC
63 BEXCN NC
64 RWEN1 NC
65 RWEN3 NC
66 RAMOEN0 NC
67 RAMOEN1 NC
68 RAMOEN2 NC
69 RAMOEN3 NC
70 VSS

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71 3.3V
72 RAMOEN4 NC
73 RAMSN1 NC
74 IOSN
75 READ NC
76 A1 9 A1
77 A3 7 A3
78 A5 28 A5
79 A7 26 A7
80 VSS
81 3.3V
82 A9 24 A9
83 A11 40 A11
84 A13 38 A13
85 A15 58 A15
86 A17 56 A17
87 A19 11 A19
88 A21 22 A21
89 A23 NC
90 VSS
91 3.3V
92 A25 NC
93 A27 NC
94 D16 NC
95 D24 46 DATA0
96 D17 NC
97 D25 47 DATA1
98 D18 NC
99 D26 50 DATA2
100 VSS
101 3.3V
102 D19 NC
103 D27 51 DATA3
104 D20 NC
105 D28 14 DATA4
106 D21 NC
107 D29 15 DATA5
108 D22 NC
109 D30 18 DATA6
110 VSS
111 3.3V
112 D23 NC
113 D31 19 DATA7
114 VSS
115 +12V NC

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116 VSS
117 -12V NC
118 VSS
119 +5V NC
120 VSS

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8.0 BOARD SCHEMATICS
The schematics are for reference ONLY.

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Change Block
Larsen
Silkscreen UT8MR8M8(P)
1 MQ11
Silkscreen
TO LEON-3FT UT699 EVAL board
Silkscreen
3.3V POWER
Silkscreen
GND
Silkscreen MBE
Silkscreen
ZZ SLEEPY
Silkscreen
VSS
Silkscreen
VDD
Silkscreen
IOSN
ROMSN0
Silkscreen
UT54ACS138E pin G1
Silkscreen
VSS
Silkscreen
VDD
VDD3_3V
VDD3_3V
VDD3_3V
VDD3_3V
VDD3_3V
VDD3_3V
VDD3_3V
VDD3_3V VDD3_3V
VDD3_3V
ADR4
ADR3
ADR2
ADR1
ADR0
ADR19
ADR21_138
ADR22_138
ADR9
ADR8
ADR7
ADR6
ADR5
ADR20
ADR15
ADR16
ADR17
ADR18
ADR10
ADR11
ADR12
ADR13
ADR14
DATA4
DATA5
DATA6
DATA7
DATA3
DATA2
DATA1
DATA0
CEB_1
CEB_2 CEB_3
CEB_4
OEB
WEB
ADR21_138
WEB
OEB
ADR22_138
ADR21_138 ADR22_138
E1_138_CS CEB_4
CEB_3
CEB_2
CEB_1
ADR0
ADR2
ADR4
ADR6
ADR8
ADR10
ADR12
ADR14
ADR16
ADR18
ADR1
ADR3
ADR5
ADR7
ADR9
ADR11
ADR13
ADR15
ADR17
ADR19 ADR20
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
ROMSN0
IOSN
ROMSN0
IOSN
E1_138_CS
Size
Scale
CAGE Code DWG NO Rev
Sheet
of
-
Aeroflex Colorado Springs
4350252-000
Tuesday, March 20, 2012
22
C
4350 Centennial Blvd.
Colorado Springs
Colorado 80907
64M MRAM EVALUATION BOARD
65342
Size
Scale
CAGE Code DWG NO Rev
Sheet
of
-
Aeroflex Colorado Springs
4350252-000
Tuesday, March 20, 2012
22
C
4350 Centennial Blvd.
Colorado Springs
Colorado 80907
64M MRAM EVALUATION BOARD
65342
Size
Scale
CAGE Code DWG NO Rev
Sheet
of
-
Aeroflex Colorado Springs
4350252-000
Tuesday, March 20, 2012
22
C
4350 Centennial Blvd.
Colorado Springs
Colorado 80907
64M MRAM EVALUATION BOARD
65342
C3
0.1uF
J9
HEADER 2
1 2
R7
10k
R6
10k
+
C7
47uF
J11
HEADER 3
1
2
3
J8
HEADER 2
1 2
C6
0.01uF
C1
0.1uF
J5
HEADER 3
1
2
3
R3
10k
J10
HEADER 2
1 2
C4
0.01uF
CONN_MEZ120
J7
DGND 1
5V 2
DGND 3
-12V 4
DGND 5
+12V 6
DGND 7
D15 8
D7 9
3.3V 10
DGND 11
D14 12
D6 13
D13 14
D5 15
D12 16
D4 17
D11 18
D3 19
3.3V 20
DGND 21
D10 22
D2 23
D9 24
D1 25
D8 26
D0 27
A26 28
A24 29
3.3V 30
DGND 31
A22 32
A20 33
A18 34
A16 35
A14 36
A12 37
A10 38
A8 39
3.3V 40
DGND 41
A6 42
A4 43
A2 44
A0 45
WRITEN 46
OEN 47
ROMSN0 48
RAMSN4 49
3.3V 50
DGND 51
RAMSN3 52
RAMSN2 53
RAMSN1 54
RAMSN0 55
RWEN2 56
RWEN0 57
BRDYN 58
RESETN 59
DGND 60
DGND
120 +5V
119 DGND
118 -12V
117 DGND
116 +12V
115 DGND
114 D31
113 D23
112 3.3V
111 DGND
110 D30
109 D22
108 D29
107 D21
106 D28
105 D20
104 D27
103 D19
102 3.3V
101 DGND
100 D26
99 D18
98 D25
97 D17
96 D24
95 D16
94 A27
93 A25
92 3.3V
91 DGND
90 A23
89 A21
88 A19
87 A17
86 A15
85 A13
84 A11
83 A9
82 3.3V
81 DGND
80 A7
79 A5
78 A3
77 A1
76 READ
75 IOSN
74 ROMSN1
73 RAMOEN4
72 3.3V
71 DGND
70 RAMOEN3
69 RAMOEN2
68 RAMOEN1
67 RAMOEN0
66 RWEN3
65 RWEN1
64 BEXCN
63 CLK
62 DGND
61
U1
54AC138/FP
A0
1
A1
2
A2
3
E1
4
O7 7
GND
8
O6 9
O5 10
O4 11
O3 12
O2 13
O1 14
O0 15
VDD 16
E2
5
E3
6
UT8MR8M8_MQ9_10
U2
VSS
1
VDD
2
NC1
3
NC2
4
E0_B
5
A4
6
A3
7
A2
8
A1
9
A0
10
A19
11
ZZ_NUIL
12
NC3
13
DQ4
14
DQ5
15
VDD
16
VSS
17
DQ6
18
DQ7
19
E1_B
20
E_B_ALL_NUIH
21
A21_NUIL
22
A22_NUIL
23
A9
24
A8
25
A7
26
A6
27
A5
28
VSS
29
VSS
30
VSS
31
VDD
32
VDD 64
VSS 63
NC4 62
NC5 61
E3_B 60
A20 59
A15 58
A16 57
A17 56
A18 55
NC6 54
G_B 53
NC7 52
DQ3 51
DQ2 50
VSS 49
VDD 48
DQ1 47
DQ0 46
E2_B 45
VSS 44
MBE_NUO 43
W_B 42
A10 41
A11 40
A12 39
A13 38
A14 37
VSS 36
VSS 35
VDD 34
VSS 33
J6
HEADER 1
1
J2
HEADER 3
1
2
3
R5
10k
R8
10k
R2
10K
C2
0.01uF
C5
0.1uF

18
ORDERING INFORMATION
UT *****
DeviceType:
8MR8M8-EVB = 64Megabit Non-Volatile MRAM Evaluation Board

19
Aeroflex Colorado Springs - Datasheet Definition
Advanced Datasheet - Product In Development
Preliminary Datasheet - Shipping Prototype
Datasheet - Shipping QML & Reduced Hi – Rel