Aim AMCX-PSI-16 User manual

Hardware
Manual
V01.00 Rev. A
October 2017
AMCX-PSI-16
16 Channels
PANAVIA
PCI Mezzanine Card Module for PMC

AMCX-PSI-16 Hardware Manual
i
AMCX-PSI-16
16 Channels
PANAVIA
PCI Mezzanine Card Module for PMC
V01.00 Rev. A
October 2017
AIM No.
60-14A30-16-0100-A
Hardware
Manual

AMCX-PSI-16 Hardware Manual
ii
AIM –Gesellschaft für angewandte Informatik und Mikroelektronik mbH
AIM GmbH
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D-79111 Freiburg / Germany
Phone [phone]
Fax [phone]
[e-mail]
AIM UK Office
Cressex Enterprise Centre, Lincoln Rd.
High Wycombe, Bucks. HP12 3RB / UK
Phone [phone]
Fax [phone]
[e-mail]
AIM GmbH –Munich Sales Office
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D-80689 München / Germany
Phone [phone]
Fax [phone]
[e-mail]
AIM USA LLC
Seven Neshaminy Interplex
Suite 211 Trevose, PA 19053
Phone [phone]
Fax [phone]
[e-mail]
© AIM GmbH 2017
Notice: The information that is provided in this document is believed to be accurate.
No responsibility is assumed by AIM GmbH for its use. No license or rights are granted by
implication in connection therewith. Specifications are subject to change without notice.

AMCX-PSI-16 Hardware Manual
iii
DOCUMENT HISTORY
The following table defines the history of this document.
Version
Cover Date
Created by
Description
01.00 Rev A
26.10.2017
E. Carraro
First Release

AMCX-PSI-16 Hardware Manual
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AMCX-PSI-16 Hardware Manual
v
TABLE OF CONTENTS
Section Title Page
1. INTRODUCTION .....................................................................................................1
1.1. General ...............................................................................................................1
1.2. How This Manual is Organized............................................................................2
1.3. Applicable Documents.........................................................................................2
1.3.1. Industry Documents ........................................................................................2
1.3.2. Product Specific Documents ...........................................................................2
2. INSTALLATION.......................................................................................................3
2.1. Preparation and Precaution for Installation..........................................................3
2.2. Installation Instructions........................................................................................3
2.3. Connecting to other Devices................................................................................4
2.3.1. Front Panel Connector Pin-out........................................................................5
2.3.2. PMC Connector P11/P12................................................................................6
2.4. Onboard LEDs...................................................................................................10
3. STRUCTURE OF THE AMCX-PSI-16 .....................................................................7
3.1. PCI Express Interface and BIU-I/O FPGA............................................................8
3.1.1. Global RAM Interface and Arbitration..............................................................8
3.1.2. Boot Function..................................................................................................8
3.2. Global RAM.........................................................................................................8
3.3. BIU Section .........................................................................................................8
3.4. BIU-Processor (BIP)............................................................................................9
3.5. PANAVIA Encoder...............................................................................................9
3.6. PANAVIA Decoder ..............................................................................................9
3.7. IRIG- and Time Code Section..............................................................................9
3.8. Timecode Encoder/Decoder................................................................................9
3.9. Time Tag Methods.............................................................................................10
3.10. Power Supply ....................................................................................................10
4. TECHNICAL DATA ...............................................................................................12
5. NOTES ..................................................................................................................17
5.1. Acronyms ..........................................................................................................17
6. APPENDIX ............................................................................................................19

AMCX-PSI-16 Hardware Manual
vi
LIST OF TABLES
Table Title Page
Table 2.1: Fornt Panel Connector Pinout................................................................................5
Table 2.2: Pin Assignment of PMC connector ........................................................................6
Table 2.3: LEDS ordering and meaning................................................................................10
Table 3.1 IRIG-B: Binary Coded Time Tag.............................................................................9
LIST OF FIGURES
Figure Title Page
Figure 2-1 Installing an Air Cooled AMCX-PSI-16 Mezzanine Module....................................4
Figure 2-2 SCSI-3 68 pin Hi-D-SUB Female Connector .........................................................4
Figure 2-3: LEDs positioning on the board............................................................................11
Figure 3-1: AMCX-PSI-16 Internal Structure...........................................................................7

1. Introduction
AMCX-PSI-16 Hardware Manual
1
1. INTRODUCTION
General1.1.
This document comprises the Hardware User’s Manual for the AMCX-PSI-16 Mezzanine
Cards. The document covers the hardware installation, the board connections the technical
data and a general description of the hardware architecture. For programming information
please refer to the documents listed in the ‘Applicable Documents’ section.
The AMCX-PSI-16 modules are members of AIM's new family of advanced PCI based PMC-
Mezzanine (IEEE Std 1386.1) for analyzing, simulating, monitoring and testing of avionic
databus systems.
The AMCX-PSI-16 card is used to simulate, monitor and inject protocol errors of PANAVIA
standard based databus systems. The AMCX-PSI-16 offers a total of 16 PANAVIA channels
with a fixed partitioning of eight receive and eight transmit channels. An onboard IRIG-B
analogue time decoder is included with sinusoidal input and ‘freewheeling’ mode for time tag
synchronization.
The IO connector is a standard SCSI-3 68 pin 1.27mm 90° Hi-D-SUB Female Connector.
The PMC module is designed to be plugged on either a host carrier board to adapt to busses
like standard PCI or cPCI, or on an embedded host computer with PMC ports.
The hardware architecture provides ample resources (i.e. processing capability and memory)
to guarantee, that all specified interface functions are available concurrently and to full
performance specifications.
The advanced architecture uses one processor to handle the 16 data streams. A powerful
Memory Arbiter and PCI-Express Controller is implemented in a Field Programmable Gate
Array (FPGA). This FPGA supports both, the interface to the application and driver software
tasks running on the host computer and assists the communication for data transfer.
This feature expands the capability of the AMCX-PSI-16 module to that of a high level
instrument.
A free-wheeling IRIG-B Time code Decoder is implemented on AMCX-PSI-16 to satisfy the
requirements of 'multi-channel time tag synchronization' on the system level.

AMCX-PSI-16 Hardware Manual
2
How This Manual is Organized1.2.
This AMCX-PSI-16 Hardware Manual is comprised of following sections.
a. Section 1 - Introduction - contains an overview of this manual.
b. Section 2 - Installation - describes the steps required to install the AMCX-PSI-
16 device, and connect the device to other external interfaces
c. Section 3 - Structure of AMCX-PSI-16 - describes the physical hardware
interfaces on the card using a block diagram and a description of each main
component
d. Section 4 - Technical Data - describes the technical specification of AMCX-
PSI-16.
Applicable Documents1.3.
The following documents shall be considered to be a part of this document to the
extent that they are referenced herein. In the event of conflict between the
documents referenced and the contents of this document, the contents of this
document shall have precedence.
1.3.1. Industry Documents
TORNADO A.D. VARIANT Serial Highway Interface Specification
CIS/172126/2052
PCI Local Bus Specification Rev. 3.0 –February 3, 2004
IEEE Standard for a Common Mezzanine Card (CMC) Family,
IEEE Std 1386-2001, 14 June 2001
IEEE Standard Physical and Environmental Layers for PCI Mezzanine Cards
(PMC),
IEEE Std 1386.1-2001, 14 June 2001
1.3.2. Product Specific Documents
AIM - Reference Manual AMCX-PSI-16 Application Interface Library
Detailed description of the programming interface between the Host Carrier board
and the onboard driver software.

2. Installation
AMCX-PSI-16 Hardware Manual
3
2. INSTALLATION
Preparation and Precaution for Installation2.1.
The AMCX-PSI-16 features a 32 PCI bus capability on the PMC connectors, therefore, there
are no jumpers or switches on the board that require modification by the user in order to
interface to the host bus.
It is recommended to use a wrist strap for any installations. If there is no wrist wrap
available, then touch a metal plate on your system to ground yourself and discharge any
static electricity during the installation work.
Installation Instructions2.2.
Please follow the instructions carefully, to avoid any damage on the device.
To Install the AMCX-PSI-16 card
1. Shutdown your system and all peripheral devices.
2. Unplug the power cord from the wall outlet. (Inserting or removing modules
with power applied may result in damage to module devices).
3. Remove the system cover to gain access to the system slots.
4. Remove the PMC carrier board from the system slot.
5. Replace the PMC Slot filler panel from the host front panel.
6. Place the AMCX-PSI-16 mezzanine module on top of the carrier board, with
the PMC connectors on the AMCX-PSI-16 aligned with the corresponding
connectors on the carrier board (see Figure 2-1).
Take care for correct size of the Bezel with ESD-gasket on ESD surface in
host front panel, and the correct size of the voltage keying pins.
7. Then connect the PMC connectors smoothly.
8. Align the standoffs on the AMCX-PSI-16 module with the carrier board. Install
the screws through the holes in the carrier board and the spacers. Tighten the
screws.
9. Install the complete board into its proper card slot. Ensure the module is
seated properly in the backplane connectors. Take care not to damage or
bend connector pins. Secure the board.
10. Replace the cover of your system.
11. Connect the system to the power source. Turn on the power to your
system.

2. Installation
AMCX-PSI-16 Hardware Manual
4
Figure 2-1 Installing an Air Cooled AMCX-PSI-16 Mezzanine Module
Connecting to other Devices2.3.
The external interface of the AMCX-PSI-16 consists of up to up to 8 Transmit and 8
Receive PANAVIA channels as well as the IRIG IN interface for multi-channel time
tag synchronization.
The front panel connector of the AMCX-PSI-16 module is a SCSI-3 68 pin 1.27mm 90° Hi-D-
SUB Female Connector.
Figure 2-2 SCSI-3 68 pin Hi-D-SUB Female Connector
The pinout is similar to the SCSI-3 breakout cable and the PANAVIA differential pairs are
connected to related SCSI-3 differential pairs. In this way it is basically possible to use a
SCSI-3 breakout cable to connect two AMCX-PSI-16 modules or an AMCX-PSI-16 to
another PANAVIA capable device.
35
1
68
34

2. Installation
AMCX-PSI-16 Hardware Manual
5
ATTENTION: the user must assure that the SCSI-3 breakout cable all internal lines are
routed from end to end and that the GND pins are neither connected together into the
cable, nor to the shield. This can create a major failure or a very big ground loop
which can produce a very poor EMC (ElectroMagnetic Compatibility) and very high
EMI (ElectroMagnetic Interference).
2.3.1. Front Panel Connector Pin-out
The front panel pin-out is shown in the following table:
Pin
No.
Signal
Direction
Type
Pin
No.
Signal
Direction
Type
1
CH1_DAT_RX_T
IN
35
CH1_DAT_RX_C
IN
2
CH1_DAT_TX_T
OUT
36
CH1_DAT_TX_C
OUT
3
CH2_DAT _RX_T
IN
37
CH2_DAT _RX_C
IN
4
CH2_DAT _TX_T
OUT
38
CH2_DAT _TX_C
OUT
5
CH3_DAT _RX_T
IN
39
CH3_DAT _RX_C
IN
6
CH3_DAT _TX_T
OUT
40
CH3_DAT _TX_C
OUT
7
CH4_DAT _RX_T
IN
41
CH4_DAT _RX_C
IN
8
CH4_DAT _TX_T
OUT
42
CH4_DAT _TX_C
OUT
9
CH1_CLK_RX_T
IN
43
CH1_CLK_RX_C
IN
10
CH1_CLK_TX_T
OUT
44
CH1_CLK_TX_C
OUT
11
CH2_CLK _RX_T
IN
45
CH2_CLK _RX_C
IN
12
CH2_CLK _TX_T
OUT
46
CH2_CLK _TX_C
OUT
13
CH3_CLK _RX_T
IN
47
CH3_CLK _RX_C
IN
14
CH3_CLK _TX_T
OUT
48
CH3_CLK _TX_C
OUT
15
CH4_CLK _RX_T
IN
49
CH4_CLK _RX_C
IN
16
CH4_CLK _TX_T
OUT
50
CH4_CLK _TX_C
OUT
17
CH7_CLK _TX_T
OUT
51
CH7_CLK _TX_C
OUT
18
CH8_CLK _RX_T
IN
52
CH8_CLK _RX_C
IN
19
CH5_DAT_RX_T
IN
53
CH5_DAT_RX_C
IN
20
CH5_DAT_TX_T
OUT
54
CH5_DAT_TX_C
OUT
21
CH6_DAT _RX_T
IN
55
CH6_DAT _RX_C
IN
22
CH6_DAT _TX_T
OUT
56
CH6_DAT _TX_C
OUT
23
CH7_DAT _RX_T
IN
57
CH7_DAT _RX_C
IN
24
CH7_DAT _TX_T
OUT
58
CH7_DAT _TX_C
OUT
25
CH8_DAT _RX_T
IN
59
CH8_DAT _RX_C
IN
26
CH8_DAT _TX_T
OUT
60
CH8_DAT _TX_C
OUT
27
CH7_CLK _RX_T
IN
61
CH7_CLK _RX_C
IN.
28
GND
Power
62
TRIGGER_OUT
OUT
29
IRIG_IN
IN
63
IRIG_OUT
OUT
30
CH5_CLK_RX_T
IN
64
CH5_CLK_RX_C
IN
31
CH5_CLK_TX_T
OUT
65
CH5_CLK_TX_C
OUT
32
CH6_CLK _RX_T
IN
66
CH6_CLK _RX_C
IN
33
CH6_CLK _TX_T
OUT
67
CH6_CLK _TX_C
OUT
34
CH8_CLK _TX_T
OUT
68
CH8_CLK _TX_C
OUT
Table 2.1: Fornt Panel Connector Pinout

2. Installation
AMCX-PSI-16 Hardware Manual
6
2.3.2. PMC Connector P11/P12
Each PMC connectors include 64 pins divided into 6 rows each one. The pinout for the
connectors P11 and P12 is described in the followed table.
PMC Slot 1 Connector P11
PMC Slot 1 Connector P12
Pin
Signal
Signal
Pin
Pin
Signal
Signal
Pin
1
TCK
-12V
2
1
+12V
TRST#
2
3
GND
PCI_INTA#
4
3
TMS
TDO
4
5
Reserved
Reserved
6
5
TDI
GND
6
7
PCI_BMODE1#
+5V
8
7
GND
Reserved
8
9
Reserved
Reserved
10
9
Reserved
Reserved
10
11
GND
Reserved
12
11
Reserved
+3.3V
12
13
PCI_CLK
GND
14
13
PCI_RESET#
PCI_BMODE3
14
15
GND
PCI_GNT#
16
15
+3.3V
PCI_BMODE4
16
17
PCI_REQ#
+5V
18
17
Reserved
GND
18
19
+5V
PCIAD31
20
19
PCIAD30
PCIAD29
20
21
PCIAD28
PCIAD27
22
21
GND
PCIAD26
22
23
PCIAD25
GND
24
23
PCIAD24
+3.3V
24
25
GND
PCI_CBE3#
26
25
PCI_IDSEL
PCIAD23
26
27
PCIAD22
PCIAD21
28
27
+3.3V
PCIAD20
28
29
PCIAD19
+5V
30
29
PCIAD18
GND
30
31
+5V
PCIAD17
32
31
PCIAD16
PCI_CBE2#
32
33
PCI_FRAME#
GND
34
33
GND
Reserved
34
35
GND
PCI_IRDY#
36
35
PCI_TRDY#
+3.3V
36
37
PCI_DEVSEL#
+5V
38
37
GND
PCI_STOP#
38
39
GND
Reserved
40
39
PCI_PERR#
GND
40
41
Reserved
Reserved
42
41
+3.3V
PCI_SERR#
42
43
PCI_PAR
GND
44
43
PCI_CBE1#
GND
44
45
+5V
PCIAD15
46
45
PCIAD14
PCIAD13
46
47
PCIAD12
PCIAD11
48
47
PCI_M66EN
PCIAD10
48
49
PCIAD9
+5V
50
49
PCIAD8
+3.3V
50
51
GND
PCI_CBE0#
52
51
PCIAD7
Reserved
52
53
PCIAD6
PCIAD5
54
53
+3.3V
Reserved
54
55
PCIAD4
GND
56
55
Reserved
GND
56
57
+5V
PCIAD3
58
57
Reserved
Reserved
58
59
PCIAD2
PCIAD1
60
59
GND
Reserved
60
61
PCIAD0
+5V
62
61
Reserved
+3.3V
62
63
GND
Reserved
64
63
GND
Reserved
64
Table 2.2: Pin Assignment of PMC connector

3. Structure of the AMCX-PSI-16
AMCX-PSI-16 Hardware Manual
7
3. STRUCTURE OF THE AMCX-PSI-16
The structure of the AMCX-PSI-16 mezzanine card is shown in the block diagram here
below:
Figure 3-1: AMCX-PSI-16 Internal Structure
The AMCX-PSI-16 comprises the following main sections:
FPGA
XC6SLX75T
SCSI-3 68 pin Hi-D-SUB Female Connector
8TX (8 Data +8
Clock)
PANAVIA
channels
BIU
Processor
400MHz
DDR2
Controller
(Hard
Coded)
Global RAM
DDR2
128MB
SPI FLASH
TCP/µMON
Microblaze Soft
Coded Processor
SPI FLASH
Novram/FPGA
DMA Engine
(Soft Coded)
PCIe 1.1
Single Lane
(Hard Coded)
PCIe to PCI
Bridge
8x
Encoder
8x
Decoder
SPI update path
32 Bit PCI PMC
Connector
IRIG
B
RS232
Debug Link
Xilinx Arbiter
(Soft Coded)
8RX (8 Data +8
Clock) PANAVIA
channels

3. Structure of the AMCX-PSI-16
AMCX-PSI-16 Hardware Manual
8
PCI Express Interface and BIU-IO FPGA
PCIe to PCI bridge
PCIe to PCI bridge
Global RAM
BIU Section
Physical I/O Interface with up to 16 Panavia channels (8RX/8TX)
IRIG –Time Code Processor with Free Wheeling Function and Sine Wave input
PCI Express Interface and BIU-I/O FPGA3.1.
The new common FPGA architecture of AIM’s new family of PCI Express based Mezzanine
modules includes both the complete PCI Express bus logic and the BIU processor logic. The
PCI Express interface connects to a transparent PCIe-to-PCI bridge which realizes a 32-bit and
66MHz capable PCI upstream port. The programmable device implements the following
features:
PCI Express 1.1 compliant bus
Global RAM interface and arbitration
Boot function
SPI controller for update programming
PANAVIA Encoder
PANAVIA Decoder
IRIG Encoder and Decoder support
3.1.1. Global RAM Interface and Arbitration
The common FPGA implements a Global RAM arbiter, which controls the Global RAM
access between both participants, the Host through the PCI Express bus and the BIU
processor.
3.1.2. Boot Function
To provide maximum flexibility and upgradeability, the FPGA device and the processor
are booted automatically after power up.
Global RAM3.2.
The Global RAM is shared between both BIU processors (BIP) and the Host-Card Bus. The
arbitration is handled by the common FPGA. It has access to the common Global RAM via a 32
bit wide data port.
BIU Section3.3.
One Bus Interface Unit (BIU) is implemented on the PMC module. The BIU handles all
PANAVIA channels. The control logic is implemented in the common FPGA device.

3. Structure of the AMCX-PSI-16
AMCX-PSI-16 Hardware Manual
9
BIU-Processor (BIP)3.4.
The BIU consists of an ultra-low power, high performance 32bit RISC processor.
PANAVIA Encoder3.5.
The Encoder logic is used to send data on the PANAVIA PSI bus generating data
streams and clock pulses. The error injection feature is also performed in the Encoder
logic, together with parity calculation.
PANAVIA Decoder3.6.
The decoder logic is able to organize incoming bits in data words and send them to FW
registers. Synchronization detection and Error detection are also done in the decoder
logic module.
IRIG- and Time Code Section3.7.
The main functions of the Time Code Processor (TCP) are:
a) IRIG-B compatible Time Code Decoder function
b) Time Code Encoder –IRIG-B compatible Time Encoder function
Timecode Encoder/Decoder3.8.
The generated time code signal is an IRIG B compatible signal. The time code
information can be used for time-tagging and multi-channel synchronization. On the
AMCX-PSI-16 a new generation of the IRIG section is implemented with a free-wheeling
IRIG functionality. If no external IRIG signal is detected, the TCP switches automatically
to the free-wheeling operation mode. Also, if an external IRIG-B signal is detected in
free-wheeling mode, the Time tag is automatically synchronized to this external IRIG-B
signal.
The time tag on the board is generated in the format shown in the next table
Table 3.1 IRIG-B: Binary Coded Time Tag
Time Element
Number of bits
DAYS of year
9
HOURS of Day
5
MINUTES of Hour
6
SECONDS of Minute
6
MICROSECONDS of Second
20
Summary
46 (6 Bytes, stored in two 32bit words)

3. Structure of the AMCX-PSI-16
AMCX-PSI-16 Hardware Manual
10
Time Tag Methods3.9.
The IRIG-IN signal shall be connected depending on the time tag method used as shown below.
a. Single AIM-Module no external IRIG-B source
- No connection required
b. Multiple AIM-Modules with no common synchronization requirement
- No connection required
c. Single or multiple AIM-Module(s) with external IRIG-B source
- Connect external IRIG-B source to IRIG-IN and GND of all modules
Power Supply3.10.
The required voltages are provided by standard voltage supplies and special onboard
single low voltage switching power supplies.
The following voltages are needed by the PMC module. They might be provided by a
standard PC power supply.
+3.3V (+/- 5%)
+5V (+/- 5%)
Note: The + 12V is not used.
Trigger Output3.11.
The trigger output signal is high active strobe signals with a pulse width of app. 500 ns. The
outputs are protected by a 82 series resistor. A buffer is provided to the trigger output able to
provide up to ± 30mA.
Onboard LEDs3.12.
The AMCX-PSI-16 card mounts 7x LEDs with different colors which are used to give a visual
feedback to the user during debug. Since the card is a PMC mezzanine card and the LEDs are
placed on the bottom side and not on the fron t panel, any visual indication is available if the
user is placed in line of sigth with the bottom side of the card.
The 7x LEDs are placed in a row with the following order:
Red_1
Green_1
Red_2
Green_2
Yellow_1
Blue_1
Yellow_2
Built-in
Test Error
TX enabled
Error or
clock-loss
RX
enabled
FW
reserved
PCI Activity
FW
reserved
Table 3.2: LEDS ordering and meaning

3. Structure of the AMCX-PSI-16
AMCX-PSI-16 Hardware Manual
11
Figure 3-2: LEDs positioning on the board
The following drawing shows the LED state diagram for the PANAVIA Receiver Error and
Receiver Busy LED's. Please note that this state diagram is implemented on each receive
channel and that the results of all channels after a logical 'OR' are used as LED driving signal.
Figure 3-3: Receive channels’ status indication state diagram
LED Green: OFF
LED Red: OFF
Power up
LED Green: ON
LED Red: OFF
Ch. Enable & no Err.
Ch. disable
LED Green: OFF
LED Red: ON
Ch. Enable & Err.
Or no Data
Ch. disable
Err. Free
LED Green: OFF
LED Red: ON
LED Green: ON
LED Red: ON
Ch. disable
Ch. disable
Error
Error
Err. Free

3. Structure of the AMCX-PSI-16
AMCX-PSI-16 Hardware Manual
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