Aim APE1553-1-DS User manual

Hardware Manual
APE1553-1/2(-DS)
Single/Dual Stream
MIL-STD-1553
PCI Express Card
AIM GmbH
Sasbacher Str. 2
79111 Freiburg, Germany
Tel: [phone]-
0
Fax: [phone]
[e-mail]
www.aim-online.com
May 2015
V01.01 Rev. B

i
APE1553-1/2(-DS)
Hardware Manual
for
Single/Dual Stream
MIL-STD-1553
PCI Express Card
V01.01 Rev. B
May 2015
AIM No: 60-111Dx-16-0101-B

ii
AIM Worldwide
AIM GmbH
Sasbacher Str. 2
79111 Freiburg, Germany
[phone]
[e-mail]
Munich Sales Office
Terofalstrasse 23 a
80689 Muenchen
[phone]
[e-mail]
AIM-USA
Seven Neshaminy Interplex
Suite 211
TREVOSE, PA 19053
267-982-2600
877-520-1553
[e-mail]
AIM UK
Cressex Business Park
Lincoln Rd, High Wycombe
Bucks HP12 3RB, England
[phone]
[e-mail]
Notice: The information that is provided in this document is believed to be accurate.
No responsibility is assumed by AIM for its use. No license or rights are granted by
implication in connection therewith. Specifications are subject to change without notice.
© Copyright 2015, AIM GmbH

iii
DOCUMENT HISTORY
Version Cover Date Created by Description
V01.00 Rev-A
08.09.2011
F.Scherer
First Released Version
V01.00 Rev-B
16.09.2011
F.Scherer
Some corrections
V01.00 Rev-C
21.09.2011
F.Scherer
Some extensions
V01.00 Rev-D
10.11.2011
F.Scherer
Table for B2B connector > +5V and +3.3V
removed
V01.01 Rev-A
07.04.2015
F.Scherer
•Some corrections.
•Change the Word Format-
Template
(Re-Formatting)
•MILScope section included to UM
V01.01 Rev-B
13.05.15
B. Schweitzer
Minor corrections at chapter 3.1.5 and fix
formatting problems

iv
TABLE OF CONTENTS
1Introduction ............................................................................................................1
1.1 General........................................................................................................................................1
1.2 How This Manual is organized..................................................................................................2
1.3 Applicable Documents...............................................................................................................2
1.3.1 Industry Documents.................................................................................................................2
1.3.2 Product Specific AIM Documents ............................................................................................2
2Installation ..............................................................................................................3
2.1 Preparation and Precaution for Installation ............................................................................3
2.2 Installation Instructions.............................................................................................................3
2.3 Frontpanel-Connectors .............................................................................................................4
2.3.1 MIL-STD-1553 Interface Connector.........................................................................................4
2.3.2 Trigger, IRIG and General Purpose Discrete-I/O (GPIO) Interface Connector .......................5
2.3.2.1 Trigger connection ..........................................................................................................6
2.3.2.2 IRIG-B connection...........................................................................................................6
2.3.2.3 GPIO connection.............................................................................................................8
2.3.2.4 RS232 connection.........................................................................................................11
2.4 Board to Board Connector (B2B connector).........................................................................12
2.5 Front Panel LED’s ....................................................................................................................14
3Structure of the APE1553-1/-2.............................................................................15
3.1 PCI Express Interface and BIU-I/O FPGA...............................................................................16
3.1.1 PCI Express Bus Interface.....................................................................................................16
3.1.2 Global RAM Interface and Arbitration....................................................................................16
3.1.3 SPI Controller for SPI-Flash update programming................................................................16
3.1.4 MIL-STD-1553 Encoder.........................................................................................................16
3.1.5 MIL-STD-1553 Decoder.........................................................................................................16
3.1.6 IRIG-B Encoder/Decoder and Timecode Processor (TCP)...................................................17
3.1.7 Maintenance RS232 Interface ...............................................................................................17
3.1.8 External Trigger Inputs and Outputs......................................................................................17
3.1.9 User programmable General Purpose Discrete-I/O (GPIO)..................................................17
3.2 Global RAM...............................................................................................................................18
3.3 BIU Section ...............................................................................................................................18
3.4 Physical Bus Interface with two Dual Redundant MIL-STD-1553B Channels....................18
3.5 Voltage Supplies ......................................................................................................................20
4MILSCOPE FUNCTIONALITY...............................................................................21
4.1 Structure of the APE1553-1/2-DS............................................................................................21
4.1.1 MILScope PBI section............................................................................................................22
4.1.2 MILScope Mainboard section ................................................................................................22
4.2 Implemented MILScope functions..........................................................................................23
4.2.1 Trigger Functions...................................................................................................................23
4.2.2 Input Filter and Noise.............................................................................................................24
4.3 External MILScope A/DC Channels........................................................................................24
5TECHNICAL DATA................................................................................................25
6NOTES...................................................................................................................31
6.1 Acronyms..................................................................................................................................31

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LIST OF FIGURES
Figure 2.3-1: DSUB9 Frontpanel-Connector, Pin1..........................................................4
Figure 2.3.2-1: HD-DSUB26 connector, Pin1..................................................................5
Figure 2.3.2.2-1: B2B IRIG Master/Slave Jumper (J0504)..............................................7
Figure 3.2.2.3-1 Discrete I/O-Pin.....................................................................................9
Figure 3.2.2.3-2 Discrete Output protection ..................................................................10
Figure 2.4-1: B2B Connector for 16-pin ribbon cable....................................................12
Figure 2.4-2: Example for a Ribbon Cable connection..................................................13
Figure 2.5-1: LED description........................................................................................14
Figure 3-1 Block Diagram of APE1553-1/-2 ..................................................................15
Figure 3.4-1: MILbus Coupling Modes...........................................................................19
Figure 3.4-2: MILbus Amplitude vs. DAC value.............................................................20
Figure 4.1-1: Structure of the MILScope .......................................................................21
Figure 4.2-2: MilScope coupling modes ........................................................................22
LIST OF TABLES
Table 2.3.1-1: Pinout DSUB9 Frontpanel-Connector......................................................4
Table 2.3.2-1: Pinout HD-DSUB26 Frontpanel-Connector..............................................5
Table 2.3.2.4-1: RS232 connection...............................................................................11
Table 2.4-1: B2B connector Pinout................................................................................12
Table 2.5-1: LED Descriptions.......................................................................................14
Table 3.1.7-1: Timetag Binary-Format...........................................................................17
Table 4.3-1: Pinout External MILScope inputs..............................................................24

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APE1553-1/2(-DS) Hardware Manual 1
1 INTRODUCTION
1.1 General
This document comprises the Hardware User’s Manual for the APE1553-1 and
APE1553-2 PCIe-Modules.
This document covers the hardware installation, the board connections the technical
data and a general description of the hardware architecture. For programming
information please refer to the documents listed in the ‘Applicable Documents’ section.
The APE1553 modules are members of AIM's new family of advanced PCI Express
cards compliant to PCI Express V1.1. The PCI Express Interface is 1-lane wide and
working with 2.5 Gbit/s in transmit and receive direction.
The APE1553 modules are used to simulate, monitor and inject protocol errors of MIL-
STD-1553A/B based databus systems. The APE1553-1/-2 offers an interface for up to
two dual-redundant MIL-STD-1553 bus channels. Furthermore the interface implements
trigger IN/OUT functions for Bus Controller (BC), Remote Terminal (RT) and Bus
Monitor (BM), as well as 8 user programmable Discrete I/O signals. An additional free
wheeling IRIG-B time code generator allows the user to synchronize to either the
onboard generated time code or the time code of an external board with a resolution of
1us.
Transformer-, Direct-, Network Emulation- and Isolated-Coupling Modes are available
at the external interface connector. A standard breakout cable (2.0 m) is available for
the APE1553 card from DSUB9 connector to four (two, if APE1553-1 module) PL-75
Twinax Connectors.
The hardware architecture provides enough resources (i.e. processing capability and
memory) to guarantee, that all specified interface functions are available concurrently
and to full performance specifications.
A powerful PCI-Express Controller and Memory Arbiter is implemented in a Field
Programmable Gate Array (FPGA). This FPGA supports both, the interface to the
application and driver software tasks running on the host computer and assists the
communication for data transfer.
This feature expands the capability of the APE1553 module to that of a high level
instrument. To fulfil the real-time requirements of a typical avionic type databus system,
a high performance 32bit RISC processor (BIP) is implemented for each Bus Interface
Unit (BIU) / each MIL-STD-1553A/B stream.
A free wheeling IRIG-B Time code Encoder/Decoder is implemented on the APE1553
to satisfy the requirements of 'multi-channel time tag synchronization' on the system
level. The IRIG-B compatible amplitude modulated sinewave output allows the
synchronization of any external module implementing IRIG-B time stamping.

2 APE1553-1/2(-DS) Hardware Manual
1.2 How This Manual is organized
This Hardware Manual is comprised of following sections.
Section 1 - Introduction –
Contains an overview of this manual.
Section 2 - Installation –
Describes the steps required to install the module, and connect the device to
other external interfaces including the MIL-STD-1553 Bus, IRIG-B, and triggers.
Section 3 - Structure of the APE1553-1/-2 –
Describes the physical hardware interfaces on the module using a block diagram
and a description of each main component
Section 4 - Technical Data –
Describes the technical specification of the module.
Section 5 - Notes -
Acronyms etc.
1.3 Applicable Documents
The following documents shall be considered to be a part of this document to the extent
that they are referenced herein. In the event of conflict between the documents
referenced and the contents of this document, the contents of this document shall have
precedence.
1.3.1 Industry Documents
•MIL-STD-1553B, Department of Defence Interface Standard for Digital
Time Division Command/Response Multiplex Data Bus, Notice 1-4,
January 1996
•PCI Express BUS Specification; PCI-SIG, Revision 1.1
1.3.2 Product Specific AIM Documents
AIM - APE1553 Getting Started Manual
Assists the first time user with software installation, hardware setup and
starting a sample project.
AIM - Reference Manual APE1553 Application Interface Library
Provides a detailed description of the programming interface.
AIM – APE1553 Programmer's Guide
Provides the 1553 application developer with high-level s/w development
information including high level system design information, board support
package (BSP) contents, user application system design concepts,
function call guidelines and sample programs.

APE1553-1/2(-DS) Hardware Manual 3
2 INSTALLATION
2.1 Preparation and Precaution for Installation
This module features full PCI Express Plug and Play capability; therefore, there are no
jumpers or switches on the board that require modification by the user in order to
interface to the PCI bus.
It is recommended to use a wrist strap for any installations. If there is no wrist wrap
available, then touch a metal plate on your system to ground yourself and discharge
any static electricity during the installation work.
2.2 Installation Instructions
The following instructions describe how to install the module in your system. Please
follow the instructions carefully, to avoid any damage on the device.
To Install the Module
1. Shutdown your system and all peripheral devices.
2. Unplug the power cord from the wall outlet. (Inserting or removing
modules with power applied may result in damage to module devices).
3. Remove the system cover to gain access to the system slots.
4. Find a free PCIe slot in your system
5. Remove the slot bracket from the slot you have chosen and put the
screw aside.
6. Align the card slot connector with the PCIe slot and gently lower the card
into the free slot.
7. Secure the card to the PCIe slot with the screw you removed from the
metal plate. Ensure the module is seated properly in the slot connector.
8. Replace the cover of your system.
9. Connect the system to the power source. Turn on the power to your
system.

4 APE1553-1/2(-DS) Hardware Manual
2.3 Frontpanel-Connectors
The external interface of the APE1553 provides of up to two dual redundant MIL-STD-
1553 channels, Trigger In/Out signals, as well as the IRIG In/Out signals for time tag
synchronization.
The MILbus interface is provided on a female DSUB9 connector and the Trigger In/Out,
IRIG and GPIO signals are provided on a HD DSUB26 connector.
2.3.1 MIL-STD-1553 Interface Connector
On the APE1553 card all MILbus signals are provided on a female DSUB9 connector at
the front panel.
Pin
No.
Signal Description
1
MILbus Channel 1 Primary (true) (APE1553-1/2)
2
MILbus# Channel 1 Primary (complement) (APE1553-1/2)
3
Shield
4
MILbus Channel 1 Secondary (true) (APE1553-1/2)
5
MILbus# Channel 1 Secondary (complement) (APE1553-1/2)
6
MILbus Channel 2 Primary (true) (APE1553-2 only)
7
MILbus# Channel 2 Primary (complement) (APE1553-2 only)
8
MILbus Channel 2 Secondary (true) (APE1553-2 only)
9
MILbus# Channel 2 Secondary (complement) (APE1553-2 only)
Table 2.3.1-1: Pinout DSUB9 Frontpanel-Connector
1
6
5
9
(front view)
9 Pin DSUB (female)
Figure 2.3-1: DSUB9 Frontpanel-Connector, Pin1
Optional a Breakout cable can be ordered with four two-meter stub cables terminated
with Trumpeter PL-75 plugs.

APE1553-1/2(-DS) Hardware Manual 5
2.3.2 Trigger, IRIG and General Purpose Discrete-I/O (GPIO) Interface Connector
The Trigger, GPIO and IRIG signals are provided on a High-Density DSUB26 female
connector. The RS232 signals are for maintenance purposes only.
Pin No.
Signal
1
RS232 RXD
2
Trigger Output BC, Channel 1
3
Trigger Input BC, Channel 1
4
Trigger Output BC, Channel 2 (APE1553-2 only)
5
Trigger Input BC, Channel 2 (APE1553-2 only)
6
IRIG Input
7
General Purpose Discrete Input/Output 1 (GPIO1)
8
reserved
9
reserved
10
RS232 TXD
11
Trigger Output RT, Channel 1
12
Trigger Input RT, Channel 1
13
Trigger Output RT, Channel 2 (APE1553-2 only)
14
Trigger Input RT, Channel 2 (APE1553-2 only)
15
General Purpose Discrete Input/Output 2 (GPIO2)
16
General Purpose Discrete Input/Output 3 (GPIO3)
17
GND
18
General Purpose Discrete Input/Output 4 (GPIO4)
19
Trigger Output BM, Channel 1
20
Trigger Input BM, Channel 1
21
Trigger Output BM, Channel 2 (APE1553-2 only)
22
Trigger Input BM, Channel 2 (APE1553-2 only)
23
IRIG Output
24
General Purpose Discrete Input/Output 5 (GPIO5)
25
reserved
26
reserved
Table 2.3.2-1: Pinout HD-DSUB26 Frontpanel-Connector
1
10
19
9
18
26
(front view)
26 Pin, High Density DSUB (female)
Figure 2.3.2-1: HD-DSUB26 connector, Pin1

6 APE1553-1/2(-DS) Hardware Manual
2.3.2.1 Trigger connection
Separate trigger inputs / outputs are provided for each MILbus-Channel at the
frontpanel connector.
The minimum trigger pulse length is 75 nanoseconds. For a pulse length shorter than
75ns it can’t be guaranteed that the trigger signal is detected.
The trigger inputs are high active with TTL voltage level and are 5V tolerant.
2.3.2.2 IRIG-B connection
The IRIG-Input and IRIG-Output signals shall be connected depending on the timetag
method used as shown below.
Case 1: Single AIM-Module no external IRIG-B source
- No connection required
Case 2: Multiple AIM-Modules with no common synchronization requirement
- No connection required
Case 3: Single or multiple AIM-Module(s) with external IRIG-B source
- Connect external IRIG-B source to IRIG-IN and GND of all modules
Case 4: Multiple AIM-Modules with no external IRIG-B source internally
synchronized.
- Connect the IRIG-OUT signal and the GND of the module you have
chosen as the time master to all IRIG-IN signals (including the time
master).
The frontpanel IRIG-B I/O is provided at the HD-DSUB26 Frontpanel-Connector.
In addition, a single IRIG-I/O signal is provided on the B2B connector, which can be
used as IRIG-Input (if in slave-mode) or as an IRIG-Output (if set to master-mode).
The IRIG-B output signal can be manually switched to the B2B connector by setting the
jumper position to “Master-Mode”.
ATTENTION:
To avoid signal collision only one board should drive the IRIG output signal.

APE1553-1/2(-DS) Hardware Manual 7
The figure below shows the IRIG Master/Slave jumper (J0504) on the APE1553:
Figure 2.3.2.2-1: B2B IRIG Master/Slave Jumper (J0504)
If the board should receive the IRIG signal, it has to be in IRIG Slave-Mode, if the board
should transmit the IRIG signal, it has to be switched to IRIG Master-Mode.
IRIG Master-Mode (IRIG output):
J0504 has to be set to position 1 and 2
IRIG Slave-Mode (IRIG Input):
J0504 has to be set to position 2 and 3 (or jumper uninstalled)
If set to IRIG Master-Mode, the on board generated IRIG output signal is available
simultaneously on the B2B connector and on the frontpanel of the 1553 Physical Bus
Interface board (1553 PBI).
To receive an external IRIG signal either the PBI IRIG input at the frontpanel or the B2B
connector IRIG input (IRIG Slave Mode) can be used.
Pos1
Pos3
Pos2

8 APE1553-1/2(-DS) Hardware Manual
2.3.2.3 GPIO connection
The APE1553 provides eight General Purpose Discrete I/O's (GPIO’s).
Five General Purpose I/O's (GPIO1 - GPIO5) are provided at the HD-DSUB26
frontpanel connector with Avionic Level inputs and outputs.
All eight GPIO's are provided on the B2B-Connector.
The GPIO’s can be used as simple discrete inputs or outputs, for example to generate
strobes (i.e. to another APE1553 board) or to sample a digital input signal generated
externally.
Discrete input signals are always enabled whereas the discrete output must be enabled
by the user. An open collector circuitry is used for the discrete output with 4V provided
by default. An external voltage from 0 to 35V can be supplied externally for switching
higher voltages. Be aware that a series resistor must be provided when a user specific
voltage is connected to a Discrete I/O (Figure 3.8-1). This serial resistor must limit the
current through the open collector transistor to max. 50 mA. Otherwise the open
collector transistor can be damaged. EMC aspects are covered by filter circuitry.
All eight GPIO’s are available on the ribbon cable B2B connector on the mainboard.
The GPIO’s can be used as simple discrete inputs or outputs, for example to generate
strobes (i.e. to another APE1553 board) or to sample a digital input signal generated
externally.
If all the GPIO’s should be provided externally, an optional Breakout Panel, connected
via the B2B connector can be used.
For more information regarding the Breakout-Panel contact factory.
Note:
The discrete outputs don’t provide a series resistor for over current protection. If using a
discrete input, make sure that the output-mode for that discrete is disabled, before
connecting an external voltage, otherwise the transistor can be damaged caused by a
high short circuit current to GND.

APE1553-1/2(-DS) Hardware Manual 9
Figure 3.2.2.3-1 Discrete I/O-Pin
Ground
FPGA
Output-Pin
Discrete IO-Pin
Front/Rear Connector
APE1553-x
Pulldown
Resistor
Current
limiting
Resistor
1 kOhm
Onboard
5V
Current
limiting
Resistor
10 kOhm
Input-Pin
FPGA
Ground
Discrete output circuitry
Discrete input circuitry

10 APE1553-1/2(-DS) Hardware Manual
Figure 3.2.2.3-2 Discrete Output protection
Discrete IO-Pin
Front/Rear Connector
APE1553-x
User
Offboard
User
FPGA
Output-Pin
Customized
Discrete
R
serial

APE1553-1/2(-DS) Hardware Manual 11
2.3.2.4 RS232 connection
For debugging purposes and board maintenance a RS232 interface is provided. To
establish a RS232 communication link between the APE1553 and a PC – COM-Port
the RS232-TXD/-RXD signals from the 26-pin high density DSUB-Connector have to be
connected with the RS232-TXD/-RXD signals from the PC via a NULL-Modem
connection.
PC RS232 Connector (COM1, COM2, ...)
Module Connector
Signal
DSUB9
HD-DSUB25
TXD
3
2
RXD
2
3
GND
5
7
Signal
HD-DSUB26
RXD
1
TXD
10
GND
17
Table 2.3.2.4-1: RS232 connection

12 APE1553-1/2(-DS) Hardware Manual
2.4 Board to Board Connector (B2B connector)
The Board to Board connector provides the eight General Purpose Discrete I/O signals
(GPIO’s) and an additional “one pin” combined IRIG-B Master-Output/Slave Input on a
16-pin ribbon cable connector (mounted on the upper right corner, see figure the figure
below).
Figure 2.4-1: B2B Connector for 16-pin ribbon cable
Pin
Signal Name
Comments
1
Reserved
Do not connect
2
Reserved
Do not connect
3
ASL GPIO 1
GPIO 1
4
ASL GPIO 2
GPIO 2
5
ASL GPIO 3
GPIO 3
6
ASL GPIO 4
GPIO 4
7
ASL GPIO 5
GPIO 5
8
ASL GPIO 6
GPIO 6
9
ASL GPIO 7
GPIO 7
10
ASL GPIO 8
GPIO 8
11
Reserved
Do not connect
12
IRIG
Master-Output / Slave-Input
13
GND
14
Reserved
Do not connect
15
Reserved
Do not connect
16
Reserved
Do not connect
Table 2.4-1: B2B connector Pinout
For connecting multiple APE1553 boards together a 16-pin standard ribbon cable with a
coded ribbon cable connector is used. It’s important to use coded connectors to avoid
damages caused by signal collisions.
Pin 16
Pin 2
Pin 1