Allwinner A20 User manual

A20

User Manual

Revision 1.2

Dec. 10, 2013

Declaration

THIS A20 USER MANUAL IS THE ORIGINAL WORK AND COPYRIGHTED PROPERTY OF ALLWINNER TECHNOLOGY

(“ALLWINNER”). REPRODUCTION IN WHOLE OR IN PART MUST OBTAIN THE WRITTEN APPROVAL OF

ALLWINNER AND GIVE CLEAR ACKNOWLEDGEMENT TO THE COPYRIGHT OWNER.

THE INFORMATION FURNISHED BY ALLWINNER IS BELIEVED TO BE ACCURATE AND RELIABLE. ALLWINNER

RESERVES THE RIGHT TO MAKE CHANGES IN CIRCUIT DESIGN AND/OR SPECIFICATIONS AT ANY TIME

WITHOUT NOTICE. ALLWINNER DOES NOT ASSUME ANY RESPONSIBILITY AND LIABILITY FOR ITS USE. NOR

FOR ANY INFRINGEMENTS OF PATENTS OR OTHER RIGHTS OF THE THIRD PARTIES WHICH MAY RESULT FROM

ITS USE. NO LICENSE IS GRANTED BY IMPLICATION OR OTHERWISE UNDER ANY PATENT OR PATENT RIGHTS

OF ALLWINNER. THIS DOCUMENTATION NEITHER STATES NOR IMPLIES WARRANTY OF ANY KIND, INCLUDING

FITNESS FOR ANY PARTICULAR APPLICATION.

THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT. CUSTOMERS SHALL BE

SOLELY RESPONSIBLE TO OBTAIN ALLAPPROPRIATELY REQUIRED THIRD PARTY LICENCES. ALLWINNER SHALL

NOT BE LIABLE FOR ANY LICENCE FEE OR ROYALTY DUE IN RESPECT OF ANY REQUIRED THIRD PARTY

LICENCE. ALLWINNER SHALL HAVE NO WARRANTY, INDEMNITY OR OTHER OBLIGATIONS WITH RESPECT TO

MATTERS COVERED UNDER ANY REQUIRED THIRD PARTY LICENCE.

Revision History

Revision

Date

Description

1.0

March 22, 2013

Initial version

1.1

September 17, 2013

Modify TVD and TVE description

1.2

December 10, 2013

Add CAN register description

Table of Contents

Declaration ....................................................................................................................................................2

Revision History.............................................................................................................................................3

Table of Contents...........................................................................................................................................4

Chapter 1 System.....................................................................................................................................9

1.1. Overview................................................................................................................................10

1.2. A20 Block Diagram................................................................................................................18

1.3. Memory Mapping...................................................................................................................19

1.4. CPU Configuration.................................................................................................................23

1.4.1. Overview ........................................................................................................................23

1.4.2. CPU Configuration Register List....................................................................................24

1.4.3. CPUCFG Register Description ......................................................................................25

1.5. CCU.......................................................................................................................................34

1.5.1. Overview ........................................................................................................................34

1.5.2. Clock Tree Diagram .......................................................................................................35

1.5.3. CCU Register List...........................................................................................................35

1.5.4. CCU Register Description..............................................................................................38

1.6. System Boot..........................................................................................................................95

1.6.1. Overview ........................................................................................................................95

1.6.2. System Boot Diagram....................................................................................................96

1.7. System Control......................................................................................................................97

1.7.1. Overview ........................................................................................................................97

1.7.2. System Control Register List .........................................................................................98

1.7.3. System Control Register................................................................................................98

1.8. PWM....................................................................................................................................102

1.8.1. Overview ......................................................................................................................102

1.8.2. PWM Register List........................................................................................................103

1.8.3. PWM Register Description...........................................................................................103

1.9. Timer....................................................................................................................................108

1.9.1. Overview ......................................................................................................................108

1.9.2. Timer Register List.......................................................................................................109

1.9.3. Timer Register Description...........................................................................................110

1.10. High Speed Timer................................................................................................................134

1.10.1. Overview...............................................................................................................134

1.10.2. High Speed Timer Register List............................................................................135

1.10.3. High Speed Timer Controller Register..................................................................136

1.11. GIC ......................................................................................................................................147

1.11.1. Interrupt Source............................................................................................................147

1.12. DMA.....................................................................................................................................152

1.12.1. Overview...............................................................................................................152

1.12.2. DMARegister List.................................................................................................153

1.12.3. DMAController Register Description....................................................................154

1.13. Audio Codec........................................................................................................................171

1.13.1. Overview...............................................................................................................171

1.13.2. Audio Codec Block Diagram.................................................................................172

1.13.3. Audio Codec Register List....................................................................................172

1.13.4. Audio Codec Register Description........................................................................173

1.14. LRADC.................................................................................................................................190

1.14.1. Overview...............................................................................................................190

1.14.2. LRADC Block Diagram.........................................................................................191

1.14.3. LRADC Register List.............................................................................................191

1.14.4. LRADC Register Description................................................................................192

1.15. TP........................................................................................................................................198

1.15.1. Overview...............................................................................................................198

1.15.2. Typical Application Circuit.....................................................................................199

1.15.3. TP Clock Tree .......................................................................................................199

1.15.4. A/D Conversion Time............................................................................................199

1.15.5. Principle of Operation ...........................................................................................201

1.15.6. TP Register List.....................................................................................................206

1.15.7. TP Register Description........................................................................................207

1.16. Security System...................................................................................................................217

1.16.1. Overview...............................................................................................................217

1.16.2. Security System Block Diagram ...........................................................................218

1.16.3. Security System Register List...............................................................................218

1.16.4. Security System Register Description..................................................................219

1.17. Security JTAG .....................................................................................................................226

1.17.1. Overview...............................................................................................................226

1.17.2. Security JTAG Register List..................................................................................227

1.17.3. Security JTAG Register Description.....................................................................227

1.18. Security ID...........................................................................................................................229

1.18.1. Overview...............................................................................................................229

1.18.2. SID Block Diagram................................................................................................230

1.19. Port Controller .....................................................................................................................231

1.19.1. Port Description ....................................................................................................231

1.19.2. Port Configuration Table .......................................................................................232

1.19.3. Port Register List ..................................................................................................238

1.19.4. Port Register Description......................................................................................239

Chapter 2 Memory................................................................................................................................297

2.1. DRAM..................................................................................................................................298

2.1.1. Overview ......................................................................................................................298

2.2. NAND Flash.........................................................................................................................299

2.2.1. Overview ......................................................................................................................299

2.2.2. Nand Flash Block Diagram ..........................................................................................300

2.2.3. NFC Timing Diagram....................................................................................................301

2.2.4. NFC Operation Guide ..................................................................................................306

Chapter 3 Graphic................................................................................................................................309

3.1. Mixer Processor...................................................................................................................310

3.1.1. Overview ......................................................................................................................310

3.1.2. Mixer Processor Block Diagram...................................................................................311

3.1.3. MP Register List...........................................................................................................311

3.1.4. MP Register Description ..............................................................................................313

Chapter 4 Image...................................................................................................................................353

4.1. CSI0.....................................................................................................................................354

4.1.1. Overview ......................................................................................................................354

4.1.2. CSI0 Block Diagram.....................................................................................................355

4.1.3. CSI0 Description ..........................................................................................................355

4.1.4. CSI0 Register List........................................................................................................358

4.1.5. CSI0 Register Description............................................................................................360

4.2. CSI1.....................................................................................................................................388

4.2.1. Overview ......................................................................................................................388

4.2.2. CSI1 Block Diagram.....................................................................................................389

4.2.3. CSI1 Description ..........................................................................................................389

4.2.4. CSI1 Timing Diagram...................................................................................................389

4.2.5. CSI1 Register List........................................................................................................390

4.2.6. CSI1 Register Description............................................................................................391

4.3. TV Decoder..........................................................................................................................403

4.3.1. Overview ......................................................................................................................403

Chapter 5 Display.................................................................................................................................404

5.1. TCON...................................................................................................................................406

5.1.1. Overview ......................................................................................................................406

5.1.2. TCON Block Diagram...................................................................................................407

5.1.3. TCON Register List......................................................................................................408

5.1.4. TCON Register Description..........................................................................................410

5.2. HDMI....................................................................................................................................436

5.2.1. Overview ......................................................................................................................436

5.2.2. HDMI Block Diagram....................................................................................................437

5.2.3. HDMI Control Register Description..............................................................................437

5.2.4. HDMI Register Description...........................................................................................439

5.3. Display Engine Frontend.....................................................................................................477

5.3.1. Overview ......................................................................................................................477

5.3.2. DEFE Block Diagram...................................................................................................478

5.3.3. DEFE Register List.......................................................................................................478

5.3.4. DEFE Register Description..........................................................................................482

5.4. Display Engine Backend .....................................................................................................528

5.4.1. Overview ......................................................................................................................528

5.4.2. Display Engine Block Diagram.....................................................................................529

5.4.3. DEBE Register list........................................................................................................529

5.4.4. DEBE Register Description..........................................................................................532

5.5. TV Encoder..........................................................................................................................574

5.5.1. Overview ......................................................................................................................574

Chapter 6 Interface...............................................................................................................................575

6.1. SD/MMC..............................................................................................................................576

6.1.1. Overview ......................................................................................................................576

6.1.2. SD/MMC Timing Diagram ............................................................................................576

6.2. TWI......................................................................................................................................577

6.2.1. Overview ......................................................................................................................577

6.2.2. TWI Controller Timing Diagram....................................................................................578

6.2.3. TWI Controller Register List.........................................................................................578

6.2.4. TWI Register Description.............................................................................................579

6.2.5. TWI Controller Special Requirement............................................................................587

6.3. SPI.......................................................................................................................................589

6.3.1. Overview ......................................................................................................................589

6.3.2. SPI Timing Diagram.....................................................................................................590

6.3.3. SPI Register List...........................................................................................................591

6.3.4. SPI Register Description..............................................................................................592

6.3.5. SPI Special Requirement.............................................................................................606

6.4. UART...................................................................................................................................607

6.4.1. Overview ......................................................................................................................607

6.4.2. UART Timing Diagram .................................................................................................608

6.4.3. UART Register List.......................................................................................................608

6.4.4. UART Register Description..........................................................................................609

6.4.5. UART Special Requirement.........................................................................................627

6.5. PS2......................................................................................................................................630

6.5.1. Overview ......................................................................................................................630

6.5.2. PS2 Block Diagram......................................................................................................631

6.5.3. PS2 Timing Diagram....................................................................................................631

6.5.4. PS2 Register List..........................................................................................................633

6.5.5. PS2 Register Description.............................................................................................633

6.5.6. PS2 Special Requirements ..........................................................................................641

6.6. IR .........................................................................................................................................642

6.6.1. Overview ......................................................................................................................642

6.6.2. IR Register List.............................................................................................................642

6.6.3. IR Register Description................................................................................................643

6.7. USB DRD.............................................................................................................................656

6.7.1. Overview ......................................................................................................................656

6.7.2. USB DRD Timing Diagram...........................................................................................656

6.8. USB Host.............................................................................................................................657

6.8.1. Overview ......................................................................................................................657

6.8.2. USB Host Block Diagram.............................................................................................658

6.8.3. USB Host Timing Diagram...........................................................................................658

6.8.4. USB Host Register List ................................................................................................658

6.8.5. EHCI Register Description...........................................................................................659

6.8.6. OHCI Register List.......................................................................................................678

6.8.7. OHCI Register Description...........................................................................................679

6.8.8. USB Host Special Requirement...................................................................................696

6.9. Digital Audio Interface .........................................................................................................697

6.9.1. Overview ......................................................................................................................697

6.9.2. Digital Audio Interface Block Diagram..........................................................................698

6.9.3. Digital Audio Interface Timing Diagram........................................................................698

6.9.4. Digital Audio Interface Register List.............................................................................700

6.9.5. Digital Audio Interface Register Description ................................................................700

6.9.6. Digital Audio Interface Special Requirement................................................................717

6.10. AC97 Interface.....................................................................................................................720

6.10.1. Overview...............................................................................................................720

6.10.2. AC97 Block diagram.............................................................................................721

6.10.3. AC97 Interface Clock Tree....................................................................................722

6.10.4. AC Link Frame Format..........................................................................................722

6.10.5. AC97 Interface Timing Diagram............................................................................723

6.10.6. AC97 Interface Register List.................................................................................727

6.10.7. AC97 Interface Register Description....................................................................728

6.10.8. AC97 Interface Special Requirement ...................................................................738

6.11. EMAC ..................................................................................................................................739

6.11.1. Overview ......................................................................................................................739

6.11.2. EMAC Block Diagram ..................................................................................................740

6.11.3. EMAC Operation Diagram ...........................................................................................741

6.12. GMAC..................................................................................................................................744

6.12.1. Overview...............................................................................................................744

6.12.2. GMAC Block Diagram...........................................................................................745

6.13. Transport Stream.................................................................................................................746

6.13.1. Overview...............................................................................................................746

6.13.2. Transport Stream Block Diagram..........................................................................747

6.13.3. Transport Stream Controller Register List............................................................747

6.13.4. Transport Stream Register Description.................................................................749

6.13.5. Transport Stream Clock Requirement ..................................................................768

6.14. Smart Card Reader .............................................................................................................769

6.14.1. Overview...............................................................................................................769

6.14.2. Smart Card Reader Block Diagram......................................................................770

6.14.3. Smart Card Reader Timing Diagram....................................................................770

6.14.4. Smart Card Reader Register List .........................................................................770

6.14.5. Smart Card Reader Register Description.............................................................771

6.14.7. SCIO Pad Configuration.......................................................................................783

6.15. SATA Host...........................................................................................................................784

6.15.1. Overview...............................................................................................................784

6.15.2. SATA_AHCI Timing Diagram................................................................................784

6.16. CAN.....................................................................................................................................785

6.16.1. Overview...............................................................................................................785

6.16.2. CAN System Block Diagram.................................................................................786

6.16.3. CAN Bit Time Configuration..................................................................................786

6.16.4. CAN Controller Register List.................................................................................787

6.16.5. CAN Controller Register Description....................................................................788

6.17. Keypad.................................................................................................................................802

6.17.1. Overview...............................................................................................................802

6.17.2. Keypad Interface Register List..............................................................................803

6.17.3. Keypad Interface Register Description.................................................................803

6.17.4. Keypad Interface Special Requirement................................................................806

Appendix A................................................................................................................................................807

Chapter 1 System

This part details the A20 system construction from following aspects:

OVERVIEW

A20 BLOCK DIAGRAM

MEMORY MAPPING

CPU CONFIGURATION

CCU

BOOT SYSTEM

SYSTEM CONTROL

PWM

TIMER

HIGH SPEED TIMER

GIC

DMA

AUDIO CODEC

LRADC

TP

SECURITY SYSTEM

SECURITY JTAG

SECURITY ID

PORT CONTROLLER

1.1. Overview

Allwinner A20 processor is a dual-core ARM Cortex-A7 mobile application solution designed for tablet and

smart TV applications.

A20 processor is based on a dual-core ARM Cortex-A7 CPU architecture, which is the most energy

efficient application processor from ARM so far and incorporates all the features of Cortex-A15. It also

integrates the powerful ARM Mali400 MP2 GPU, delivering a reliable system performance as well as good

game compatibility. Besides, A20 supports 2160p video decoding and H.264 HP 1080p video encoding.

Additionally, A20 processor features a wide range of interfaces and connectivity, including 4-CH CVBS in,

4-CH CVBS out, HDMI with HDCP, VGA, LVDS/RGB LCD, SATA, USB, and GMAC, etc. More

importantly, A20 processor is pin-compatible with its predecessor A10, which greatly simplifies the product

design process and makes the upgrade of a design much easier.

The A20 features are listed below:

Dual-Core CPU

●Dual Cortex-A7

–ARMv7 ISA standard ARM instruction set

–Thumb-2

–Jazeller RCT

–NEON Advanced SIMD

–VFPv4 floating point

–Hardware virtualization support

–Large Physical Address Extensions(LPAE)

–JTAG debug

–One general timer for per CPU

–32KB Instruction and 32KB Data L1 cache for per CPU

–256KB L2 cache

Graphic Engine

●3D

–Mali400 MP2 GPU

–Support OpenGL ES 2.0 / OpenVG 1.1 standard

●2D

–Support BLT and ROP2/3/4

–Support 90°/180°/270° rotation

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