Allwinner A20 User manual

A20
User Manual
Revision 1.2
Dec. 10, 2013
Copyright © 2013Allwinner Technology Co., Ltd.All Rights Reserved.

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 2 / 812
Declaration
THIS A20 USER MANUAL IS THE ORIGINAL WORK AND COPYRIGHTED PROPERTY OF ALLWINNER TECHNOLOGY
(“ALLWINNER”). REPRODUCTION IN WHOLE OR IN PART MUST OBTAIN THE WRITTEN APPROVAL OF
ALLWINNER AND GIVE CLEAR ACKNOWLEDGEMENT TO THE COPYRIGHT OWNER.
THE INFORMATION FURNISHED BY ALLWINNER IS BELIEVED TO BE ACCURATE AND RELIABLE. ALLWINNER
RESERVES THE RIGHT TO MAKE CHANGES IN CIRCUIT DESIGN AND/OR SPECIFICATIONS AT ANY TIME
WITHOUT NOTICE. ALLWINNER DOES NOT ASSUME ANY RESPONSIBILITY AND LIABILITY FOR ITS USE. NOR
FOR ANY INFRINGEMENTS OF PATENTS OR OTHER RIGHTS OF THE THIRD PARTIES WHICH MAY RESULT FROM
ITS USE. NO LICENSE IS GRANTED BY IMPLICATION OR OTHERWISE UNDER ANY PATENT OR PATENT RIGHTS
OF ALLWINNER. THIS DOCUMENTATION NEITHER STATES NOR IMPLIES WARRANTY OF ANY KIND, INCLUDING
FITNESS FOR ANY PARTICULAR APPLICATION.
THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT. CUSTOMERS SHALL BE
SOLELY RESPONSIBLE TO OBTAIN ALLAPPROPRIATELY REQUIRED THIRD PARTY LICENCES. ALLWINNER SHALL
NOT BE LIABLE FOR ANY LICENCE FEE OR ROYALTY DUE IN RESPECT OF ANY REQUIRED THIRD PARTY
LICENCE. ALLWINNER SHALL HAVE NO WARRANTY, INDEMNITY OR OTHER OBLIGATIONS WITH RESPECT TO
MATTERS COVERED UNDER ANY REQUIRED THIRD PARTY LICENCE.

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Revision History
Revision
Date
Description
1.0
March 22, 2013
Initial version
1.1
September 17, 2013
Modify TVD and TVE description
1.2
December 10, 2013
Add CAN register description

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Table of Contents
Declaration ....................................................................................................................................................2
Revision History.............................................................................................................................................3
Table of Contents...........................................................................................................................................4
Chapter 1 System.....................................................................................................................................9
1.1. Overview................................................................................................................................10
1.2. A20 Block Diagram................................................................................................................18
1.3. Memory Mapping...................................................................................................................19
1.4. CPU Configuration.................................................................................................................23
1.4.1. Overview ........................................................................................................................23
1.4.2. CPU Configuration Register List....................................................................................24
1.4.3. CPUCFG Register Description ......................................................................................25
1.5. CCU.......................................................................................................................................34
1.5.1. Overview ........................................................................................................................34
1.5.2. Clock Tree Diagram .......................................................................................................35
1.5.3. CCU Register List...........................................................................................................35
1.5.4. CCU Register Description..............................................................................................38
1.6. System Boot..........................................................................................................................95
1.6.1. Overview ........................................................................................................................95
1.6.2. System Boot Diagram....................................................................................................96
1.7. System Control......................................................................................................................97
1.7.1. Overview ........................................................................................................................97
1.7.2. System Control Register List .........................................................................................98
1.7.3. System Control Register................................................................................................98
1.8. PWM....................................................................................................................................102
1.8.1. Overview ......................................................................................................................102
1.8.2. PWM Register List........................................................................................................103
1.8.3. PWM Register Description...........................................................................................103
1.9. Timer....................................................................................................................................108
1.9.1. Overview ......................................................................................................................108
1.9.2. Timer Register List.......................................................................................................109
1.9.3. Timer Register Description...........................................................................................110
1.10. High Speed Timer................................................................................................................134
1.10.1. Overview...............................................................................................................134
1.10.2. High Speed Timer Register List............................................................................135
1.10.3. High Speed Timer Controller Register..................................................................136
1.11. GIC ......................................................................................................................................147
1.11.1. Interrupt Source............................................................................................................147
1.12. DMA.....................................................................................................................................152
1.12.1. Overview...............................................................................................................152
1.12.2. DMARegister List.................................................................................................153
1.12.3. DMAController Register Description....................................................................154
1.13. Audio Codec........................................................................................................................171
1.13.1. Overview...............................................................................................................171
1.13.2. Audio Codec Block Diagram.................................................................................172
1.13.3. Audio Codec Register List....................................................................................172
1.13.4. Audio Codec Register Description........................................................................173
1.14. LRADC.................................................................................................................................190

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1.14.1. Overview...............................................................................................................190
1.14.2. LRADC Block Diagram.........................................................................................191
1.14.3. LRADC Register List.............................................................................................191
1.14.4. LRADC Register Description................................................................................192
1.15. TP........................................................................................................................................198
1.15.1. Overview...............................................................................................................198
1.15.2. Typical Application Circuit.....................................................................................199
1.15.3. TP Clock Tree .......................................................................................................199
1.15.4. A/D Conversion Time............................................................................................199
1.15.5. Principle of Operation ...........................................................................................201
1.15.6. TP Register List.....................................................................................................206
1.15.7. TP Register Description........................................................................................207
1.16. Security System...................................................................................................................217
1.16.1. Overview...............................................................................................................217
1.16.2. Security System Block Diagram ...........................................................................218
1.16.3. Security System Register List...............................................................................218
1.16.4. Security System Register Description..................................................................219
1.17. Security JTAG .....................................................................................................................226
1.17.1. Overview...............................................................................................................226
1.17.2. Security JTAG Register List..................................................................................227
1.17.3. Security JTAG Register Description.....................................................................227
1.18. Security ID...........................................................................................................................229
1.18.1. Overview...............................................................................................................229
1.18.2. SID Block Diagram................................................................................................230
1.19. Port Controller .....................................................................................................................231
1.19.1. Port Description ....................................................................................................231
1.19.2. Port Configuration Table .......................................................................................232
1.19.3. Port Register List ..................................................................................................238
1.19.4. Port Register Description......................................................................................239
Chapter 2 Memory................................................................................................................................297
2.1. DRAM..................................................................................................................................298
2.1.1. Overview ......................................................................................................................298
2.2. NAND Flash.........................................................................................................................299
2.2.1. Overview ......................................................................................................................299
2.2.2. Nand Flash Block Diagram ..........................................................................................300
2.2.3. NFC Timing Diagram....................................................................................................301
2.2.4. NFC Operation Guide ..................................................................................................306
Chapter 3 Graphic................................................................................................................................309
3.1. Mixer Processor...................................................................................................................310
3.1.1. Overview ......................................................................................................................310
3.1.2. Mixer Processor Block Diagram...................................................................................311
3.1.3. MP Register List...........................................................................................................311
3.1.4. MP Register Description ..............................................................................................313
Chapter 4 Image...................................................................................................................................353
4.1. CSI0.....................................................................................................................................354
4.1.1. Overview ......................................................................................................................354
4.1.2. CSI0 Block Diagram.....................................................................................................355
4.1.3. CSI0 Description ..........................................................................................................355
4.1.4. CSI0 Register List........................................................................................................358
4.1.5. CSI0 Register Description............................................................................................360
4.2. CSI1.....................................................................................................................................388
4.2.1. Overview ......................................................................................................................388
4.2.2. CSI1 Block Diagram.....................................................................................................389
4.2.3. CSI1 Description ..........................................................................................................389

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4.2.4. CSI1 Timing Diagram...................................................................................................389
4.2.5. CSI1 Register List........................................................................................................390
4.2.6. CSI1 Register Description............................................................................................391
4.3. TV Decoder..........................................................................................................................403
4.3.1. Overview ......................................................................................................................403
Chapter 5 Display.................................................................................................................................404
5.1. TCON...................................................................................................................................406
5.1.1. Overview ......................................................................................................................406
5.1.2. TCON Block Diagram...................................................................................................407
5.1.3. TCON Register List......................................................................................................408
5.1.4. TCON Register Description..........................................................................................410
5.2. HDMI....................................................................................................................................436
5.2.1. Overview ......................................................................................................................436
5.2.2. HDMI Block Diagram....................................................................................................437
5.2.3. HDMI Control Register Description..............................................................................437
5.2.4. HDMI Register Description...........................................................................................439
5.3. Display Engine Frontend.....................................................................................................477
5.3.1. Overview ......................................................................................................................477
5.3.2. DEFE Block Diagram...................................................................................................478
5.3.3. DEFE Register List.......................................................................................................478
5.3.4. DEFE Register Description..........................................................................................482
5.4. Display Engine Backend .....................................................................................................528
5.4.1. Overview ......................................................................................................................528
5.4.2. Display Engine Block Diagram.....................................................................................529
5.4.3. DEBE Register list........................................................................................................529
5.4.4. DEBE Register Description..........................................................................................532
5.5. TV Encoder..........................................................................................................................574
5.5.1. Overview ......................................................................................................................574
Chapter 6 Interface...............................................................................................................................575
6.1. SD/MMC..............................................................................................................................576
6.1.1. Overview ......................................................................................................................576
6.1.2. SD/MMC Timing Diagram ............................................................................................576
6.2. TWI......................................................................................................................................577
6.2.1. Overview ......................................................................................................................577
6.2.2. TWI Controller Timing Diagram....................................................................................578
6.2.3. TWI Controller Register List.........................................................................................578
6.2.4. TWI Register Description.............................................................................................579
6.2.5. TWI Controller Special Requirement............................................................................587
6.3. SPI.......................................................................................................................................589
6.3.1. Overview ......................................................................................................................589
6.3.2. SPI Timing Diagram.....................................................................................................590
6.3.3. SPI Register List...........................................................................................................591
6.3.4. SPI Register Description..............................................................................................592
6.3.5. SPI Special Requirement.............................................................................................606
6.4. UART...................................................................................................................................607
6.4.1. Overview ......................................................................................................................607
6.4.2. UART Timing Diagram .................................................................................................608
6.4.3. UART Register List.......................................................................................................608
6.4.4. UART Register Description..........................................................................................609
6.4.5. UART Special Requirement.........................................................................................627
6.5. PS2......................................................................................................................................630
6.5.1. Overview ......................................................................................................................630
6.5.2. PS2 Block Diagram......................................................................................................631
6.5.3. PS2 Timing Diagram....................................................................................................631

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6.5.4. PS2 Register List..........................................................................................................633
6.5.5. PS2 Register Description.............................................................................................633
6.5.6. PS2 Special Requirements ..........................................................................................641
6.6. IR .........................................................................................................................................642
6.6.1. Overview ......................................................................................................................642
6.6.2. IR Register List.............................................................................................................642
6.6.3. IR Register Description................................................................................................643
6.7. USB DRD.............................................................................................................................656
6.7.1. Overview ......................................................................................................................656
6.7.2. USB DRD Timing Diagram...........................................................................................656
6.8. USB Host.............................................................................................................................657
6.8.1. Overview ......................................................................................................................657
6.8.2. USB Host Block Diagram.............................................................................................658
6.8.3. USB Host Timing Diagram...........................................................................................658
6.8.4. USB Host Register List ................................................................................................658
6.8.5. EHCI Register Description...........................................................................................659
6.8.6. OHCI Register List.......................................................................................................678
6.8.7. OHCI Register Description...........................................................................................679
6.8.8. USB Host Special Requirement...................................................................................696
6.9. Digital Audio Interface .........................................................................................................697
6.9.1. Overview ......................................................................................................................697
6.9.2. Digital Audio Interface Block Diagram..........................................................................698
6.9.3. Digital Audio Interface Timing Diagram........................................................................698
6.9.4. Digital Audio Interface Register List.............................................................................700
6.9.5. Digital Audio Interface Register Description ................................................................700
6.9.6. Digital Audio Interface Special Requirement................................................................717
6.10. AC97 Interface.....................................................................................................................720
6.10.1. Overview...............................................................................................................720
6.10.2. AC97 Block diagram.............................................................................................721
6.10.3. AC97 Interface Clock Tree....................................................................................722
6.10.4. AC Link Frame Format..........................................................................................722
6.10.5. AC97 Interface Timing Diagram............................................................................723
6.10.6. AC97 Interface Register List.................................................................................727
6.10.7. AC97 Interface Register Description....................................................................728
6.10.8. AC97 Interface Special Requirement ...................................................................738
6.11. EMAC ..................................................................................................................................739
6.11.1. Overview ......................................................................................................................739
6.11.2. EMAC Block Diagram ..................................................................................................740
6.11.3. EMAC Operation Diagram ...........................................................................................741
6.12. GMAC..................................................................................................................................744
6.12.1. Overview...............................................................................................................744
6.12.2. GMAC Block Diagram...........................................................................................745
6.13. Transport Stream.................................................................................................................746
6.13.1. Overview...............................................................................................................746
6.13.2. Transport Stream Block Diagram..........................................................................747
6.13.3. Transport Stream Controller Register List............................................................747
6.13.4. Transport Stream Register Description.................................................................749
6.13.5. Transport Stream Clock Requirement ..................................................................768
6.14. Smart Card Reader .............................................................................................................769
6.14.1. Overview...............................................................................................................769
6.14.2. Smart Card Reader Block Diagram......................................................................770
6.14.3. Smart Card Reader Timing Diagram....................................................................770
6.14.4. Smart Card Reader Register List .........................................................................770
6.14.5. Smart Card Reader Register Description.............................................................771

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6.14.7. SCIO Pad Configuration.......................................................................................783
6.15. SATA Host...........................................................................................................................784
6.15.1. Overview...............................................................................................................784
6.15.2. SATA_AHCI Timing Diagram................................................................................784
6.16. CAN.....................................................................................................................................785
6.16.1. Overview...............................................................................................................785
6.16.2. CAN System Block Diagram.................................................................................786
6.16.3. CAN Bit Time Configuration..................................................................................786
6.16.4. CAN Controller Register List.................................................................................787
6.16.5. CAN Controller Register Description....................................................................788
6.17. Keypad.................................................................................................................................802
6.17.1. Overview...............................................................................................................802
6.17.2. Keypad Interface Register List..............................................................................803
6.17.3. Keypad Interface Register Description.................................................................803
6.17.4. Keypad Interface Special Requirement................................................................806
Appendix A................................................................................................................................................807

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Chapter 1 System
This part details the A20 system construction from following aspects:
OVERVIEW
A20 BLOCK DIAGRAM
MEMORY MAPPING
CPU CONFIGURATION
CCU
BOOT SYSTEM
SYSTEM CONTROL
PWM
TIMER
HIGH SPEED TIMER
GIC
DMA
AUDIO CODEC
LRADC
TP
SECURITY SYSTEM
SECURITY JTAG
SECURITY ID
PORT CONTROLLER

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1.1. Overview
Allwinner A20 processor is a dual-core ARM Cortex-A7 mobile application solution designed for tablet and
smart TV applications.
A20 processor is based on a dual-core ARM Cortex-A7 CPU architecture, which is the most energy
efficient application processor from ARM so far and incorporates all the features of Cortex-A15. It also
integrates the powerful ARM Mali400 MP2 GPU, delivering a reliable system performance as well as good
game compatibility. Besides, A20 supports 2160p video decoding and H.264 HP 1080p video encoding.
Additionally, A20 processor features a wide range of interfaces and connectivity, including 4-CH CVBS in,
4-CH CVBS out, HDMI with HDCP, VGA, LVDS/RGB LCD, SATA, USB, and GMAC, etc. More
importantly, A20 processor is pin-compatible with its predecessor A10, which greatly simplifies the product
design process and makes the upgrade of a design much easier.
The A20 features are listed below:
Dual-Core CPU
●Dual Cortex-A7
–ARMv7 ISA standard ARM instruction set
–Thumb-2
–Jazeller RCT
–NEON Advanced SIMD
–VFPv4 floating point
–Hardware virtualization support
–Large Physical Address Extensions(LPAE)
–JTAG debug
–One general timer for per CPU
–32KB Instruction and 32KB Data L1 cache for per CPU
–256KB L2 cache
Graphic Engine
●3D
–Mali400 MP2 GPU
–Support OpenGL ES 2.0 / OpenVG 1.1 standard
●2D
–Support BLT and ROP2/3/4
–Support 90°/180°/270° rotation

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–Support mirror/ alpha (plane and pixel alpha) /color key
–Format conversion: ARGB 8888/4444/1555, RGB565, MONO 1/2/4/8bpp, Palette 1/2/4/8bpp (input
only), YUV 444/422/420
Memory
●Internal BROM
–Support system boot from NAND Flash, SPI Nor Flash (SPI0), SD Card/TF card (SDC0/2)
–Support system code download through USB DRD (Dual-Role Device)
●SDRAM
–Support DDR3/DDR3L/DDR2
–Up to 32-bit bus width
–Support 2GB address space
–16 address signal lines and 3 bank signal lines
●NAND Flash
–Comply to ONFI 2.3 and Toggle 1.0
–Up to 64-bit ECC per 512 bytes or 1024 bytes
–Up to 8bits data bus width
–Support 1K/2K/4K/8K/16K page size
–Up to 8 CE and 2 RB
–Support system boot from NAND flash
–Support SLC/MLC NAND and EF-NAND
–Support SDR/DDR NAND interface
●SD/MMC Interface
–Comply with eMMC standard specification V4.3
–Comply with SD physical layer specification V3.0
–Comply with SDIO card specification V2.0
–1/4/8-bits bus width
–Support HS/DS/SDR12/SDR25 bus mode
–Support eMMC mandatory and alternative boot operations
–Support four independent SD/MMC/SDIO controllers
–Support SDSC/SDHC/SDXC/MMC/ RS-MMC card
–Support eMMC/iNand Flash
–Support 1GB/2GB/4GB/8GB/16GB/32GB/64GB /128GB SD/MMC card
–Support SDIO interrupt detection
–Support descriptor-based internal DMA controller for efficient scatter and gather operations

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System Resources
●Timer
–6 timers: clock source can be switched over 24M/32K for all timers, and external signals can be used
as clock source for Timer4/5
–Two 33-bit AVS counters
–Watchdog to generate reset signal or interrupt
–Real time counter for second, minute, hour, day, month, and year
●High Speed Timer
–4 channels
–Clock source is fixed to AHB, and the pre-scale ranges from 1 to 16
–56-bit counter that can be separated to 24-bit high register and 32-bit low register
●DMA
–16 channels:8 channels with normal DMA,8 channels with dedicated DMA
–Support data width of 8/16/32 bits
–Support linear and IO address modes
●CCU
–8PLLs
–a main 24MHz oscillator
–an on-chip RC oscillator
–a 32768Hz oscillator (optional)
–Clock management: clock gating ,clock enabling to the device modules, clock reset, clock generation,
clock division
●GIC
–Support 16 SGIs, 16 PPIs, and 128 SPIs
–Support ARM architecture security extensions
–Support ARM architecture virtualization extensions
–Support uniprocessor and multiprocessor environments
Video Engine (Phoenix 3.0)
●Video Decoding
–Support picture size up to 3840x2160
–Support decoding speed up to 1080p@60fps
–Supported formats: Mpeg1/2, Mpeg4 SP/ASP GMC, H.263 including Sorenson Spark, H.264
BP/MP/HP, VP6/8, AVS jizun, Jpeg/Mjpeg, etc.
●Video Encoding
–H.264 HP up to 1080p@30fps

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–Jpeg baseline: picture size up to 4080x4080
–Alpha blending
–Thumb generation
–4x2 scaling ratio from 1/16 to 64 arbitrary non-integer ratio
Display Engine
●Four moveable and size-adjustable layers, each layer size up to 8192x8192 pixels
●Ultra-Scaling engine
–8-tap scale filter in horizontal and 4 tap in vertical
–Source image size from 8x4 to 8192x8192 resolution and destination image size from 8x4 to
8192x8192 resolution
●Support multiple image input formats
–mono 1/2/4/8 bpp
–palette 1/2/4/8 bpp
–6/24/32 bpp color
–YUV444/420/422/411
●Support alpha blending/color key/gamma/harware cursor/sprite
●Output color correction: luminance/hue/saturation, etc
●Support de-interlace
●Video enhancement: lum peaking/DCTi/black and white level extension
●3D input/output format conversion and display
Video Output
●HDMI 1.4 transmitter with HDCP
●LVDS/Sync RGB/CPU LCD interface up to 1920x1200 resolution
●Support 4-channel CVBS, or 2-channel S-video, or 1-channel YPbPr/VGA (YPbPr/VGA up to 1080p)
●Support two-channel independent display
Video Input
●Support TV decoder: 4-ch analog CVBS or 1-ch YPbPr(480i/576i/480p/576p) signal input
●Dual CMOS sensor parallel interfaces that support YUV format only
–CSI0 up to 1080p@30fps
–CSI1 up to 720p@30fps
●Support BT656 interface
●Support 24-bit YUV444/RGB interface
Analog Audio Output
●Stereo audio DAC
●Stereo capless headphone drivers
–Up to 100dB SNR during DAC playback
–Support 8KHz~192KHz DAC sample rate

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●One low-noise analog microphone bias
●Dedicated headphone outputs
●Two mixers to meet different requirements
–Output mixer for LINEINL/R, FMINL/R, MIC1/2 and Stereo DAC output
–ADC record mixer for LINEINL/R, FMINL/R, MIC1/2 and Stereo DAC output
Analog Audio Input
●Support four analog audio inputs
–Two microphone inputs
–Differential or stereo line-in input
–Stereo FM-in input
●Stereo audio ADC
–96dBA SNR
–Support 8KHz ~ 48KHz ADC sample rate
RTP
●12-bit SAR ADC
●Dual touch detection
●Sampling frequency up to 2MHz
Connectivity
USB2.0 DRD
●Dual-Role Decive(DRD) Controller
●Support High-Speed (HS, 480-Mbps), Full-Speed (FS, 12-Mbps), and Low-Speed (LS, 1.5-Mbps) in
Host mode
●Support High-Speed (HS, 480-Mbps), Full-Speed (FS, 12-Mbps) in Device mode
●Support up to 5 user-configurable endpoints for Bulk , Isochronous, Control and Interrupt
USB EHCI/OHCI
●Two EHCI/OHCI-compliant hosts
EMAC
●Support 10/100Mbps MII data transfer rate
GMAC
●Comply with the IEEE 802.3-2002 standard
●Programmable frame length to support Standard or Jumbo Ethernet frames with size up to 16KB
●Support 10/100/1000Mbps data transfer rates RGMII interface to communicate with an external Gigabit
PHY
●Support 10/100Mbps MII PHY interface
Digital Audio In/Out

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●One I2S compliant audio interface, supporting 8-channel and 2-channel input
●One PCM, supporting linear sample(8-bit or 16-bit), 8-bit u-law and A-law companded sample
●One AC97 audio codec, supporting 2-channel and 6-channel audio data output
Transport Stream Controller
●Support both SPI and SSI
●Speed up to 150Mbps for both SPI and SSI
●Support 32-channel PID filter
●Support hardware PCR packet detect
Open-Drain TWI
●Up to 5 TWIs(Two Wire Interface)
●Support Standard mode(up to 100K bps) and Fast mode(up to 400K bps)
●Master/Slave configurable
●Allows 10-bit addressing transactions
Smart Card Reader
●One smart card reader controller supporting ISO/IEC 7816-3 and EMV2000 specifications
●Support synchronous and any other non-ISO 7816 and non-EMV cards
SPI
●Full-duplex synchronous serial interface
●Up to 4 independent SPI controllers
●Master/Slave configurable
●Mode0~3 are supported for both transmit and receive operations
●SPI clock are configurable
UART
●Up to 8 UART controllers
–UART0 with two wires for debug tools
–UART1 with 8 wires
–UART2/3 each with 4 wires
–others each with 2 wires
●Compliant with industry-standard 16550 UARTs
●Support Infrared Data Association(IrDA) 1.0 SIR
PS2
●Two PS2 compliant to IBM PS2 and AT-compatible keyboard and mouse interface
●Dual-role controller: a PS2 host or a PS2 device
CIR
●A flexible receiver for IR remote control

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●Up to two IR controllers
●Programmable FIFO thresholds
SATA
●One SATA Host controller
●Support SATA 1.5Gb/s and SATA 3.0Gb/s
●Comply with SATA spec 2.6
●Support external SATA(eSATA)
CAN
●One CAN bus controller
●Support the CAN2.0 A/B protocol specification
●Programmable data rate up to 1Mbps
Keypad
●One keypad matrix interface up to 8 rows and 8 colums
●Interrupt for key press or key release
●Internal debouncing filter to prevent switching noises
LRADC
●6-bit resolution
●Voltage input range between 0V to 2V
●Support hold key and continuous key
●Support single key,normal key and continuous key
PWM
●2 PWM channels outputs
●Support cycle mode and pulse mode
●The pre-scale is from 1 to 64
Security System
●Crypto Engine
–Support AES, DES, 3DES, SHA-1, MD5
–Support ECB/CBC modes for AES/DES/3DES
–128-bit, 192-bit and 256-bit key size for AES
–160-bit hardware PRNG with 192-bit seed
●Security JTAG
Power Management
●Flexible PLL clock generator and OSC for 32KHz
●Flexible clock gate
●Support DVFS for CPU frequency and voltage adjustment

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●Support standby mode (only DDR+RTC-Domain power exist)
Package
●FBGA 441 balls,0.80mm ball pitch, 19x19x1.4mm

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1.2. A20 Block Diagram
The follow figure shows the block diagram of theA20.

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 19 / 812
1.3. Memory Mapping
Module
Address
Size(Bytes)
SRAM A1
0x0000 0000---0x0000 3FFF
16K
SRAM A2
0x0000 4000---0x0000 7FFF
16K
SRAM A3
0x0000 8000---0x0000 B3FF
13K
SRAM A4
0x0000 B400---0x0000 BFFF
3K
SRAM NAND
2K
SRAM D
0x0001 0000---0x0001 0FFF
4K
SRAM B(Secure)
0x0002 0000---0x0002 FFFF
64K
SRAM Controller
0x01C0 0000---0x01C0 0FFF
4K
DRAM Controller
0x01C0 1000---0x01C0 1FFF
4K
DMA
0x01C0 2000---0x01C0 2FFF
4K
NAND Flash
0x01C0 3000---0x01C0 3FFF
4K
Transport Stream
0x01C0 4000---0x01C0 4FFF
4K
SPI 0
0x01C0 5000---0x01C0 5FFF
4K
SPI 1
0x01C0 6000---0x01C0 6FFF
4K
Memory Stick
0x01C0 7000---0x01C0 7FFF
4K
TVD
0x01C0 8000---0x01C0 8FFF
4K
CSI 0
0x01C0 9000---0x01C0 9FFF
4K
TVE 0
0x01C0 A000---0x01C0 AFFF
4K
EMAC
0x01C0 B000---0x01C0 BFFF
4K
LCD 0
0x01C0 C000---0x01C0 CFFF
4K
LCD 1
0x01C0 D000---0x01C0 DFFF
4K
Video Engine
0x01C0 E000---0x01C0 EFFF
4K
SD/MMC 0
0x01C0 F000---0x01C0 FFFF
4K
SD/MMC 1
0x01C1 0000---0x01C1 0FFF
4K
SD/MMC 2
0x01C1 1000---0x01C1 1FFF
4K
SD/MMC 3
0x01C1 2000---0x01C1 2FFF
4K

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 20 / 812
Module
Address
Size(Bytes)
USB 0
0x01C1 3000---0x01C1 3FFF
4K
USB 1
0x01C1 4000---0x01C1 4FFF
4K
Security System
0x01C1 5000---0x01C1 5FFF
4K
HDMI
0x01C1 6000---0x01C1 6FFF
4K
SPI 2
0x01C1 7000---0x01C1 7FFF
4K
SATA
0x01C1 8000---0x01C1 8FFF
4K
PATA
0x01C1 9000---0x01C1 9FFF
4K
ACE
0x01C1 A000---0x01C1 AFFF
4K
TVE 1
0x01C1 B000---0x01C1 BFFF
4K
USB 2
0x01C1 C000---0x01C1 CFFF
4K
CSI 1
0x01C1 D000---0x01C1 DFFF
4K
0x01C1 E000---0x01C1 EFFF
4K
SPI3
0x01C1 F000---0x01C1 FFFF
4K
CCU
0x01C2 0000---0x01C2 03FF
1K
Interrupt
0x01C2 0400---0x01C2 07FF
1K
PIO
0x01C2 0800---0x01C2 0BFF
1K
Timer
0x01C2 0C00---0x01C2 0FFF
1K
SPDIF
0x01C2 1000---0x01C2 13FF
1K
AC97
0x01C2 1400---0x01C2 17FF
1K
IR0
0x01C2 1800---0x01C2 1BFF
1K
IR 1
0x01C2 1C00---0x01C2 1FFF
1K
IIS-1
0x01C2 2000---0x01C2 23FF
1K
IIS-0
0x01C2 2400---0x01C2 27FF
1K
LRADC 0/1
0x01C2 2800---0x01C2 2BFF
1K
AD/DA
0x01C2 2C00---0x01C2 2FFF
1K
Keypad
0x01C2 3000---0x01C2 33FF
1K
0x01C2 3400---0x01C2 37FF
1K
SID
0x01C2 3800---0x01C2 3BFF
1K
SJTAG
0x01C2 3C00---0x01C2 3FFF
1K
0x01C2 4000---0x01C2 43FF
1K
IIS-2
0x01C2 4400---0x01C2 47FF
1K
0x01C2 4800---0x01C2 4BFF
1K