BVM BVME310 User manual

Manual P/N 454-48019 BVM Limited,
Hobb Lane,
Hedge End,
Southampton,
SO30 0GH, UK.
TEL: [phone]
FAX: [phone]
E-MAIL: [e-mail]
WEB: http://www.bvmltd.co.uk
User's Manual
BVME310
MC68000
16-BIT PROCESSOR BOARD
Board Revision E / E1
Manual Revision H February 17, 1997
This material contains information of proprietary interest to BVM Ltd. It has been supplied in
confidence and the recipient, by accepting this material, agrees that the subject matter will not be
copied or reproduced, in whole or in part, nor its contents revealed in any manner or to any person
except to meet the purposes for which it was delivered.

i
DISCLAIMER
The information in this document has been checked and
is believed to be entirely reliable, however no
responsibility is assumed for inaccuracies. BVM Ltd.
reserves the right to make changes and/or improvements
in both the product and the product documentation without
notice. BVM Ltd. does not assume any liability arising out
of the application or use of any product described herein;
neither does it convey any licence under its patent rights
or the rights of others.
USE OF PRODUCT
This product has been designed to operate in a VMEbus
compatible electrical environment. Insertion of the board
into any slot which is not VMEbus compatible is likely to
cause serious damage. Insertion and removal of the board
from the backplane or cable(s) from the board must not be
done whilst in a powered condition.
Do not lever out any devices from the product, which uses
surface-mounted devices extensively, as these can be
fractured by excessive force.
This product uses devices sensitive to static electricity.
Ensure adequate static electricity precautions are
observed when handling the product and associated
devices.
RF. INTERFERENCE
This product was designed with great consideration to
EMC aspects, and includes many of the practices already
used on BVM’s 89/336/EEC compliant products. The
product this far has not been tested and therefore may be
used by OEM’s only.
GENERAL NOTICES
UNPACKING AND INSPECTION
This product contains components which are susceptible
to static discharge, and should be handled with
appropriate caution.
Upon receipt of this product, visually inspect the board for
missing, broken or damaged components and for physical
damage to the printed circuit board or connectors. This
product was shipped in perfect physical condition. Any
physical damage to the product is the responsibility of the
shipping carrier and should be reported to the carrier's
agent immediately.
RETURN OF GOODS
Before returning a product for repair, verify as well as
possible that the suspected unit is at fault. Then call BVM
Ltd. for a Customer Return (CR) number. Carefully
package the unit, in the original shipping carton if this is
available, and ship prepaid and insured, preferably by
courier, with the CR number written on the outside of the
package.
Include a return address and the telephone number of a
technical contact, and a detailed description of the
observed fault. For out-of-warranty repairs, a purchase
order for repair charges must accompany the return. BVM
Ltd. will not be responsible for damage due to improper
packaging of returned items. Out of warranty repairs can
be arranged, and will be charged on a material and labour
basis, subject to a minimum repair charge. Return
transportation and insurance will be charged as part of the
repair and is in addition to the minimum charge.
SOFTWARE LICENCE NOTICE
Any software that is provided as Copyright BVM Ltd. is
proprietary and confidential property of BVM Ltd., and
each single copy is given on the agreed understanding
that it is licensed for use on product combinations
supplied by BVM Ltd. or their appointed distributors only.
The software product may not be copied (except for
backup purposes), given away, rented, loaned,
reproduced, distributed or transmitted in any way or form,
in whole or in part, without written permission of BVM Ltd.
This applies to any merged, modified or derivative version
of the software including, but not limited to, versions
produced by customising, translating, reverse
engineering, decompiling or disassembly.
This licence may be automatically terminated without
notice if any of its provisions are breached. Reasonable
legal costs may be awarded to the prevailing party in
connection with this licence agreement. Use of, or
accepted delivery of these products shall constitute your
acceptance of the provisions of this licence agreement.
WARRANTY
A) BVM Ltd. warrants that the articles furnished hereunder
are free from defects in material and workmanship for one
year after the date of shipment.
B) All warranties and conditions, express and implied,
statutory and otherwise, as to the quality of the goods or
their fitness for any purpose are hereby excluded and with
the exception of liability for death or personal injury
caused by negligence as defined in the Unfair Contract
Terms Act 1977 the seller shall not be liable for any loss,
injury or damage arising directly or indirectly from the use,
application or storage of such goods.
C) Subclause (B) above shall not apply where the buyer
deals as a consumer as this expression is defined in the
Unfair Contract Terms Act 1977.
D) The liability of BVM Ltd. hereunder shall be limited to
repair or replacement at the manufacturers discretion of
any defective unit. Equipment or parts which have been
subject to abuse, misuse, accident, alteration, neglect,
unauthorised repair or installation are not covered by this
warranty. BVM Ltd. shall have the right of determination
as to the existence and cause of any defect.
E) The warranty period of the replacement or a repaired
product or part shall terminate with the termination of the
warranty period with respect to the original product or part
for all replacement parts supplied or repairs made during
the warranty period.
F) Although BVM Ltd. offer a high level of technical
support and advice, due to the complex nature and wide
application of product configurations it is the responsibility
of the purchaser to be satisfied at the time of purchase
that the products are suitable for the final application.
G) The term 'Software' used herein is defined as 'any
program data or code in source or binary format recorded
in or on any readable device or media'.
H) BVM Ltd. will effect all reasonable effort to resolve
accepted reproducible software errors reported within 12
months of purchase. Acceptance of an error shall solely
be based on conformance to supporting specifications.
Proper operation of earlier releases is not guaranteed.
NOTICES
Copyright 1997 by BVM Ltd.
OS-9 is a registered trademark of Microware Systems
Corporation.

Copyright 1997 BVM Ltd.
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Table Of Contents
Contents Page
1. Introduction..........................................................................................................................................1
1.1 Scope.............................................................................................................................................1
1.2 Part Numbers.................................................................................................................................1
2. Overview..............................................................................................................................................2
2.1 Features.........................................................................................................................................2
2.2 Applications....................................................................................................................................3
3. Operation.............................................................................................................................................4
3.1 Block Diagram................................................................................................................................4
3.2 Processor.......................................................................................................................................4
3.3 Memory..........................................................................................................................................4
3.4 Real Time Clock.............................................................................................................................4
3.5 Serial Port ......................................................................................................................................4
3.6 Interrupts........................................................................................................................................5
3.6.1 VMEbus Interrupt Handler......................................................................................... 5
3.6.2 Internal Interrupts.......................................................................................................5
3.7 VMEbus Master..............................................................................................................................5
3.8 VMEbus System Controller Functions ...........................................................................................6
3.9 Reset Management/ Configuration Switch.....................................................................................6
3.10 Local Bus Monitor ........................................................................................................................6
3.11 LED Indicators..............................................................................................................................6
4. VMEbus Installation.............................................................................................................................7
5. Configuration .......................................................................................................................................8
5.1 BVME310 PCB Layout...................................................................................................................8
5.2 Link Definitions...............................................................................................................................8
5.2.1 FL1 EPROM Size Select........................................................................................... 8
5.2.2 JPRB Interrupt Handler Options................................................................................ 9
5.2.3 FL2 VMEbus ACFAIL Interrupt Enable...................................................................10
5.2.4 JPRC System Controller Functions. .......................................................................10
5.2.5 JPRE Parallel Sense Block.....................................................................................11
5.2.6 FL3 68681 IP5 Source ............................................................................................12
5.3 Indicators......................................................................................................................................12
6. Connector Pinouts.............................................................................................................................13
6.1 P1 VMEbus J1 Connector............................................................................................................13
6.2 ja & jb Serial Port Connections ....................................................................................................14
7. Programming.....................................................................................................................................15
7.1 Address Map................................................................................................................................15
7.1.1 Bus Error..................................................................................................................15
7.2 EPROM........................................................................................................................................16
7.3 Real Time Clock (451-48013 only) ..............................................................................................16
7.4 SRAM...........................................................................................................................................16
7.5 Serial Controller ...........................................................................................................................16
7.6 Non Volatile EEPROM (451-48013 only).....................................................................................17

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7.7 VMEbus Master Access...............................................................................................................18
7.7.1 A16:D16 (D08EO) ................................................................................................... 18
7.7.2 A24:D16 (D08EO) ................................................................................................... 18
8. Specification ......................................................................................................................................19
8.1 On-Board Functions.....................................................................................................................19
8.2 VMEbus Master............................................................................................................................19
8.3 VMEbus System Controller Functions .........................................................................................19
8.4 Board Configuration.....................................................................................................................20
8.5 Operating Environment................................................................................................................20
Appendix A - Data Sheets & Manual References..................................................................................21
Appendix B - Circuit Diagrams ..............................................................................................................22

BVME310
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1. Introduction
1.1 Scope
This manual provides:-
A getting started guide.
Configuration details.
A user reference guide.
A memory map.
General Hardware Description.
Information is provided to allow the module to be integrated into a system and configured by the
system engineer. The User manual is intended for use by system integrators, service personnel,
software engineers and end users.
Unless otherwise stated, address information is in hexadecimal notation.
It is assumed the reader has a good knowledge of VMEbus, the 68000 and serial communication
functions.
1.2 Part Numbers
451-48011 3U VME 68000 CPU Module operating at 10MHz, with 512Kbytes EPROM and
512Kbytes SRAM.
451-48013 3U VME 68000 CPU Module operating at 10MHz, with 512Kbytes EPROM, 2Mbytes
SRAM, 128bytes E2PROM and RTC.

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2. Overview
2.1 Features
•68000 CPU, operating at 10Mhz clock rate.
•Up to 128/256/512Kbytes local zero-wait state EPROM.
•512 Kbytes or 2Mbytes local zero-wait state SRAM (Build Option).
•128 byte EEPROM for configuration settings (451-48013 Option).
•Battery backed Real Time Clock (451-48013 Option).
•Reset/Abort Switch.
•Indication LED’s (RUN & EXTERNAL).
•Two RS232 Interrupt Driven Serial I/O Ports with independently programmable baud rates.
•Optimised A24/D16 master VMEbus interface.
VMEbus Interrupt handler 7 level, Vectored and Autovectored.
•System Controller Functions:-
Single level Arbiter.
RESET, SYSCLK generator Bus timeout BERR generator.
•Single slot 3U form factor.
•Fully compatible to VMEbus specification revision C.1.
•Full OS9 Software support.

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2.2 Applications
•VMEbus Main System processor.
•Multi Processing Node.
•Industrial Control.

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3. Operation
3.1 Block Diagram
3.2 Processor
The BVME310 is based on the MC68HC000 16-bit Quad processor a low power version of the 68000.
The module has been designed to operate at 10MHz.
3.3 Memory
EPROM The BVME310 can support 128K, 256K or 512Kbytes of zero wait state ROM in the two
JEDEC sockets. The sockets are compatible with 27C512, 27C010 and 27C020 PROM’s
with device speeds of 250nS and below. Link configuration is necessary for 27C020
support.
SRAM SRAM is available in either 512Kbytes or 2Mbyte configuration and supports zero wait
state operation. The SRAM is a build time option and cannot be upgraded.
EEPROM The BVME310 offers a 128Kbyte of EEPROM for non volatile parameter storage. The
EEPROM is accessed via the 68681’s I/O interface. Link configuration is necessary to
operate the EEPROM.
3.4 Real Time Clock
The BVME310 provides a battery backed real time clock shadowed under the even byte of the
EPROM memory. The clock provides full date and time functions, and is battery backed using a
lithium battery giving typically 10 years of non volatile operation. This option is only available on the
451-48013
3.5 Serial Port
The BVME310 utilises the 68681 to provide two RS232 serial ports each with three handshake lines,
supporting baud rates of up to 38.4Kbits/s. The ports can be accessed via two 14 way IDC connectors
through the Front Panel. The 68681 also provides an extensive Counter/Timer function.

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3.6 Interrupts
3.6.1 VMEbus Interrupt Handler
The BVME310 will support VMEbus interrupts on any of 7 levels. A jumper link is provided to allow
each Interrupt level to individually enabled.
A VMEbus interrupt causes the CPU to reply with a VMEbus Master Interrupt acknowledge cycle. This
cycle uses only IACK that is broadcast in a similar way to the addresses. The A1, A2 and A3 address
lines indicate the address level being handled.
The interrupting device returns an ID vector on the odd data byte. This is used as the user vector by
the CPU.
3.6.2 Internal Interrupts
Internal CPU interrupts are generated from a variety of sources, as detailed in the table below:
Level Source Type
7 VME IRQ7
Abort Switch
ACFAIL
VBCLR
Autovectored
Autovectored
Autovectored
Autovectored
6 VME IRQ6 Vectored
5 VME IRQ5 Vectored
4 VME IRQ4 Vectored
3 VME IRQ3
68681 SERIAL Vectored Vectored
2 VME IRQ2 Vectored
1 VME IRQ1 Vectored
The table shows a number of Interrupt sources, these can be link configured to match the customers
requirements. VMEbus Interface
3.7 VMEbus Master
Byte or word Master accesses may be made to the standard (A24) and short (A16) address spaces.
Read Modify Write (RMW) cycles are supported.
The VMEbus daisy chain arbitration circuitry is optimised to allow very efficient multi-master operation.
Special purpose LSI provides immunity to metasability. Asynchronous arbitration gives BGIN to
BGOUT delay = 15nS worst case.
The BVME310 supports the Release When Done (RWD) VMEbus arbitration method. The method
uses FAIR requesting, ensuring each master has an equal chance of obtaining the bus.

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3.8 VMEbus System Controller Functions
The BVME310 provides a number of system controller functions that may be enabled as follows:-
RESET
Asserted if the +5V falls below +4.7V or the Reset button is pressed, when link selected. VMEbus
RESET has a minimum asserted period of 200mS.
Arbitration
The BVME310 is configured to support Single level arbitration when link selected.
SYSCLK
The BVME310 provides a 16MHz VMEbus SYSCLK when link selected.
VMEBERR
The BVME310 provides a 25.6µS Bus Timeout BERR signal when link selected.
3.9 Reset Management/ Configuration Switch
A MAX700 is used to control the CPU Reset. The device will provide Reset when either the Voltage
drops below 4.7V or the front Panel Reset is pressed. The Reset pulse is in excess of 200mS. Link
configuration allows an external VMEbus module to generate Processor Reset.
The BVME310 has no configuration switch, but a combination of multiple RESET depressions and
SRAM storage can be used to allow access to a configuration program.
3.10 Local Bus Monitor
The BVME310 provides a 25.6µS a local Bus Timeout BERR signal for internal accesses, BERR for
external accesses is set by the system controller.
3.11 LED Indicators
GREEN LED Indicates processor activity.
RED LED Indicates EXTERNAL activity (to the VMEbus).

BVME310
Copyright 1997 BVM Ltd.
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4. VMEbus Installation
The BVME310 module is inserted into a vacant VMEbus slot. If it is to function as the system
controller, then it should be positioned in the left most slot. It passes through all VMEbus daisy chained
arbitration signals.
IACK should be jumpered to IAKIN on the backplane in the left hand slot. All interrupt IAKIN to
IAKOUT and BGIN to BGOUT signals should be jumpered across vacant slots to the left of the
module.
If it is not the system controller, it may be located in any of the VMEbus slots to the right of the
VMEbus system controller.
To install the BVME310:-
1. Ensure all backplane jumpers associated with the slot for the BVME310 are removed.
2. Ensure the BVME310 module is correctly configured for the target system.
3. Insert the BVME310 module into the rack pushing the VMEbus connector fully home.
4. Secure the BVME310 into the rack with the two fixing screws top and bottom.
5. Plug in serial cable to ja and or jb.
Removal is the reverse of assembly.
If the test or application software fails, ensure that all installation instructions have been correctly
carried out. Some typical reasons for incorrect operation are:-
1. Socketed components may become disturbed in transit. Push home all socketed components
where suspect.
2. The BVME310 module uses the VMEbus Address modifier codes to determine address
significance. Ensure the host CPU module produces the correct address modifier codes.
3. Ensure that all links are configured to the default set-up or that any alterations to the default
are correctly configured.
4. Ensure that the VMEbus backplane (if used) is correctly configured with regard to the daisy-
chain signal jumpers and the IACK termination jumpers (if any).

BVME310
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5. Configuration
5.1 BVME310 PCB Layout
5.2 Link Definitions
The following link definitions show the links grouped in the same orientation as the layout drawing
above, i.e. the VMEbus P1 connectors to the left. Link positions marked with a ›show the BVME310
default configuration.
The following features on the BVME310 are all link selectable:-
5.2.1 FL1 EPROM Size Select

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1 & 2 Fitted ›27C512 (512Kbit) or 27C010 (1Mbit) devices
2 & 3 Fitted 27C020 (2Mbit) devices
FL1 determines the EPROM size supported by the BVME310. When FL1 is fitted in positions 1 and 2,
the BVME310 will support 27C512 or 27C010 devices giving 128/256Kbytes of EPROM space. When
FL1 is fitted in positions 2 and 3, the BVME310 will support 27C020 devices giving 512Kbytes of
EPROM space.
On the 451-48011 variant FL1 is fitted with a factory link permanently in position 1 and 2 and therefore
the BVME310 should only be fitted with 27C512 or 27C010 devices. On the 451-48013 variant the
user may select the EPROM size, by default the link is set to position 1 and 2.
The BVME310 should always be fitted with 250nS devices or faster regardless of size.
5.2.2 JPRB Interrupt Handler Options
Link Setting Interrupt Level Interrupt Source Acknowledge type
1 & 18 Fitted ›7 Abort Switch Autovectored
1 & 9 Fitted 7 VMEbus ACFAIL Autovectored
1 & 8 Fitted 7 VMEbus BCLR Autovectored
1 & 17 Fitted 7 VME IRQ7 Autovectored
2 & 16 ›6 VME IRQ6 Vectored
3 & 15 ›5 VME IRQ5 Vectored
4 & 14 ›4 VME IRQ4 Vectored
5 & 13 ›3 68681 IRQ Vectored
5 & 10 3 VME IRQ3 Vectored
6 & 12 ›2 VME IRQ2 Vectored
7 & 11 ›1 VME IRQ1 Vectored
JPRB is used to select the interrupt sources for the BVME310 as shown in the table above. It is
recommended that for a level where more than one interrupt source is available, only one is chosen
except ABORT and VMEbus ACFAIL where both may be set to generate IRQ7. FL2 may also be
used to select VMEbus ACFAIL, and when set will be enabled regardless of the setting on JPRB.

BVME310
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5.2.3 FL2 VMEbus ACFAIL Interrupt Enable
1 & 2 Fitted ›VMEbus ACFAIL Interrupt Source Enabled.
1 & 2 Omitted VMEbus ACFAIL Interrupt Source Disabled.
FL2 is used to select ACFAIL as an Interrupt source. When fitted ACFAIL is enabled to drive IRQ7
should the fault condition occur. On the 451-48011 variant this link is fitted with a factory link
permanently enabling ACFAIL. On the 451-48013 variant the status can be set by the user. If ACFAIL
is selected by JPRB, that will override the setting of this link.
5.2.4 JPRC System Controller Functions.
1 & 2 Fitted ›CPU Reset will generate a VME Reset.
3 & 4 Fitted ›VMEbus SYSCLK Driven.
5 & 6 Fitted ›VMEbus Timeout Monitor Enabled.
7 & 8 Fitted ›VMEbus SGL Arbiter Enabled. (Level 3)
JPRC is used to enable the system controller functions, when the BVME310 is the System controller
all links should be fitted.
Link position 1 & 2 enables a push button Reset or a Power up Reset to generate a VMEbus Reset
when fitted.
Link position 3 & 4 enables the BVME310 to generate the 16MHz VMEbus SYSCLK signal when
fitted.

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Link position 5 & 6 enables the BVME310 as the VMEbus Timeout Monitor when fitted. The BVME310
will generate a VME BERR if any cycle on the VMEbus lasts longer than 25.6µS.
Link position 7 & 8 enables the BVME310 to operate as the single level SGL arbiter when fitted. SGL
arbitration operates on level 3 only.
5.2.5 JPRE Parallel Sense Block
1 & 2 Fitted 68681 IP4 bit Set High
2 & 3 Fitted 68681 IP4 bit Set Low
4 & 5 Fitted 68681 IP5 bit Set High
5 & 6 Fitted 68681 IP5 bit Set Low
7 & 8 Fitted 68681 IP6 bit Set High
8 & 9 Fitted 68681 IP6 bit Set Low
JPRE provides three parallel sense bits which may be read by the MPU through the MC68681.
BE CAUTIOUS NEVER TO CONNECT ANY OF THE SET [3,6,9] TO ANY OF THE SET [1,4,7]!!!

BVME310
Copyright 1997 BVM Ltd.
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5.2.6 FL3 68681 IP5 Source
1 & 2 Fitted ›68681 IP5 monitors the Abort Button.
2 & 3 Fitted 68681 IP5 connected to EEPROM O/P
FL3 determines the source for the 68681 Input IP5 . When FL3 is fitted in positions 1 and 2, IP5 is
used to monitor the status of the Abort Button. When FL3 is fitted in positions 2 and 3, IP5 is used as
the Data input from the EEPROM.
On the 451-48011 variant FL3 is fitted with a factory link permanently in position 1 and 2 because the
EEPROM is not fitted. On the 451-48013 by default FL3 fitted in position 2 and 3 to allow the
EEPROM to be read, however on this variant the status can be set by the user.
5.3 Indicators
RED LED Indicates the BVME310 is the current VMEbus Master.
GREEN LED Indicates processor currently running valid code. The LED will be extinguished by a
RESET.

BVME310
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6. Connector Pinouts
6.1 P1 VMEbus J1 Connector
Pin Number Row A
Signal Mnemonic Row B Signal Mnemonic Row C Signal Mnemonic
1 D0 /BBSY D8
2D1/BCLRD9
3D2/ACFAILD10
4 D3 /BG0IN D11
5 D4 /BG0OUT D12
6 D5 /BG1IN D13
7 D6 /BG1OUT D14
8 D7 /BG2IN D15
9 GND /BG2OUT GND
10 SYSCLK /BG3IN /SYSFAIL
11 GND /BG3OUT /BERR
12 /DS1 /BR0 /SYSRESET
13 /DS0 /BR1 /LWORD
14 /WRITE /BR2 AM5
15 GND /BR3 A23
16 /DTACK AM0 A22
17 GND AM1 A21
18 /AS AM2 A20
19 GND AM3 A19
20 /IACK GND A18
21 /IACKIN SERCLK A17
22 /IACKOUT SERDAT A16
23 AM4 GND A15
24 A7 /IRQ7 A14
25 A6 /IRQ6 A13
26 A5 /IRQ5 A12
27 A4 /IRQ4 A11
28 A3 /IRQ3 A10
29 A2 /IRQ2 A9
30 A1 /IRQ1 A8
31 -12V +5V STDBY +12V
32 +5V +5V +5V
Signals shown in the shaded boxes are not used.
The following signals are not required by the BVME310, but have been connected onboard to preserve
the VMEbus daisy chain:-
IACKIN is connected to IACKOUT,
BG0IN is connected to BG0OUT,
BG1IN is connected BG1OUT
BG2IN is connected to BG2OUT.

BVME310
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6.2 ja & jb Serial Port Connections
ja and jb carry the serial port signals for Serial Channel A and Serial Channel B. jb (Serial Channel A)
is the lower connector. The layout is designed to connect directly to a standard 25-way connector as
shown:
The pinout numbering conventions are different
for the two styles of connector (see diagram).
However, the pinout is arranged to give a one to
one connection to a 25-way D-type connector
when using Insulation Displacement Connectors
(IDC) and ribbon cable.
Not all the RS232 signals defined for a 25 way
connector are supported by the BVME310. The
cable assembly should be built such that pin 1
on the 14 way connector connects to pin 1 of the
25 way. A 14 way ribbon cable is used leaving
pins 8 - 13 and 21 - 25 unconnected.

BVME310
Copyright 1997 BVM Ltd.
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7. Programming
The following section describes the programming information required to run the basic functionality of
the BVME310. This section includes specific peripheral locations and basic programming information
on the Key devices. More information can be found on many of the devices in the relevant data
sheets. See Appendix Appendix A for more information.
7.1 Address Map
Two address maps are available on the BVME310. The ‘standard’ map is used on the 451-48011 and
allows for 512Kbytes of SRAM. The ‘alternative’ address map allows for 2Mbyte of SRAM an is used
on the 451-48013. The address map is set in the PLD and may be changed to meet user
requirements. Please contact your supplier for more information.
Notes:
Where a peripheral has a size smaller than the allocated memory space, the peripheral wraps around
repeatedly. Thus the device is accessible anywhere within its allocated address space. For future
compatibility, devices should only be accessed at their lowest location.
7.1.1 Bus Error
Unused locations will not return a DTACK and will result in a CPU bus error. A Bus error will also occur
on an access to a VMEbus location that does not return a DTACK within this period. The CPU bus
error timeout period for the BVME310 is 25.6µS. The CPU bus error timer is also dependant on
VMEbus error which the BVME310 monitors.
SERIAL A/B
512Kbyte SRAM
VMEbus Standard
(A24 Address)
unused
512Kbytes EPROM
VMEbus Short
(A16 Address)
'Standard'
000000
080000
100000
F00000
FE0000
FF0000
FFFFFF
SERIAL A/B
2Mbytes SRAM
VMEbus Standard
(A24 Address)
unused
512Kbytes EPROM
VMEbus Short
(A16 Address)
'Alternative'
000000
080000
280000
F00000
FE0000
FF0000
FFFFFF

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7.2 EPROM
EPROM: 000000
Size: 128/256/512Kbytes
Width: 16 Bit
Access: Read
The BVME310 provides 2 x 32-pin EPROM JEDEC compatible sockets which may be fitted with
27C512, 27C010 or 27C020 devices, depending on the setting of FL1, providing 128Kbytes -
512Kbytes of PROM.
The memory provides zero wait state access to the CPU providing device speeds of 250nS or faster
are used.
7.3 Real Time Clock (451-48013 only)
The 451-48013 variant of the BVME310 provides a RTC which is 'shadowed' under the even byte
EPROM. A highly structured sequence of 64 cycles is used to gain access to the time information and
temporarily disconnect the EPROM from the system bus. Information transfer is achieved by using
address bits CPUA1 and CPUA3 and data bit CPUD24. All RTC operations are then accomplished by
read cycles from the EPROM address space. Write and Read operations are determined by the level of
CPUA3. When CPUA3 is low, a write cycle is enabled and the data is determined by CPUA1. When
CPUA3 is high, a read operation is enabled and data is read on CPUD8.
As the EPROM is disabled when accessing the RTC, the code to access it must first be copied to RAM
and executed from there.
For further information refer to the DS1215 data sheet, see Appendix Appendix A.
7.4 SRAM
SRAM: 080000
Size: (451-48011) 512Kbytes
Size: (451-48013) 2Mbytes
Width: 16 Bit
Access: Read/Write
The BVME310 is factory fitted with 512Kbytes of SRAM on the 451-48011 or 2Mbytes on the 451-
48013. The memory which is accessed as a 16-bit block again provides zero wait state access to the
CPU.
7.5 Serial Controller
Serial Controller FE0001
Size: 32 Words
Width: 8 Bit
Access: Read/Write
The BVME310 provides two serial ports operating up to 38.4Kbaud. The ports are controlled using the
MC68681 Dual Universal Asynchronous Receiver Transmitter which also provides a multi-functional
Counter/Timer.