Alpha Data ADM-VPX3-9Z2 User manual

ADM-VPX3-9Z2
User Manual
Document Revision: 1.1
16t January 2020

ADM-VPX3-9Z2 User Manual
V1.1 - 16t January 2020
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ADM-VPX3-9Z2 User Manual
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able Of Contents
1 Introduction ...................................................................................................................................... 1
1.1 Key Features ................................................................................................................................. 1
1.2 References & Specifications .......................................................................................................... 1
1.3 rder Code .................................................................................................................................... 2
2 Installation ........................................................................................................................................ 3
2.1 Handling Instructions ..................................................................................................................... 3
2.2 Hardware Installation ..................................................................................................................... 3
2.2.1 System Requirements ............................................................................................................... 3
2.2.2 Cooling Requirements ............................................................................................................... 3
2.3 Software Installation ...................................................................................................................... 4
3 Functional Description .................................................................................................................... 5
3.1 verview ........................................................................................................................................ 5
3.1.1 Switch Definitions ...................................................................................................................... 6
3.1.2 LED Definitions .......................................................................................................................... 7
3.2 VPX P0 Interface ........................................................................................................................... 9
3.2.1 SYSRESET# .............................................................................................................................. 9
3.2.2 AUXCLK ..................................................................................................................................... 9
3.2.3 REFCLK ..................................................................................................................................... 9
3.3 VPX P2 GPI ................................................................................................................................ 9
3.3.1 LVDS .......................................................................................................................................... 9
3.4 JTAG Interface ............................................................................................................................. 10
3.4.1 n-board Interface ................................................................................................................... 10
3.4.2 VPX Interface ........................................................................................................................... 10
3.4.3 JTAG Voltages ......................................................................................................................... 10
3.5 Clocks .......................................................................................................................................... 11
3.5.1 I Delay Reference Clock (FABRIC_CLK) .............................................................................. 12
3.5.2 Fixed 100MHz Reference clock REFCLK100M ....................................................................... 12
3.5.3 Programmable Clocks (PR GCLK1 and PR GCLK2) ........................................................... 12
3.5.4 Module to Carrier Global Clocks (CLK_M2C) .......................................................................... 13
3.5.5 Module to Carrier MGTREF Clocks (GBTCLK_M2C) .............................................................. 13
3.5.6 PS_REFCLK ............................................................................................................................ 13
3.5.7 VIDE _CLK ............................................................................................................................. 13
3.5.8 USB_REFCLK24M .................................................................................................................. 14
3.5.9 ETH_CLK25M .......................................................................................................................... 14
3.6 Resets .......................................................................................................................................... 14
3.7 Zynq PS Block ............................................................................................................................. 14
3.7.1 Boot Modes .............................................................................................................................. 14
3.7.2 PS Memory Interfaces ............................................................................................................. 14
3.7.2.1 Quad SPI Flash Memory ..................................................................................................... 14
3.7.2.2 MicroSD and eMMC Flash Memories .................................................................................. 15
3.7.2.3 PS DDR4 Memory ............................................................................................................... 15
3.7.3 Ethernet Interfaces .................................................................................................................. 15
3.7.4 Serial C M Ports ..................................................................................................................... 15
3.7.5 USB Interfaces ......................................................................................................................... 16
3.8 Zynq PL Block .............................................................................................................................. 16
3.8.1 I/ Bank Voltages .................................................................................................................... 16
3.8.2 PL MGT Links .......................................................................................................................... 16
3.8.3 FMC+ GPI Interface .............................................................................................................. 17
3.8.4 VPX P2 GPI Interface ........................................................................................................... 17
3.9 System Monitoring ....................................................................................................................... 17
3.9.1 Automatic Temperature Monitoring .......................................................................................... 18
3.9.2 System Monitor Status LEDs ................................................................................................... 18

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3.10 FMC Interface and Front-Panel I/ ............................................................................................. 19
Appendix A P1 Pin Assignments ...................................................................................................................... 21
A.1 Data Plane (P1 Wafers 1-4) ......................................................................................................... 21
A.2 Data/Expansion Plane (P1 Wafers 5-8) ....................................................................................... 21
A.3 Expansion/User Plane (P1 Wafers 9-14) ..................................................................................... 22
A.4 Control Plane (P1 Wafers 15-16) ................................................................................................. 22
Appendix B P2 Pin Assignments ...................................................................................................................... 23
B.1 GPI (P2 Wafers 4-6) ................................................................................................................. 23
Appendix C FMC Pin Assignments ................................................................................................................... 24
C.1 GPI Pins .................................................................................................................................... 24
C.2 Clock Pins .................................................................................................................................... 26
C.3 MGT Pins ..................................................................................................................................... 27
List of ables
able 1 References ........................................................................................................................................ 1
able 2 Build Options ..................................................................................................................................... 2
able 3 Reset Switch Definitions .................................................................................................................... 6
able 4 VPX Control Switch Definitions (SW3) .............................................................................................. 6
able 5 Processor Setup Switch Definitions (SW4) ........................................................................................ 6
able 6 Main LED Definitions ......................................................................................................................... 8
able 7 Ethernet LED Definitions ................................................................................................................... 8
able 8 USB LED Definitions .......................................................................................................................... 8
able 9 DDR REFCLK Connections ............................................................................................................. 12
able 10 REFCLK100M Connections ............................................................................................................. 12
able 11 PROGCLK1 Connections ................................................................................................................ 12
able 12 PROGCLK2 Connections ................................................................................................................ 12
able 13 CLK_M2C Connections ................................................................................................................... 13
able 14 GCLK_M2C Connections ................................................................................................................ 13
able 15 PS_REFCLK Connection ................................................................................................................. 13
able 16 VIDEO_REFCLK Connection .......................................................................................................... 14
able 17 Reset Switches ................................................................................................................................ 14
able 18 Boot Mode Selection ........................................................................................................................ 14
able 19 Ethernet Status LEDs ...................................................................................................................... 15
able 20 PL FPGA IO Banks .......................................................................................................................... 16
able 21 PL MG Links .................................................................................................................................. 16
able 22 FMC+ Groups (J1) ........................................................................................................................... 17
able 23 VPX P2 GPIO Groups ..................................................................................................................... 17
able 24 Voltage and emperature Monitors (in microcontroller) ................................................................... 18
able 25 emperature Limits .......................................................................................................................... 18
able 26 System Monitor Status LEDs ........................................................................................................... 19
able 27 Data Plane (P1 Wafers 1-4) ............................................................................................................. 21
able 28 Data/Expansion Plane (P1 Wafers 5-8) ........................................................................................... 21
able 29 Expansion/User Plane (P1 Wafers 9-14) ......................................................................................... 22
able 30 Control Plane (P1 Wafers 15-16) ..................................................................................................... 22
able 31 GPIO (P2 Wafers 4-6) ...................................................................................................................... 23
able 32 GPIO Pins ........................................................................................................................................ 24
able 33 Clock Pins ........................................................................................................................................ 26
able 34 MG Pins ......................................................................................................................................... 27

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List of Figures
Figure 1 ADM-VPX3-9Z2 Air Cooled ............................................................................................................... 4
Figure 2 ADM-VPX3-9Z2 Block Diagram ......................................................................................................... 5
Figure 3 LED Locations ................................................................................................................................... 7
Figure 4 J AG Boundary Scan Chain ............................................................................................................ 10
Figure 5 Clocks .............................................................................................................................................. 11
Figure 6 Ethernet Interfaces .......................................................................................................................... 15
Figure 7 Serial COM Ports ............................................................................................................................. 15
Figure 8 USB Interfaces ................................................................................................................................. 16

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1 Introduction
he ADM-VPX3-9Z2 shall be a high performance reconfigurable 3U OpenVPX format board based on the Xilinx
Zynq Ultrascale+ range of Multiprocessor System-on-Chips (MPSoC).
1.1 Key Features
Key Features
• 3U Open VPX, compliant to VI A Standard 46.0 and 65
• FMC+ interface compliant to Vita 57.4 with high density connector
• Support for Zynq Ultrascale+ ZU9/ZU15 MPSoC in FFVB1156 package
• VPX P1 utilized according to OpenVPX payload slot profile SL 3-PAY-1F1F2U-14.2.4
• 4 optical duplex lanes at data rates of up to 10Gbps as described in Vita 66.4
• Half width P2 with 24 GPIO as described in Vita 66.4
• Processing System (PS) Block consisting of:
• Quad-core ARM Cortex-A53, Dual-core ARM Cortex-R5, Mali-400 GPU
• 1 bank of DDR4-2400 SDRAM, 1GB x72, 8GB total + ECC
• Removable microSD Flash memory
• wo Quad SPI Flash memory, up to 2Gb each
• wo USB ports to VPX P1
• Programmable Logic (PL) block consisting of:
• 600k logic cells (ZU9EG) or 747k logic cells (ZU15EG)
• 4-lanes of HSSIO on the PS block that can be configured as either:
• Dedicated 4 lane PCI-Express Gen 2 interface on the OpenVPX Data Plane
• 3 lanes on the OpenVPX Expansion Plane and 1 lane to an on board SSD drive chip
• 1 lane of PCIe on the Data Plane, 2 lanes on the Expansion Plane and 1 lane to the mSA A socket
• wo OpenVPX 1000Base-X Control Plane interfaces to VPX P1
• 2 Serial COM port interfaces to VPX P1
• Voltage and temperature monitoring
• Air-cooled and conduction-cooled configurations
1.2 References & Specifications
ANSI/VI A 46.0 VPX Baseline Standard, October 2007, VI A, ISBN 1-885731-44-2
ANSI/VI A 46.4 PCI Express® on the VPX Fabric Connector, July 2010, VI A, Draft 0.15
ANSI/VI A 46.6 Gigabit Ethernet Control Plane on VPX, September 2010, VI A, Draft 0.7
ANSI/VI A 46.9 PMC/XMC Rear I/ Fabric Signal Mapping on 3U and 6U VPX Modules Standard,
November 2010, VI A, ISBN 1-885731-63-9
ANSI/VI A 48.2 Mechanical Specifications for Microcomputers Using REDI
Conduction Cooling Applied to VITA VPX, July 2010, VI A, ISBN 1-885731-60-4
ANSI/VI A 57.1 FPGA Mezzanine Card (FMC) Standard, July 2008, VI A, ISBN 1-885731-49-3
ANSI/VI A 65 penVPX™ System Specification, June 2010, VI A, ISBN 1-885731-58-2
ANSI/VI A 57.4 FPGA Mezzanine Card Plus(FMC+) Standard, March 2016, VI A, Draft
Table 1 : References (continued on next page)
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ANSI/VI A 66.0 ptical Interconnect on VPX - Base Standard, July 2016, VI A, ISBN 1-885731-90-6
ANSI/VI A 66.4 ptical Interconnect n VPX – Half Width MT Variant, April 2016, VI A, ISBN
1-885731-88-4
Table 1 : References
1.3 Order Code
ADM-VPX3-9Z2/z-2(c)(o)
Name Symbol Configurations
Zynq Ultrascale+™ device z 15EG = ZU15EG , 9EG = ZU9EG (Contact factory for details)
Cooling c blank = air cooled commercial /AC1 = air cooled industrial
/CC1 = conduction cooled industrial
Optics o blank= No optics fitted ,
/O = V66.4 Optics fitted
Table 2 : Build Options
Not all combinations are available. Please check with Alpha Data sales for details.
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2 Installation
2.1 Handling Instructions
he components on this board can be damaged by electrostatic discharge (ESD). o prevent damage, observe
ESD precautions:
- Always wear a wrist-strap when handling the card
- Hold the board by the edges
- Avoid touching any components
- Store in ESD safe bag.
2.2 Hardware Installation
2.2.1 System Requirements
he ADM-VPX3-9Z2 is a 3U OpenVPX compliant FPGA card with FMC front IO interface.
Alpha Data offers a Rear ransition Module (R M) that breaks out all P2 IO and P1 control lanes (Part number:
ADM-VPX3-9Z2-R M).
2.2.2 Cooling Requirements
he power dissipation of the board is highly dependent on the FPGA application. A power estimator spreadsheet
is available on request from Alpha Data. his should be used in conjunction with Xilinx power estimation tools to
determine the approximate current requirements for each power rail.
he board is supplied with a passive air cooled or conduction cooled heatsink according to the order number
given at time of purchase. It is the users responsibility to ensure sufficient airflow for air cooled applications and
appropriate metalwork for conduction cooled applications.
he board features system monitoring that measures the board and FPGA temperature. It also includes a
self-protection mechanism that will clear the target FPGA configuration if an over-temperature condition is
detected.
See Section System Monitoring for health monitoring details.
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Figure 1 : ADM-VPX3-9Z2 Air Cooled
2.3 Software Installation
Please refer to the Reference Designs on the Alpha Data Download Site. Example projects for configuring the
Zynq Ultrascale+ MPSOC device and example software for running on the ARM CPUs can be downloaded from
there.
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3 Functional Description
3.1 Overview
Figure 2 : ADM-VPX3-9Z2 Block Diagram
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3.1.1 Switc Definitions
here are two push-button reset switches on the board. heir functions are detailed below.
Switch Ref. Function ON State Off State
SW1 Hardware
Reset Hardware Reset (complete restart) Normal Operation
SW2 Software Reset Software Reset (warm reset) Normal Operation
Table 3 : Reset Switc Definitions
here are two sets of eight DIP switches placed on the bottom of the board. heir functions are described below.
Note:
All switches are OFF by default. Factory Configuration switch must be in the OFF position for normal
operation.
Switch Ref. Function ON State Off State
SW3-1 Spare (to FPGA
pin AM14) User defined User defined
SW3-2 Internal
Oscillator Use VPX REFCLK Use Internal Oscillator source
SW3-3 Internal SA A
SSD Enable Internal SSD is connected to PS HSSIO lane 1 PCIe lane (1) is connected to PS HSSIO lane 1
SW3-4 Flash Boot
Inhibit arget FPGA is not configured from onboard flash memory. arget FPGA is configured from on- board flash memory.
SW3-5 VPX J AG Connect J AG chain to P0 Isolate J AG chain from P0
SW3-6 HSSIO_MUX_
SELEC A FPGA MG Bank 129 routed to FMC+ Socket FPGA MG Bank 129 connected to V66.4 Fibre
SW3-7 Factory
Configuration - Normal Operation
SW3-8 HSSIO_MUX_
SELEC B FPGA MG Bank 130 routed to FMC+ Socket FPGA MG Bank 130 connected to VPX P1
Table 4 : VPX Control Switc Definitions (SW3)
Switch Ref. Function ON State Off State
SW4-(4:1) PS_MODE(3:0) PS Boot Mode - see section Boot Modes
SW4-5 PS_MUX_SEL0 PS HSSIO lane 0 connected to PCIe
(0) PS HSSIO lane 0 connected to VPX P1
SW4-6 PS_MUX_SEL1 PS HSSIO lanes (2:1) connected to
PCIe(2:1) PS HSSIO lanes (2:1) connected to VPX P1
SW4-7 nSD_EMMC SD Card enabled eMMC device enabled
SW4-8 SD_WP SD Card Write Protected (must be
enabled in software) SD Card Write Enabled
Table 5 : Processor Setup Switc Definitions (SW4)
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3.1.2 LED Definitions
here are seven LEDs to provide a visual indication of the board status.
heir locations are shown in Figure 3
D5 D11
D6
D7
D10 D8 D9 D12
D15 D14 D13 D18
D17
D16
D19
D22
D21
Figure 3 : LED Locations
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Comp. Ref. Function ON State Off State
D13 (Green) System Monitor
Status See able 26
D18 (Red) System Monitor
Status See able 26
D15 (Green) FPGA (PL)
Done PL is configured PL is not configured
D19 (Amber) VPX J AG
S A US J AG chain Connected to VPX P0 J AG chain isolated from VPX P0
D14 (Red) Power Fault Power Supply Fault Power Supplies off or within range
D11 (Red) PS Error PS Error Normal Operation
D12 (Green) PS Status Normal Operation PS is in Reset / Error
D16 (Green) SA A PHY Link Established No Link
D17 (Green) SA A DAS Data transfer in progress Disk Idle
Table 6 : Main LED Definitions
A further two sets of three LEDs provide an indication of the status of the two Ethernet interfaces
Comp. Ref. Function ON State Off State
D9 (Green) Ethernet 0
LED0 See able 19
D8 (Green) Ethernet 0
LED1 See able 19
D10 (Green) Ethernet 0
LED2 See able 19
D5 (Green) Ethernet 1
LED0 See able 19
D6 (Green) Ethernet 1
LED1 See able 19
D7 (Green) Ethernet 1
LED2 See able 19
Table 7 : Et ernet LED Definitions
wo Bi-Colour LEDs provide an indication of the status of the two USB interfaces
Comp. Ref. Function ON State Off State
D22 (Bi-Green) USB1 Status Normal Operation Not Operational
D22 (Bi-Amber) USB1 Error Error Normal Operation
D21 (Bi-Green) USB2 Status Normal Operation Not Operational
D21 (Bi-Amber) USB2 Error Error Normal Operation
Table 8 : USB LED Definitions
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3.2 VPX P0 Interface
3.2.1 SYSRESET#
VPX Reset In. his signal is an active low input from the system. When asserted, the PS PCIe interface will be
reset.
he SYSRESE # signal is translated to 1.8V levels and connected to the FPGA at MIO pin J22.
3.2.2 AUXCLK
Auxiliary Clock. his clock is a direct input to the target FPGA. In OpenVPX this clock line is used for 1PPS
synchronization signaling. he prefered signaling standard is LVDS.
AUXCLK_P is connected to FPGA GC pin E22
AUXCLK_N is connected to FPGA GC pin D22
3.2.3 REFCLK
Reference Clock. his clock is an input to the onboard clock distribution and generation system. he 50MHz
defined in OpenVPX can be used to align all system clocks. Alternatively an onboard 25MHz reference can be
generated as shown in VPX Control Switch Definitions (SW3).
3.3 VPX P2 GPIO
3.3.1 LVDS
he GPIO on P2 is compatible with 2.5V signaling such as LVDS and 2.5V single ended signals.
hese signals are routed differentially. he FPGA is protected from inappropriate signal levels by a low
resistance quick switch that clamps at 2.5V in either direction, but can accept up to 3.3V on an input.
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3.4 JTAG Interface
3.4.1 On-board Interface
A J AG boundary scan chain is connected to header J2. his allows the connection of the Xilinx J AG cable.
he scan chain is shown in Figure J AG Boundary Scan Chain:
FPGA
XCZUxxEG
FFVB1156
FMC+
I/F
PRESENT#
VREF (3.3V)
Buffer
3.3V
En#
FMC_TDI
FMC_TDO
HDR_TDI
HDR_TDO
Buffer
3.3V
En#
VPX
Con
(P0)
Header
J2
VPX_TDI
VPX_TDO
VPX_ TAG_EN# SW3-5
Figure 4 : JTAG Boundary Scan C ain
If the boundary scan chain is connected to the interface at the VPX backplane (SW3-5 is ON), header J2 should
not be used.
3.4.2 VPX Interface
he J AG interface on the VPX backplane is normally unused. When SW3-5 is OFF (default), all J AG signals to
P0 are left floating.
he J AG interface can be connected to the VPX Backplane (through level-translators) by switching SW3-5 ON.
3.4.3 JTAG Voltages
he on-board J AG scan chain uses 3.3V. he Vcc supply provided on J2 to the J AG cable is +3.3V and is
protected by a poly fuse rated at 350mA.
he J AG signals at the VPX interface use 3.3V signal levels and are connected through buffers to the on-board
scan chain.
he J AG signals at the FMC interface also use 3.3V signal levels and are connected through buffers to FMC
boards scan chain.
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3.5 Clocks
he ADM-VPX3-9Z2 board provides a wide variety of clocking options. In addition to the clocks routed from the
FMC+ connector, the board has 2 user-programmable clock generators. hese clocks can be combined with the
FPGA's internal PLLs to suit a wide variety of communication protocols.
A complete overview of the clock routing on the ADM-VPX3-9Z2 is given in Clocks. A description of each clock
follows.
Zynq Ultrascale+
MGT/ Banks
MGT130
REFCLK0
REFCLK1
MGT129
REFCLK0
REFCLK1
MGT12
REFCLK0
REFCLK1
MGT230
REFCLK0
REFCLK1
MGT229
REFCLK0
REFCLK1
MGT22
REFCLK0
REFCLK1
FMC+
Programmable
Clock
Synthesizer
Prog_clk1
Buffer
Prog_clk2
Buffer
VPX
P0
Bank 4
GBTCLK0_M2C
GBTCLK1_M2C
25 MHz
Oscillator
PS_505
REFCLK2
REFCLK3
REFCLK0
REFCLK1
Bank 64
Bank 67
Bank 47
100MHz
Buffer
VPXAUXCLK
VPXREFCLK
REFCLK100M
VPXSPARECLK
PROGCLK1
PROGCLK2
GBTCLK2_M2C
GBTCLK3_M2C
GBTCLK4_M2C
GBTCLK5_M2C
FABRIC_CLK
Figure 5 : Clocks
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3.5.1 IO Delay Reference Clock (FABRIC_CLK)
he fixed reference clock FABRIC_CLK is a differential LVDS signal.
FABRIC_CLK is used as the reference clock for the IO delay control block (IDELAYC RL).
Signal Frequency arget FPGA Input IO Standard "P" pin "N" pin
FABRIC_CLK 300 MHz IO BANK 47 LVDS G21 F21
Table 9 : DDR REFCLK Connections
3.5.2 Fixed 100MHz Reference clock REFCLK100M
A fixed 100MHz reference clock is available on the board.
Signal Frequency arget FPGA Input IO
Standard "P" pin
REFCLK100M[0] 100 MHz PS_505_MG REFCLK_0 LVDS AA27
REFCLK100M[1] 100 MHz IO BANK 48 LVDS E17
REFCLK100M[2] 100 MHz MG REFCLK1_230 LVDS B10
REFCLK100M[3] 100 MHz MG REFCLK1_128 LVDS N27
Table 10 : REFCLK100M Connections
3.5.3 Programmable Clocks (PROGCLK1 and PROGCLK2)
here are two programable clock sources that are forwarded throughout the FPGA. hese clocks can be
programmed via the avr2util utility contained within the Alpha Data ADM-VPX3-9Z2 SDK. PROGCLK1 and
PROGCLK2 are generated by a dedicated programmable clock generator IC and offer extremely high frequency
resolutions (1ppm increments).
Signal Frequency arget FPGA Input IO Standard "P" pin "N" pin
PROGCLK1[0] 5 - 400 MHz PS_505_MG REFCLK_1 LVDS W27 W28
PROGCLK1[1] 5 - 400 MHz IO BANK 67 LVDS R10 R9
PROGCLK1[2] 5 - 400 MHz MG REFCLK1_228 LVDS J8 J7
PROGCLK1[3] 5 - 400 MHz MG REFCLK1_129 LVDS J27 J28
Table 11 : PROGCLK1 Connections
Note: PROGCLK1[3:0] are all buffered copies of the same clock signal.
Signal Frequency arget FPGA Input IO Standard "P" pin "N" pin
PROGCLK2[0] 5 - 400 MHz IO BANK 48 LVDS E19 D19
PROGCLK2[1] 5 - 400 MHz IO BANK 64 LVDS AK8 AK7
PROGCLK2[2] 5 - 400 MHz MG REFCLK1_130 LVDS E27 E28
PROGCLK2[3] 5 - 400 MHz MG REFCLK1_229 LVDS E8 E7
Table 12 : PROGCLK2 Connections
Note: PROGCLK2[3:0] are all buffered copies of the same clock signal.
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3.5.4 Module to Carrier Global Clocks (CLK_M2C)
A connected FMC+ board can generate a number of differential Global clocks (as per the FMC standard). hey
each connect to an global clock input on the FPGA.
Signal Frequency FPGA Input IO Standard "P" pin "N" pin
CLK_M2C_0 Variable Bank 66 LVDS Y5 AA5
CLK_M2C_1 Variable Bank 66 LVDS Y4 Y3
CLK_M2C_2 Variable Bank 65 LVDS AF6 AG6
CLK_M2C_3 Variable Bank 65 LVDS AE7 AF7
Table 13 : CLK_M2C Connections
3.5.5 Module to Carrier MGTREF Clocks (GBTCLK_M2C)
A connected FMC board can generate a number of differential MG Reference clocks (as per the FMC standard)
. hey each connect to an MG REFCLK input on the FPGA.
Signal Frequency FPGA Input IO Standard "P" pin "N" pin
GB CLK_0_M2C Variable MG REFCLK_228 LVDS L8 L7
GB CLK_1_M2C Variable MG REFCLK_229 LVDS G8 G7
GB CLK_2_M2C Variable MG REFCLK_230 LVDS C8 C7
GB CLK_3_M2C Variable MG REFCLK_128 LVDS R27 R28
GB CLK_4_M2C Variable MG REFCLK_129 LVDS L27 L28
GB CLK_5_M2C Variable MG REFCLK_130 LVDS G27 G28
Table 14 : GCLK_M2C Connections
3.5.6 PS_REFCLK
he PS reference clock is an independent 50.0MHz reference clock. his is the master clock of the PS side of
the MPSoC.
Signal Frequency FPGA Input IO Standard pin
PS_REFCLK 50MHz PS_REF_CLK (Bank
503) LVCMOS18 U24
Table 15 : PS_REFCLK Connection
3.5.7 VIDEO_CLK
An optional independent 27.0MHz reference clock is provided. his can be used to clock the video sections in
the PS side of the MPSoC.
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Signal Frequency FPGA Input IO Standard pin
VIDEO_REFCLK 27MHz PS_MIO27 (Bank
501) LVCMOS18 M21
Table 16 : VIDEO_REFCLK Connection
3.5.8 USB_REFCLK24M
he USB PHY and hub are provided with an independent 24.0MHz reference clock. his clock is asynchronous
to the clocks generated by the Si5338B and is not connected to the Zynq SoC.
3.5.9 ETH_CLK25M
he Ethernet PHYs are provided with an independant 25.0MHz reference clock. his clock is asynchronous to
the clocks generated by the Si5338B and is not connected to the Zynq SoC..
3.6 Resets
he Zynq PS can be reset via the two push button switches, SW1 and SW2.
Switch Reset ype Effect
SW1 Power on Reset
(PS_POR_B pin) Clears all logic. Mode pins sampled (i.e. reconfigures hardware). Reboots MPSoC.
SW2 Soft Reset
(PS_SRS _B pin) Same as Power on Reset - but does not sample Mode pins (hardware configuration unchanged).
Table 17 : Reset Switc es
3.7 Zynq PS Block
3.7.1 Boot Modes
PS_MODE3
(SW4-4) PS_MODE2 (SW4-3) PS_MODE1 (SW4-2) PS_MODE0 (SW4-1) Boot Mode
ON ON ON ON J AG
ON ON ON OFF Quad SPI (24 bit addressing)
ON ON OFF ON Quad SPI (32 bit addressing)
ON ON OFF OFF SD Flash - SD 2.0
ON ON ON ON eMMC v4.5 at 1.8V
Table 18 : Boot Mode Selection
Note: all other possible switch settings are reserved / invalid.
3.7.2 PS Memory Interfaces
he memory devices attached to the PS side of the MPSoC are outlined below.
3.7.2.1 Quad SPI Flas Memory
he ADM-VPX3-9Z2 has two Quad SPI Flash devices, up to 2Gb each. hey can be interfaced seperately in x1,
x2,x4 modes or together in x8 mode.
Page 14 Functional Description
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