ALPHA PROJECT ALPHA SoM Series User manual

©2023 Alpha Project Co., Ltd.
Cove
Rev 1.0
Hardware Manual
αSMARC-RZ/G2E
RZ/G2E System on Module
ALPHA SoM Series

Alpha SoM Series αSMARC-RZ/G2E
MS104-FPGA/CⅢ
αSMARC-RZ/G2E Hardware Manual
©2023 Alpha Project Co., Ltd.
https://www.apnet.co.jp
Important Information and Disclaimer
Thank you for purchasing an αSMARC-RZ/G2E.
Please read this manual first in order to use this module correctly.
We appreciate your continued patronage of our products.
Product Includes
This module consists of the following components. Check the contents of the package, and if anything is missing,
contact the vendor from which you purchased this product.
■ Please understand that the contents and specifications of this module are subject to change without warning.
Handling Precautions
Warranty
■During the warranty period, if the product malfunctions during normal use while following precautions described in this manual, it will be
covered by the warranty.
■Regardless of whether or not the product is under warranty, Alpha Project Co., Ltd. will not compensate for any direct or indirect damage
resulting from the operation of this product.
■The warranty covers the main body of the product. The software, manuals, consumables, and packing boxes are not covered by the warranty.
■This warranty is only valid in Japan. We do not accept requests from overseas.
■For details on the product warranty regulations, see the attached warranty document or our website.
●αSMARC-RZ/G2E (with heat sink) x1 ● Manual, warranty information x1
αSMARC-RZ/G2E Product Includes
●General consumer electronic components are used in this product, and it was designed with the intent of using it
for general consumer electronic equipment. Do not use this product in applications involving human life or accidents,
or applications which may cause significant property damage, such as space, aviation, medical, nuclear power,
transportation, traffic, and various safety devices.
●
Do not use this product in environments with extremely hot or cold temperatures or strong vibrations.
●
Do not use this product in water, or environments with high humidity or excessive oil.
●
Do not use this product in environments with corrosive gas, flammable gas, etc.
●
Do not turn on the power when the front of the circuit board is wet or is contacting metal.
●
Do not apply power that exceeds the rating.
■Please understand that operation cannot be guaranteed in environments with excessive noise.
■
Beware that using the product in environments with continuous vibration (in vehicles, etc.) or impacts can shorten the product life or cause it
to malfunction.
■Turn off the power immediately if the product emits smoke, flame, or abnormal heat.
■Beware that using this module in conditions that exceed the range of its specifications can cause it to malfunction.
■
Among the products and technologies listed in this manual, an export license based on the Foreign Exchange and Foreign Trade Law is
required when exporting or taking out of Japan any items that fall under the regulated goods (technologies) stipulated in said law.
■
Alpha Project Co., Ltd. owns the copyright to the manual that comes with this product. It is prohibited to divert, post, transfer, or distribute
this manual without permission.

Alpha SoM Series αSMARC-RZ/G2E
MS104-FPGA/CⅢ
αSMARC-RZ/G2E Hardware Manual
©2023 Alpha Project Co., Ltd.
https://www.apnet.co.jp
Reference Documents
Device and SMARC standard documents are published on the websites of various companies and organizations.
Consult them along with this manual.
■RZ/G2E Group / Renesas Electronics
■SMARC STANDARD (SGeT.ORG)
-SMARC Hardware Specification 2.1.1
-SMARC Design Guide Ver. 2.0
*About reference documents
- Documents and website URLs of various companies are subject to change without notice.
- Please direct inquiries about devices to the contact point of each device manufacturer.
Trademarks / License
■SMARC and the SMARC logo are trademarks of SGeT (Standardization Group for Embedded Technologies).
■RZ/G2E is a registered trademark, trademark, or product name of Renesas Electronics Corporation.
■Arm®and Cortex®are registered trademarks ofARM Limited (or its subsidiaries) in EU countries and other countries.
■SD, SDHC, SDXC, microSD, microSDHC, and microSDXC are trademarks of SD-3C LLC.
■Names of other companies and products are registered trademarks or trademarks of each company.
■Alpha Project Co., Ltd. is a member of SGeT (Standardization Group for Embedded Technologies).
■Alpha Project Co., Ltd. is a member of SDA (SD Association).

Alpha SoM Series αSMARC-RZ/G2E
αSMARC-RZ/G2E Hardware Manual
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Contents
1. Overview 1
1.1 Product Overview ...........................................................................................1
1.2 Functions and Features....................................................................................1
1.3 About SMARC................................................................................................2
1.4 About Linux BSP ............................................................................................2
1.5 Specifications Overview.................................................................................3
1.6 External Specifications ...................................................................................4
1.7 Circuit Configuration......................................................................................5
1.8 Address Map ...................................................................................................7
2. Functions 8
2.1 CPU.................................................................................................................8
2.2 MEMORY.......................................................................................................8
2.3 Other................................................................................................................9
2.4 SMARC Interface .........................................................................................10
2.5 Settings..........................................................................................................16
2.6 LED Indicator ...............................................................................................17
2.7 UART Connector ..........................................................................................18
2.8 JTAG Connector............................................................................................19
2.9 Power Supply Connector ..............................................................................20
3. Interface Function Details 21
3.1 LVDS LCD....................................................................................................21
3.2 Gigabit Ethernet............................................................................................22
3.3 CAMERA......................................................................................................23
3.4 I2C.................................................................................................................24
3.5 SDIO .............................................................................................................25
3.6 AUDIO I2S ...................................................................................................26
3.7 SPI.................................................................................................................27
3.8 USB 2.0.........................................................................................................28
3.9 USB 3.0.........................................................................................................29
3.10 Serial Port....................................................................................................30
3.11 CAN BUS....................................................................................................31
3.12 PCI Express.................................................................................................32
3.13 GPIO ...........................................................................................................33

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4. Power Supply and System Control 34
4.1 Power Supply................................................................................................34
4.2 System Control..............................................................................................34
5. Technical Data 38
5.1 External Dimensions.....................................................................................38
5.2 Compatible Connectors.................................................................................40
5.3 Designing the Carrier Board.........................................................................41
5.4 Heat Dissipation Measures............................................................................42
6. Related Products 43
6.1 SMARC2.1 Compliant Carrier Board...........................................................43
6.2 αSMARC-RZ/G2E Development Kit...........................................................43
6.3 Card Edge Connector....................................................................................43
7. Product Support Information 44
8. Information on Engineering Services 45

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1. Overview
1.1 Product Overview
αSMARC-RZ/G2E comes equipped with Renesas Electronics RZ/G2E MPU and is a SoM (System on Module) for mass production that
conforms to the SMARC2.1 standard.
RZ/G2E is based on the ARM Cortex®-A53 dual core, has a built-in 3D graphics engine PowerVR GE8300, and supports Full HD video
encoding/decoding.
Its peripheral functions include high-speed interfaces such as USB 3.0, PCI Express, Gigabit Ethernet, and many others such as LCD and
AUDIO, so it is ideal for applications such as HMI for industrial use.
Its form factor conforms to the standard SMARC 2.1, and its high compatibility and extensibility make it possible to build flexible and scalable
systems.
1.2 Functions and Features
■RZ/G2E Arm® Cortex®-A53 Dual Core 1.2 GHz equipped
The ARM v8 architecture 64-bit compatible processor delivers high performance with low power consumption.
■Supports Full HD video encoding/decoding
Supports H.264/H.265 Full HD (1920 x 1080 60 fps) encoding and decoding.
■eMMC, DDR3-L memory equipped
Comes equipped with eMMC 8GByte for program memory and DDR3L-SDRAM 1 GByte for data memory.
■Highly extensible interface
In addition to high-speed communication interfaces such as USB3.0, PCI Express, and Gigabit Ethernet, it has many peripheral functions such
as LCD (LVDS) x 2 channels, AUDIO, camera input (MIPI CSI-2), and CAN.
■Compliant with SMARC 2.1 standard
The module’s high compatibility and extensibility make it possible to build a flexible and scalable system.
Very compact size, just 82 mm x 50 mm.
■Supports wide temperature range
The operating temperature is -20° C to +60° C.
■Uses Linux as the standard OS
The Verified Linux Package (Ultra Long Term Support Linux) is used to reduce the burden of software development and maintenance.
*The Verified Linux Package is provided by Renesas Electronics. Visit the Renesas Electronics website for details.
■SMARC standard compliant carrier board is provided
Acarrier board and Linux BSPare provided that allow you to start software development immediately.
The circuit diagram of the carrier board has been opened to the public, so it can be used as a reference.

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1.3 About SMARC
SMARC (Smart Mobility ARChitecture) is a standard for small form factor SoM (System on Module).
Two module sizes are defined, 82 mm x 50 mm and 82 mm x 80 mm, and for signal connections we use 314-pin edge terminals mating with 0.5
mm pitch connectors.
Using SMARC SoM eliminates the need for complicated design around the CPU, which enables the user to focus on designing application-
specific carrier boards, so low development costs and short time to market can be achieved.
The SMARC standard SoM and carrier board are compatible, so scalable systems can be built according to the application.
For more information on SMARC, see the SGeT (Standardization Group for Embedded Technology) home page.
SMARC Hardware Specification 2.1.1 https://www.sget.org/standards/smarc/
1.4 About Linux BSP
This module uses Linux as the standard OS.
LinuxBSP (Linux Board Support Package) is included in the development kit. For details, see our website.

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1.5 Specifications Overview
αSMARC-RZ/G2E Specifications
Function
Specifications
Form Factor
SMARC2.1 Short Size
CPU
R8A774C0HA01BG (552Pin FCBGA)
Arm®Cortex®-A53 Dual Core 1.2 GHz
ROM
eMMC 8 GByte
SPI FLASH 4 MByte
EEPROM 2 KByte
RAM
DDR3L-1856 (928 MHz) 1 GByte / 32 bit data-bus
SMARC Interface
(314 pin edge terminal)
Gigabit Ethernet
USB 3.0 SuperSpeed OTG
USB 2.0 High-Speed Host/Function
PCI Express Rev 2.0 (1 Lane)
SD-CARD
LCD (LVDS)
CAMERA(MIPI CSI-2)
UART
CAN (FD Support)
AUDIO I2S
SPI
I2C
GPIO
×1
×1
×2
×1
×1
×2
×1
×3
×2
×1
×1
×3
×14
RTC
Maximum daily difference ±2 seconds
Backup with external power supply
LED
Monitor LED ×1
Power LED ×1
UART
UART Connector UART (TTL) 1 port
JTAG
JTAG Connector CoreSight half pitch 10 pin (5p × 2 rows)
Heat Sink
Dedicated product installed
Power Supply
DC 5.0 V ±5%
Current Consumption
Max 10 W
Use Environment Conditions
Temperature: -20 to +60˚ C (no condensation)
Dimensions
82 mm (W) × 50 mm (D)
Circuit Board
FR-4 (UL94-V0)
Environmental Support
RoHS directive (2015/863/EU)
Table 1.5-1 Hardware specifications

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1.6 External Specifications
[Parts]
When a heat sink is attached
RZ/G2E
Cortex-A53 Dual 1.2GHz
CN2
JTAG I/F Connecter
CN1
UART Connecter
SW1
MODE SW
CN4
Power Connecter
P1-P156 (Parts side)
S1-S158 (Back side)
SMARC edge terminal
LD1
Monitor
LD2
Power
0224-0000
000C7B-000000
MAC Address
Serial Number
Fig 1.6-1 Appearance

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1.7 Circuit Configuration
Fig 1.7-1 αSMARC-RZ/G2E configuration block diagram
SMARC Edge Contacts (314 pin)
MONITOR LED
RZ/G2E
Cortex-A53 Dual
1.2 GHz
I2C
CN1
JTAG
UART
GPIO
RMII
DU_CLK
MIPI CSI-2
LCD (LVDS) x 2
I2C x 3
I2S
Unimplemented
QSPI
DDR IF
SD/MMC IF
CN2
JTAG
UART
EXTAL
SD
USB 3.0 CLK
PCIe CLK
PCIe CLK
UART x 3
SPI
CAN
1.8 V
1.1 V
2.5 V
1.35 V
3.3 V
5
GPIO x 14
USB 2.0 x 2
USB 3.0
PCIe
Ethernet
CN4
Power supply connector
5 V
1.8 V / 3.3 V
EEPROM
2KByte
RTC
SPI FLASH
4 MByte
DDR3L
1 GByte
eMMC
8 GByte
LEVEL SHIFTER
3.3 V ↔ 1.8 V
SW-REG
ISL8023
SW-REG
ISL8023
PWM-CTRL
ISL68200
REG
ISL80505
SW-REG
ISL8023
GigaEther
PHY
CLK Gen
9FGV0441
RESET
IC
LDO
ISL80505
OSC
OSC
48 MHz
Power
Sequencer

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The main devices and parts used in this module are as follows.
For device specifications, see the website of each device manufacturer.
Product Function
Model / Manufacturer
Specifications
Remarks
CPU
R8A774C0HA01BG / Renesas
ARM Cortex-A53 Dual
eMMC
THGBMJG6C1L / Kioxia
64 Gbit eMMC
*1
DDR3L
MT41K256M16 / Micron
4 Gbit DDR3L Memory
*1
SPI FLASH
MX25L3235E / Macronix
32 Mbit QSPI FLASH
*1
RealTimeClock
S-35390A / ABLIC
RealTimeClock
Ethernet PHY
KSZ9131RNXI / Microchip
Gigabit Ethernet Transceiver
Clock Generator
9FGV0441AKLF / Renesas
PCIe Clock Generator
Power
ISL8023IRTAJZ-T7A / Renesas
SwitchBuck-Reg
Power
ISL68200IRZ-T7A / Renesas
PWM Controller
Power
ISL80505IRAJZ-T7A / Renesas
LowDrop-Reg
Connector Number
Connector Model / Manufacturer
Application
Remarks
CN1
SM4B-SRSS-TB / JST
UART Connecter
CN2
HEADER 10p (5px2) 1.27 mm Pitch
JTAG Connector
CN4
SM05B-SRSS-TB / JST
Power Connecter
*1 Please note that parts may be changed to equivalent products without notice.
Table 1.7-2 Main devices
Table 1.7-3 Connector List

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1.8 Address Map
Address
Area
H’00_00000000
Legacy (DDR0 shadow A) *1
H’01_00000000
Reserved
H’02_00000000
Reserved
H’03_00000000
Reserved
H’04_00000000
H’04_3FFFFFFF
DDR0 Area DDR3L 1 GByte
H’05_40000000
DDR3L Mirror
H’05_00000000
Reserved
H’06_00000000
Reserved
H’07_00000000
Reserved
H’08_00000000
DDR0 Area shadow B
H’09_00000000
Reserved
H’0A_00000000
Reserved
H’0B_00000000
Reserved
H’0C_00000000
DDR0 Area shadow C
H’0D_00000000
Reserved
H’0E_00000000
Reserved
H’0F_00000000
Reserved
H’10_00000000
Reserved
H’11_00000000
Reserved
H’12_00000000
Reserved
H’13_00000000
Reserved
H’14_00000000
Reserved
H’15_00000000
Reserved
H’18_00000000
uTLB (IPMMU slave) ch0
H’1C_00000000
Reserved
H’20_00000000
Reserved
H’30_00000000
Reserved
H’FF_00000000
Reserved
Fig 1.8-1 Address Map
*1 Internal registers are assigned to the Legacy Area.
For details on the address map, see the “RZ/G Series 2nd Generation User's Manual: Hardware”.

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2. Functions
2.1 CPU
This module is equipped with RZ/G2E MPU manufactured by Renesas Electronics.
It is based on theArmV8 architecture 64 bit compatible processorArm® Cortex-A53 dual core, and in addition to advanced graphics functions
such as a 3D graphics engine and video encoder, it also supports high-speed interfaces such as Gigabit Ethernet, USB 3.0, PCI Express, and
MIPI CSI-2.
For detailed functions of RZ/G2E, see the Renesas Electronics product page and device datasheet.
RZ/G2E product page (Renesas Electronics) RZ/G2E microprocessor
2.2 MEMORY
2.2.1 eMMC NAND Flash
This module is equipped with 8 GByte eMMC NAND Flash.
It is connected to the MMC interface (SDHI3) of RZ/G2E and can be used as a boot device.
Bandwidth is up to 400 MB/s in HS400 mode.
2.2.2 DDR3L SDRAM
This module is equipped with 1 GByte DDR3L SDRAM.
It is connected to the RZ/G2E’s External BUS Controller via a 32 bit bus.
The clock has a maximum of 928 MHz (DDR3L-1856), and the bandwidth is up to 7424 MB/s.
2.2.3 SPI FLASH
This module has a 4 MByte SPI FLASH.
It is connected to the RZ/G2E SPI Multi I/O Bus Controller (QSPI0) and can be used as a boot device when updating firmware.

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2.3 Other
2.3.1 RTC
This module is equipped with RTC (Real Time Clock).
It can be backed up from VDD_RTC of the SMARC interface.
Function
Specifications
RTC
S-35390A(ABLIC)
Current consumption: 0.25 uATyp Maximum daily difference ±2 seconds
2.3.2 EEPROM
This module is equipped with 2 KByte EEPROM.
It is used to store parameters such as MAC addresses. The MAC address assigned by our company is written at time of shipment.
2.3.3 I2C Control Device
EEPROM, RTC, Clock Generate, and PWM Controller are connected to RZ/G2E’s I2C interface and can be controlled.
Table 2.3-1 Overview of RTC specifications
SCL2
SDA2
RZ/G2
E
VDD_RTC
SMARC I/F
RTC
S-35390A
SCK
SDA
Fig 2.3-2 I2C control device circuit connection configuration
EEPROM
SCL
SDA
Clock
Generator
9FGV0441A
SCLK
SDATA
DIF0
DIF1
DIF2
PCIE0_CLK
USB3S0_CLK
PCIE_A_REFCK
VDD
VDD_3V3
25 MHz
Device Code = 0110
Device Code = 1010
Device Code = 1101
PWM
Controller
ISL68200
SCL
SDA
VDD
Device Code = 1000/1100/1110/1111

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2.4 SMARC Interface
2.4.1 Interface Terminal
This module complies with SMARC standard 2.1.
The connection with the carrier board of the SMARC standard module is an edge terminal, and the shape is suitable for MXM 3.0 connectors.
The assignment of pin numbers is unique to the SMARC standard, with P1-P156 arranged on the front side and S1-S158 arranged on the back
side, for a total of 314 pins.
2.4.2 Supported Functions
The SMARC standard defines the level of support required for each function, and they are categorized as follows.
“ shall”
Must
“should”
Recommended
“May”
Not often used option
“Alternate”
Options shared with another use
This module supports the following functions and signals.
Function
Channel
SMARC
requirement
αSMARC-RZ/G2E
Remarks
LVDS LCD
LVDS0
Should
O
24 bit Single or Dual
LVDS1
May
O
HDMI
HDMI
Should
--
Display Port
DP0
May
--
DP1
May
--
Camera
CSI0
May
--
CSI1
Should
O
SDIO
SDIO
Should
O
SPI
SPI0
Should
O
eSPI1
Should
--
Audio
I2S0
Should
O
HDA
Should
--
P1
P74
P75
P156
S158
S76
S75
S1
Module front (parts side)
Module rear (back side)
Fig 2.4-1 SMARC edge terminal layout
Table 2.4-2 Function list
o: Supported -- : Not supported

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I2C
Power Management
Shall
O
General Purpose
Shall
O
CAMERA
May
O
Shared with General Purpose
LCD
May
O
Serial Ports
SER0
Shall
O
SER1
Shall
O
SER2
Should
O
SER3
Should
--
CAN Bus
CAN0
May
O
CAN1
May
O
USB
USB0
Shall
O
Function (exclusive with USB1)
USB1
Shall
O
Host (exclusive with USB0)
USB2
May
--
(Super Speed)
USB2 SS
May
--
USB3
May
O
OTG
(Super Speed)
USB3 SS
May
O
OTG
USB4
May
--
USB5
May
--
PCI Express
PCIe_A
Should
O
PCIe_B
May
--
PCIe_C
May
--
PCIe_D
May
--
Serial ATA
SATA
Should
--
Gigabit Ethernet
GBE0
Should
O
GBE1
May
--
Watchdog
WDT Out
Should
--
GPIO
GPIO[0:11]
Shall
O
GPIO[12:13]
Should
O
Management
CARRIER_PWR_ON
Shall
O
VIN_PWR_BAD#
Shall
O
CARRIR_STBY#
Should
--
POWER_BTN#
Should
O
RESET_IN#
Should
O
RESET_OUT#
Should
O
CHARGING#
Should
--
CHARGE_PRSNT#
Should
--
BATLOW#
Should
--
SLEEP#
Should
--
SMB_ALERT#
Should
--
TEST#
Should
O
BootSelect
BOOT_SEL[0:2]#
Shall
O
ForceRecov
FORCE_RECOV#
Should
O
RTC
VDD_RTC
Should
O
POWER
VDD_IN
Shall
O
GND
Shall
O

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2.4.3 Signal Assignment
The signal assignments for the SMARC interface are shown in the following table.
-“N.C” in the signal name indicates Not Connected.
-“P.U” and “P.D” indicate pull-up or pull-down within SoM.
-“O.D” indicates open drain.
-“x” in voltage indicates it conforms to the standard of each interface.
-VDD_IO can be set to 1.8 V (standard) or 3.3 V. For details, see “2.5.2 VDD_IO Settings”.
For definitions of each signal in the SMARC standard, see the SMARC standard specification.
SMARC Hardware Specification 2.1.1 https://www.sget.org/standards/smarc/
No.
Signal Name
Input/
Output
Voltage
Remarks
No.
Signal Name
Input/
Output
Voltage
Remarks
P1
N.C
S1
I2C_CAM1_CK
Out
VDD_IO
P.U 2.2k
P2
GND
GND
S2
I2C_CAM1_DAT
Out
VDD_IO
P.U 2.2k
P3
CSI1_CK+
In
x
S3
GND
GND
P4
CSI1_CK-
In
x
S4
N.C
P5
N.C
S5
N.C
P6
N.C
S6
CAM_MCK
Out
VDD_IO
P7
CSI1_RX0+
In
x
S7
N.C
P8
CSI1_RX0-
In
x
S8
N.C
P9
GND
GND
S9
N.C
P10
CSI1_RX1+
In
x
S10
GND
GND
P11
CSI1_RX1-
In
x
S11
N.C
P12
GND
GND
S12
N.C
P13
N.C
S13
GND
GND
P14
N.C
S14
N.C
P15
GND
GND
S15
N.C
P16
N.C
S16
GND
GND
P17
N.C
S17
N.C
P18
GND
GND
S18
N.C
P19
GBE0_MDI3-
I/O
x
S19
N.C
P20
GBE0_MDI3+
I/O
x
S20
N.C
P21
GBE0_LINK100#
Out
3.3 V O.D
S21
N.C
P22
GBE0_LINK1000#
Out
3.3 V O.D
S22
N.C
P23
GBE0_MDI2-
I/O
x
S23
N.C
P24
GBE0_MDI2+
I/O
x
S24
N.C
P25
GBE0_LINK_ACT#
Out
3.3 V O.D
S25
GND
GND
P26
GBE0_MDI1-
I/O
x
S26
N.C
P27
GBE0_MDI1+
I/O
x
S27
N.C
P28
GBE0_CTREF
Out
x
S28
N.C
P29
GBE0_MDI0-
I/O
x
S29
N.C
P30
GBE0_MDI0+
I/O
x
S30
N.C
P31
N.C
In
VDD_IO
P.U 10K
S31
N.C
P32
GND
GND
S32
N.C
P33
SDIO_WP
In
3.3 V
P.U 10K
S33
N.C
P34
SDIO_CMD
I/O
3.3 V/1.8 V
P.U 47K
S34
GND
GND
P35
SDIO_CD#
In
3.3 V
P.U 10K
S35
N.C
P36
SDIO_CK
Out
3.3 V/1.8 V
P.U 47K
S36
N.C
Table 2.4-3 SMARC interface signal assignment

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P37
SDIO_PWR_EN
Out
3.3 V
P.U 47k
S37
USB3_VBUS_DET
In
5 V
P.D 100k
P38
GND
GND
S38
AUDIO_MCK
Out
VDD_IO
P39
SDIO_D0
I/O
3.3 V/1.8 V
P.U 47k
S39
I2S0_LRCK
I/O
VDD_IO
P40
SDIO_D1
I/O
3.3 V/1.8 V
P.U 47k
S40
I2S0_SDOUT
Out
VDD_IO
P41
SDIO_D2
I/O
3.3 V/1.8 V
P.U 47k
S41
I2S0_SDIN
In
VDD_IO
P42
SDIO_D3
I/O
3.3 V/1.8 V
P.U 47k
S42
I2S0_CK
I/O
VDD_IO
P43
SPI0_CS0#
Out
VDD_IO
S43
N.C
P44
SPI0_CK
Out
VDD_IO
S44
N.C
P45
SPI0_DIN
In
VDD_IO
S45
N.C
P46
SPI0_DO
Out
VDD_IO
S46
N.C
P47
GND
GND
S47
GND
GND
P48
N.C
S48
I2C_GP_CK
Out
VDD_IO
P.U 2.2k
P49
N.C
S49
I2C_GP_DAT
I/O
VDD_IO
P.U 2.2k
P50
GND
GND
S50
N.C
P51
N.C
S51
N.C
P52
N.C
S52
N.C
P53
GND
GND
S53
N.C
P54
N.C
S54
N.C
P55
N.C
S55
N.C
3.3 V
P.U 10k
P56
N.C
S56
N.C
P57
N.C
S57
N.C
P58
N.C
S58
N.C
P59
GND
GND
S59
N.C
P60
USB0+
I/O
x
S60
N.C
P61
USB0-
I/O
x
S61
GND
GND
P62
USB0_EN_OC#
I/O
3.3 V O.D
P.U 10k
S62
USB3_SSTX+
Out
x
P63
USB0_VBUS_DET
In
5 V
P.D 100k
S63
USB3_SSTX-
Out
x
P64
N.C
S64
GND
GND
P65
USB1+
I/O
x
S65
USB3_SSRX+
In
x
P66
USB1-
I/O
x
S66
USB3_SSRX-
In
x
P67
USB1_EN_OC#
I/O
3.3 V O.D
P.U 10k
S67
GND
GND
P68
GND
GND
S68
USB3+
I/O
x
P69
N.C
S69
USB3-
I/O
x
P70
N.C
S70
GND
GND
P71
N.C
3.3 V
P.U 10k
S71
N.C
P72
N.C
S72
N.C
P73
N.C
S73
GND
GND
P74
USB3_EN_OC#
I/O
3.3 V O.D
P.U 10k
S74
N.C
P75
PCIE_A_RST#
Out
3.3 V
P.U 47k
S75
N.C
P76
N.C
3.3 V
P.U 10k
S76
N.C
P77
N.C
S77
N.C
P78
N.C
S78
N.C
P79
GND
GND
S79
N.C
P80
N.C
S80
GND
GND
P81
N.C
S81
N.C
P82
GND
GND
S82
N.C
P83
PCIE_A_REFCK+
Out
x
S83
GND
GND
P84
PCIE_A_REFCK-
Out
x
S84
N.C
P85
GND
GND
S85
N.C
P86
PCIE_A_RX+
In
x
S86
GND
GND
P87
PCIE_A_RX-
In
x
S87
N.C
P88
GND
GND
S88
N.C
P89
PCIE_A_TX+
Out
x
S89
GND
GND
P90
PCIE_A_TX-
Out
x
S90
N.C

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P91
GND
GND
S91
N.C
P92
N.C
S92
GND
GND
P93
N.C
S93
N.C
P94
GND
GND
S94
N.C
P95
N.C
S95
N.C
P96
N.C
S96
N.C
P97
GND
GND
S97
N.C
P98
N.C
S98
N.C
P99
N.C
S99
N.C
P100
GND
GND
S100
N.C
P101
N.C
S101
GND
GND
P102
N.C
S102
N.C
Out
P103
GND
GND
S103
N.C
Out
P104
N.C
S104
USB3_OTG_ID
In
3.3 V
P105
N.C
VDD_IO
P.U 100k
S105
N.C
P106
N.C
VDD_IO
P.U 100k
S106
N.C
P107
N.C
S107
LCD1_BKLT_EN
Out
VDD_IO
P.D 470k
P108
GPIO0
I/O
VDD_IO
P.U 470k
S108
LVDS1_CK+
Out
x
P109
GPIO1
I/O
VDD_IO
P.U 470k
S109
LVDS1_CK-
Out
x
P110
GPIO2
I/O
VDD_IO
P.U 470k
S110
GND
GND
P111
GPIO3
I/O
VDD_IO
P.U 470k
S111
LVDS1_0+
Out
x
P112
GPIO4
I/O
VDD_IO
P.U 470k
S112
LVDS1_0-
Out
x
P113
GPIO5
I/O
VDD_IO
P.U 470k
S113
N.C
P114
GPIO6
I/O
VDD_IO
P.U 470k
S114
LVDS1_1+
Out
x
P115
GPIO7
I/O
VDD_IO
P.U 470k
S115
LVDS1_1-
Out
x
P116
GPIO8
I/O
VDD_IO
P.U 470k
S116
LCD1_VDD_EN
Out
VDD_IO
P.D 470k
P117
GPIO9
I/O
VDD_IO
P.U 470k
S117
LVDS1_2+
Out
x
P118
GPIO10
I/O
VDD_IO
P.U 470k
S118
LVDS1_2-
Out
x
P119
GPIO11
I/O
VDD_IO
P.U 470k
S119
GND
GND
P120
GND
GND
S120
LVDS1_3+
Out
x
P121
I2C_PM_CK
I/O
VDD_IO
P.U 2.2K
S121
LVDS1_3-
Out
x
P122
I2C_PM_DAT
I/O
VDD_IO
P.U 2.2K
S122
LCD1_BKLT_PWM
Out
VDD_IO
P.D 470k
P123
BOOT_SEL0#
In
VDD_IO
P.U 1.5k
S123
GPIO13
I/O
VDD_IO
P.U 470k
P124
BOOT_SEL1#
In
VDD_IO
P.U 1.5k
S124
GND
GND
P125
BOOT_SEL2#
In
VDD_IO
P.U 1.5k
S125
LVDS0_0+
Out
x
P126
RESET_OUT#
Out
VDD_IO
S126
LVDS0_0-
Out
x
P127
RESET_IN#
In
3.3 V
P.U 10k
S127
LCD0_BKLT_EN
Out
VDD_IO
P.D 470k
P128
POWER_BTN#
In
VDD_IN
P.U 10k
S128
LVDS0_1+
Out
x
P129
SER0_TX
Out
VDD_IO
S129
LVDS0_1-
Out
x
P130
SER0_RX
In
VDD_IO
P.U 100k
S130
GND
GND
P131
SER0_RTS#
Out
VDD_IO
S131
LVDS0_2+
Out
x
P132
SER0_CTS#
In
VDD_IO
P.U 100k
S132
LVDS0_2-
Out
x
P133
GND
GND
S133
LCD0_VDD_EN
Out
VDD_IO
P.D 470k
P134
SER1_TX
Out
VDD_IO
S134
LVDS0_CK+
Out
x
P135
SER1_RX
In
VDD_IO
P.U 100k
S135
LVDS0_CK-
Out
x
P136
SER2_TX
Out
VDD_IO
S136
GND
GND
P137
SER2_RX
In
VDD_IO
P.U 100k
S137
LVDS0_3+
Out
x
P138
SER2_RTS#
Out
VDD_IO
S138
LVDS0_3-
Out
x
P139
SER2_CTS#
In
VDD_IO
S139
I2C_LCD_CK
Out
VDD_IO
P.U 2.2k
P140
N.C
S140
I2C_LCD_DAT
I/O
VDD_IO
P.U 2.2k
P141
N.C
S141
LCD0_BKLT_PWM
Out
VDD_IO
P.D 470k
P142
GND
GND
S142
GPIO12
I/O
VDD_IO
P.U 470k
P143
CAN0_TX
Out
VDD_IO
S143
GND
GND
P144
CAN0_RX
In
VDD_IO
P.U 470k
S144
N.C

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P145
CAN1_TX
Out
VDD_IO
S145
N.C
VDD_IO
P.U 10k
P146
CAN1_RX
In
VDD_IO
P.U 470k
S146
PCIE_WAKE#
In
3.3 V
P.U 10k
P147
VDD_IN
In
4.75 - 5.25 V
S147
VDD_RTC
In
2.0 - 3.25 V
P148
VDD_IN
In
4.75 - 5.25 V
S148
N.C
P149
VDD_IN
In
4.75 - 5.25 V
S149
N.C
P150
VDD_IN
In
4.75 - 5.25 V
S150
VIN_PWR_BAD#
In
VDD_IN
P.U 10k
P151
VDD_IN
In
4.75 - 5.25 V
S151
N.C
P152
VDD_IN
In
4.75 - 5.25 V
S152
N.C
P153
VDD_IN
In
4.75 - 5.25 V
S153
N.C
VDD_IO
P.U 10k
P154
VDD_IN
In
4.75 - 5.25 V
S154
CARRIER_PWR_ON
Out
VDD_IO
P155
VDD_IN
In
4.75 - 5.25 V
S155
FORCE_RECOV#
In
VDD_IO
P.U 10k
P156
VDD_IN
In
4.75 - 5.25 V
S156
N.C
S157
TEST#
In
1.8 V
P.U 1.5k
S158
GND
GND
2.4.4 DC Characteristics
Each signal is compliant with common 1.8 V CMOS or 3.3 V CMOS.
Item
Symbol
Min
Max
UNIT
VDD_IN
Power Supply
VDD_IN
4.75
5.25
V
1.8 V (SDIO)
High-Level Output Voltage
VOH
1.4
V
Low-Level Output Voltage
VOL
0.45
V
High-Level Input Voltage
VIH
1.27
2.1
V
Low-Level Input Voltage
VIL
-0.3
0.58
V
3.3 V
High-Level Output Voltage
VOH
2.4
3.6
V
Low-Level Output Voltage
VOL
0.4
V
High-Level Input Voltage
VIH
2.0
3.6
V
Low-Level Input Voltage
VIL
-0.3
0.4
V
VDDIO (1.8 V or 3.3 V)
High-Level Output Voltage
VOH
VDDIO × 0.65
VDDIO - 0.4
V
Low-Level Output Voltage
VOL
0.4
V
High-Level Input Voltage
VIH
VDDIO × 0.65
VDDIO + 0.3
V
Low-Level Input Voltage
VIL
0
VDDIO × 0.35
V
Table 2.4-4 SMARC interface DC characteristics