Terasic PCA3 User manual

PCA3 User Manual
www.terasic.com
February 8, 2018
1
CONTENTS
Chapter 1 Introduction .....................................................................................................................2
1.1 Package Contents........................................................................................................................................2
1.2 Features.......................................................................................................................................................3
1.3 Getting Help ...............................................................................................................................................4
Chapter 2 Architecture.....................................................................................................................5
2.1 Layout and Components.............................................................................................................................5
2.2 Block Diagram of the PCA3 card...............................................................................................................6
Chapter 3 Card Components ........................................................................................................... 8
3.1 PCIe Edge Connector.................................................................................................................................8
3.2 PCIe Cable Connector..............................................................................................................................10
3.3 LEDs.........................................................................................................................................................14
3.4 Lane Re-driver IC.....................................................................................................................................14
Chapter 4 Setup Example.............................................................................................................. 16
4.1 Introduction ..............................................................................................................................................16
4.2 PC PCI Express Software SDK................................................................................................................16
4.3 Reference Design - Fundamental .............................................................................................................28
4.4 PCIe Reference Design –DDR3..............................................................................................................34
Chapter 5 Appendix ..................................................................................................................... 41
5.1 Revision History.......................................................................................................................................41
5.2 Copyright Statement.................................................................................................................................41

PCA3 User Manual
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February 8, 2018
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Chapter 1
Introduction
PCA3 (PCIe Cable Adapter, Gen 3) is a conversion card to connect boards with your host PC. It can
support up to PCIe Gen 3 x4. Users with boards such as Terasic TR4 and TR5 can establish
high-speed data transmission through this card and the PCIe cable via PCIe connector to any host
PC. It provides automatic rate-detect and adaptation to PCIe Gen-1, Gen-2, and Gen-3 speeds.
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1. .1 1 P Pa ac ck ka ag ge e C Co on nt te en nt ts s
Figure 1-1 The PCA3 package contents
The PCA3 package includes:
PCA3 card
System CD Download Guide

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1. .2 2 F Fe ea at tu ur re es s
Figure 1- shows a photograph of the PCA3.
Figure 1-2 Exterior View
The key features of the card are listed below:
•Up to 8.0Gbps PCIe 3.0 Serial Re-Driver
•PCIe x4 Gen 3
•Adjustable receiver equalization
•Adjustable transmitter amplitude and de-emphasis

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1
1. .3 3 G Ge et tt ti in ng g H He el lp p
Here is information of how to get help if you encounter any problem:
Terasic Technologies
•Tel: [phone]
•Email: [email protected]

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Chapter 2
Architecture
This chapter provides information about architecture and block diagram of the PCA3 card.
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2. .1 1 L La ay yo ou ut t a an nd d C Co om mp po on ne en nt ts s
The picture of the Terasic PCIe x4 Cable Adapter (PCA3) is shown in Figure 2-1 and Figure 2-2. It
depicts the layout of the card and indicates the locations of the connectors and key components.
Figure 2-1 The PCA3 Card PCB and Component Diagram (top view)

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Figure 2-2 The PCA3 Card PCB and Component Diagram (bottom view)
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2. .2 2 B Bl lo oc ck k D Di ia ag gr ra am m o of f t th he e P PC CA A3 3 c ca ar rd d
Figure 2-3 shows the block diagram of the PCA3 card.

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Figure 2-3 Block Diagram of PCA3

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Chapter 3
Card Components
This chapter describes the specifications of the onboard components.
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3. .1 1 P PC CI Ie e E Ed dg ge e C Co on nn ne ec ct to or r
This PCIe edge connector is used to connect the PCA3 with PC motherboard PCIe slot, as show
Figure 3-1 and Figure 3-2.
Figure 3-1 PCA3 Edge Connector

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Figure 3-2 Plug the PCA3 into the PCIe slot of the Motherboard
The pins are defined as shown in Table 3-1 with side A on the top of the center-line on the solder
side of the card and side B on the bottom of the centerline on the component side of the card.
The PCIe interface pins PETpx, PETnx, PERpx, and PERnx are named with the following
convention: “PE” stands for PCIe high speed, “T” for Transmitter, “R” for Receiver, “p” for
positive (+), and “n” for negative (-).
Note that adjacent differential pairs are separated by two ground pins to manage the connector
crosstalk.
Table 3-1 gives the wiring information of the PCIe Edge connector.
Table 3-1 Pin assignments and descriptions on PCIe Edge connector
Pin Numbers
Side B
Side A
Name
Description
Name
Description
1
NC
NC
PRSNT1n
Hot-Plug presence
detect
2
NC
NC
NC
NC
3
NC
NC
NC
NC
4
GND
Ground
GND
Ground
5
SMCLK
System Clock
NC
NC

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SMDAT
System Data Line
NC
NC
7
GND
Ground
NC
NC
8
VCC3P3
3.3V Power
NC
NC
9
NC
NC
VCC3P3
3.3V Power
10
3.3VAUX
3.3 VAuxiliary
Power
VCC3P3
3.3V Power
11
WAKE
NC
PERSTn
Fundamental
Reset
Mechanical Key
12
RSVD
Reserved
GND
Ground
13
GND
Ground
REFCLK+
Reference clock
(differential
pair)
14
PETp0
Transmitter
differential pair,
Lane 0
REFCLK-
15
PETn0
GND
Ground
16
GND
Ground
PERp0
Receiver
differential pair,
Lane 0
17
PRSNT2n
Hot-Plug presence
detect
PERn0
18
GND
Ground
GND
Ground
19
PETp1
Transmitter
differential pair,
Lane 1
RSVD
Reserved
20
PETn1
GND
Ground
21
GND
Ground
PERp1
Receiver
differential pair,
Lane 1
22
GND
Ground
PERn1
23
PETp2
Transmitter
differential pair,
Lane 2
GND
Ground
24
PETn2
GND
Ground
25
GND
Ground
PERp2
Receiver
differential pair,
Lane 2
26
GND
Ground
PERn2
27
PETp3
Transmitter
differential pair,
Lane 3
GND
Ground
28
PETn3
GND
Ground
29
GND
Ground
PERp3
Receiver
differential pair,
Lane 3
30
RSVD
Reserved
PERn3
31
PRSNT2n
Hot-Plug presence
detect
GND
Ground
32
GND
Ground
RSVD
Reserved
3
3. .2 2 P PC CI Ie e C Ca ab bl le e C Co on nn ne ec ct to or r
A PCIe cable connector is used to connect the PCIe x4 Cable and PCA cable connector, connect the

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adapter by using a PCIe x4 Cable, as show Figure 3-3.
Figure 3-3 PCIe x4 Cable and PCA3
To purchase the PCIe x4 Cable, please refer to the url: PCIe_Cable.terasic.com.
Figure 3-4 shows the PCIe Cable connects PCA3 connector

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Figure 3-4 PCIe Cable and PCA3 connector Connected
Table 3-2 gives the wiring information of the PCIe Cable connector.
Table 3-2 wiring information of the PCIe Cable connector
Pin Numbers
Name
Description
A1
GND
Ground reference for PCI
Express transmitter Lanes
A2
PETp0
Differential PCI Express
transmitter Lane 0
A3
PETn0
Differential PCI Express
transmitter Lane 0
A4
GND
Ground reference for PCI
Express transmitter Lanes
A5
PETp1
Differential PCI Express
transmitter Lane 1
A6
PETn1
Differential PCI Express
transmitter Lane 1
A7
GND
Ground reference for PCI
Express transmitter Lanes
A8
PETp2
Differential PCI Express
transmitter Lane 2
A9
PETn2
Differential PCI Express
transmitter Lane 2
A10
GND
Ground reference for PCI

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Express transmitter Lanes
A11
PETp3
Differential PCI Express
transmitter Lane 3
A12
PETn3
Differential PCI Express
transmitter Lane 3
A13
GND
Ground reference for PCI
Express transmitter Lanes
A14
CREFCLK+
Differential 100MHz cable
reference clock
A15
CREFCLK-
Differential 100MHz cable
reference clock
A16
GND
Ground reference for PCI
Express transmitter Lanes
A17
SB_RTN
Signal return for single ended
sideband signals
A18
CPRSNTn
Used for detection of whether
a cable is installed and the
downstream subsystem is
powered
A19
CPWRON
Turns power on / off to slave type
downstream subsystems
B1
GND
Ground reference for PCI
Express transmitter Lanes
B2
PERp0
Differential PCI Express
receiver Lane 0
B3
PERn0
Differential PCI Express
receiver Lane 0
B4
GND
Ground reference for PCI
Express transmitter Lanes
B5
PERp1
Differential PCI Express
receiver Lane 1
B6
PERn1
Differential PCI Express
receiver Lane 1
B7
GND
Ground reference for PCI
Express transmitter Lanes
B8
PERp2
Differential PCI Express
receiver Lane 2
B9
PERn2
Differential PCI Express
receiver Lane 2
B10
GND
Ground reference for PCI
Express transmitter Lanes
B11
PERp3
Differential PCI Express
receiver Lane 3
B12
PERn3
Differential PCI Express

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receiver Lane 3
B13
GND
Ground reference for PCI
Express transmitter Lanes
B14
PWR
+3.3VCable power
B15
PWR
+3.3VCable power
B16
PWR RTN
Cable power return
B17
PWR RTN
Cable power return
B18
CWAKEn
Power management signal for
wakeup events (optional)
B19
CPERSTn
Cable PERSTn
3
3. .3 3 L LE ED Ds s
The PCA3 includes status LEDs, please refer to Table 3-3 for the status of the LED indicator.
Table 3-3 Status of the LED indicator
3
3. .4 4 L La an ne e R Re e- -d dr ri iv ve er r I IC C
A Lane Re-driver IC U1(DS80PCI402) is implemented on PCA3 card. In addition to supporting the
4-lane repeater function, DS80PCI402 chip also supports some modifiable parameters, such as
input equalization, internal Signal Detect Threshold and loopback function. These functions can be
set up by some of the resistances on PCA3 card, Figure 3-5 shows the resistances setting. Table 3-4
lists pin configuration and function.
Board
Reference
LED name
Description
D1
CBL
Cable PRSNT1n
D2
EDGE
Edge PRSNT1n
D3
POWER
Power LED

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Figure 3-5 Resistances setting
Table 3-4 Pin configuration and function
Pin Numbers
Name
Description
19
EQA1
EQA1 control the level of equalization on the input pins. The pins are
active only when ENSMB is deasserted (low).
20
EQA0
EQA0 control the level of equalization on the input pins. The pins are
active only when ENSMB is deasserted (low).
21
RATE
RATE control pin selects GEN 1,2 and GEN 3 operating modes.
Tie 1kΩ to GND = GEN 1,2
FLOAT = AUTO Rate Select of Gen1/2 and Gen3 with de-emphasis
Tie 20kΩ to GND = GEN 3 without de-emphasis
Tied 1kΩ to VDD = RESERVED
22
RXDET
The RXDET pin controls the receiver detect function. Depending on the
input level, a 50Ω or > 50kΩ termination to the power rail is enabled.
23
LPBK
Controls the loopback function
Tie 1kΩ to GND = Root Complex Loopback (INA_n to OUTB_n)
Float = Normal Operation
Tie 1kΩ to VDD = End-point Loopback (INB_n to OUTA_n)
26
SD_TH/RD_EN
Controls the internal Signal Detect Threshold

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Chapter 4
Setup Example
This chapter demonstrates how to use PCA3 daughtercard with FPGA host board. In the system CD,
we provide demonstration projects for Terasic TR4 and TR5 FPGA board. We will introduce how to
use PCA3 daughtercard and Terasic TR5 FPGA development board to communicate with the PC via
PCIe interface. For PCA3 with TR4 board, please refer to the CD
folder …/Demonstrations/TR4/doc/ for detailed document description.
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4. .1 1 I In nt tr ro od du uc ct ti io on n
The application reference design shows how to implement fundamental control and data transfer by
using PCIe port on the TR5. In the design, basic I/O is used to read or write the buttons and LEDs
on the TR5. High-speed data transfer is performed by DMA. Both Memory-Mapped and FIFO
memory types are demonstrated in the reference design. The demonstration also makes use of the
associated PCIe cable adapter card (PCA3). System Requirements
The following items are required for the PCA demonstration
•TR5 board x1
•PCA3 card x1
•PCIe x4 Cable x1
•PC x1
4
4. .2 2 P PC C P PC CI I E Ex xp pr re es ss s S So of ft tw wa ar re e S SD DK K
The CD contains a PC Windows based SDK to allow users to develop their 64-bits software
application on Windows XP/7/10 64-bits. The SDK is located in the “CDROM
\Demonstrations\TR5\PCIe_SW_KIT”folder which includes:
PCI Express Driver
PCI Express Library

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PCI Express Examples
The kernel mode driver assumes the PCIe vender ID (VID) is 0x1172 and the device ID (DID) is
0xE003. If different VID and DID are used in the design, users need to modify the PCIe vender ID
(VID) and device ID (DID) in the driver INF file accordingly.
The PCI Express Library is implemented as a single DLL called TERASIC_PCIE_AVMM.DLL.
This file is a 64-bits DLL. With the DLL exported to the software API, users can easily
communicate with the FPGA. The library provides the following functions:
Basic Data Read and Write
Data Read and Write by DMA
For high performance data transmission, DMA is required as the read and write operations are
specified under the hardware design on the FPGA.
PCI Express Software Stack
Figure 7-8 shows the software stack for the PCI Express application software on 64-bit Windows.
The PCI Express driver incorporated in the DLL library is called TERASIC_PCIE_AVMM.dll.
Users can develop their applications based on this DLL. The altera_pcie_win_driver.sys kernel
driver is provided by Altera.

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Figure 4-1 PCI Express Software Stack
Install PCI Express Driver on Windows
The PCIe driver is located in the folder:
“CDROM\Demonstrations\TR5\PCIe_SW_KIT\PCIe_Driver “
The folder includes the following four files:
Altera_pcie_win_driver.cat
Altera_pcie_win_driver.inf
Altera_pcie_win_driver.sys
WdfCoinstaller01011.dll
To install the PCI Express driver, execute the steps below:
1. Make sure the TR5 and the PC are both powered off.
2. Plug the PCIe adapter card(PCA3) into the PCIe slot on the PC motherboard. Use the PCIe
cable to connect to the TR5 PCIE connector and the PCA3 (See Figure 4-2 )

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Figure 4-2 FPGA board connect to PC
3. Power on your TR5 board and the host PC
4. Make sure Altera Programmer and USB-Blaster II driver are installed
5. Execute test.bat in “CDROM\Demonstrations\TR5\PCIe_Fundamental\demo_batch” to
configure the FPGA
6. Restart windows Operation System
7. Click the Control Panel menu from the Windows Start menu. Click the Hardware and the
Sound item before clicking the Device Manager to launch the Device Manager dialog. There
will be a PCI Device item in the dialog, as shown in Figure 4-3. Move the mouse cursor to
the PCI Device item and right click it to select the Update Driver Software... item.