Xilinx Spartan-3A DSP FPGA Series Quick start guide

Spartan-3A/3AN Starter Kit Board Schematic
(Annotated)
21-AUG-2007
For additional information …
www.xilinx.com/s3astarter
See UG334: Spartan-3A/3AN Starter Kit User Guide for further information on each board feature

Spartan-3A/3AN Starter Kit Board
TM
FX2 Expansion Connector, 6-pin Headers
Hirose FX2 100-pin Expansion Connector
Connectorless Debugging Port Landing Pads
Six-pin Accesory Headers
DAC Analog Outputs
ADC Analog Inputs
FX2 Expansion
Connector
Six-pin
Accessory
Headers
Connectorless
Debugging Port
ADC
Inputs
DAC
Outputs

Spartan-3A/3AN Starter Kit Board
TM
RS-232, VGA, Audio ports, SMA connector
Stereo Audio mini jack
PS/2 Mouse/Keyboard connector
Clock Input/Output SMA connector
RS-232 serial ports
12-bit VGA port
SPI PROM select jumpers
VGA
PS/2
Audio jack
Clock SMA
SPI select
jumper
RS-232
DCE DTE
The PS/2 connector has primary and secondary connections to
the FPGA. The secondary connections are available by
attaching an external Y-splitter cable.
Primary DATA
Secondary DATA
Primary CLK
Secondary CLK
NOTE: See schematic Page 13 for details.

Spartan-3A/3AN Starter Kit Board
TM
10/100 Ethernet PHY, magnetics
RJ-45 Connector
LAN8700 10/100 Ethernet PHY
www.smsc.com/main/catalog/lan8700.html
LAN8700 10/100 Ethernet PHY
RJ-45 Connector

Spartan-3A/3AN Starter Kit Board
TM
Voltage regulators
www.national.com/pf/LP/LP3906.html
Voltage
FPGA core
supply
FPGA I/O
Banks 0, 1, 2
FPGA auxiliary
supply
Embedded
USB / JTAG
Programmer
Bank 0
Bank 2
Bank 1
Bank 3
(1.2V)
(3.3V)
(3.3V)
(1.8V)
FPGA
FPGA
DDR2 SDRAM
Termination
(0.9V)
DDR2 SDRAM
Device, FPGA
(1.8V)
DAC Reference
Voltage
(3.3V)
DDR2 SDRAM
Voltage Ref.
(0.9V)
I C Interface
2
I C Interface
2
regulators
Power switch
Wall power adapter
input
I/O Bank 3

Spartan-3A/3AN Starter Kit Board
TM
Configuration, Mode pins, Platform Flash PROM
SUSPEND pin, JTAG header
Second 4 Mbit
Platform Flash PROM
is not mounted
Platform Flash Enable
FPGA Mode Select jumper
JTAG Header
Platform
Flash
PROM
FPGA Configuration Control
SUSPEND
slide switch
PROG_B
jumper
DONE
LED
DONE LED
PROG_B
pushbutton
PROG_B pushbutton
SUSPEND switch
JTAG Header
Platform Flash PROM
(Jumper J26)
M0
M1
M2
J26
Master Serial
M0
M1
M2
J26
Master SPI
M0
M1
M2
J26
Master BPI
M0
M1
M2
J26
JTAG
M0
M1
M2
J26
Master Internal SPI
Platform Flash Enable Jumper
(Jumper J46)
(Spartan-3AN only)
DONE
CE
GND
J46
PROM
DONE
CE
GND
J46
PROM
DONE
CE
GND
J46
PROM
Platform Flash Enable Jumper
(Jumper J46)
DISABLE Enable
only during
configuration
Enable
Always
Also enable
Platform Flash
PROM using
Jumper J46
Disable Platform Flash PROM
by removing Jumper J46
(Jumper J46)

Spartan-3A/3AN Starter Kit Board
TM
FPGA I/O Bank 0 and Bank 1, Clock Oscillators
50 MHz Oscillator Auxiliary Oscillator Socket
CLK_50MHZ CLK_AUX
FPGA
Bank 1
FPGA
Bank 0
FPGA: XC3S700A/AN-4FGG484C(E FPGA: XC3S700A/AN-4FGG484C(ES)

Spartan-3A/AN Starter Kit Board
TM
FPGA I/O Bank 2 and Bank 3
FPGA
FPGA
Bank 2
Bank 3
AWAKE
LED
FPGA I/O Bank 3
is dedicated to the
DDR2 SDRAM
interface
interface
FPGA: XC3S700A/AN-4FGG484C(ES)
FPGA: XC3S700A/AN-4FGG484C(ES)

Spartan-3A/3AN Starter Kit Board
TM
FPGA Power Supply Decoupling

Spartan-3A/3AN Starter Kit Board
TM
ADC, DAC, and Pre-amplifier
www.linear.com
ADC, DAC,
pre-amplifier
headers
Analog
Analog-to-Digital Converter (ADC)
LTC1407-1, two-channel, 12-bit resolution, serial
www.linear.com/pc/productDetail.do?navId=H0,C1,C1155,C1001,C1158,P2484
Digital-to-Analog Converter (DAC)
LTC2624, four-channel, 12-bit resolution, serial
www.linear.com/pc/productDetail.do?navId=H0,C1,C1155,C1005,C1156,P2048
(3.3V)
(nominally 3.3V)
The DAC_REF_CD voltage is programmable via the
I2C control interface on the LP3906 voltage regulator
designated as IC18 on sheet 5. At power-up, this
reference voltage is 3.3V.
(see sheet 2)
Thevenin termination to improve
the signal integrity on these
high-fanout signals.
Programmable Gain Amplifier (AMP)
LTC6912-1, two-channel, serial
www.linear.com/pc/productDetail.do?navId=H0,C1,C1154,C1009,C1121,P7596

0Ω
Spartan-3A/3AN Starter Kit Board
TM
32Mx16 DDR2 SDRAM
32Mx16 DDR2 SDRAM
DDR2 SDRAM device
Termination network
Connects to FPGA
I/O Bank 3
The DDR2 SDRAM interface has specific pin assignment
and layout requirements to support the Xilinx Memory
Interface Generator (MIG) software. See the “DDR SDRAM”
chapter in UG334: Spartan-3A/3AN Starter Kit User Guide.
0Ω
DESIGN NOTE: The Revision C board has an inductor in this
location. Shorting across this location improves high-frequency
DDR2 SDRAM interface performance.
The Revision D board uses a 0Ωresistor.
DESIGN NOTE: The Revision C board has an inductor in this
location. Shorting across this location improves high-frequency
DDR2 SDRAM interface performance.
The Revision D board uses a 0Ωresistor.

Spartan-3A/3AN Starter Kit Board
TM
M29DW323DT x8/x16 Parallel NOR Flash
STMicroelectronics
M29DW323DT
32 Mbit, x8/x16
parallel NOR Flash
www.st.com/stonline/products/families/memories/fl_nor_emb/fl_m29dw.htm
To configure from parallel NOR
Flash, remove Jumper J46 to
disable the Platform Flash PROM
M0
M1
M2
J26
DONE
CE
GND
J46
PROM
To configure from parallel NOR
Flash, set the FPGA mode select
pins using Jumper J46 as shown

Spartan-3A/3AN Starter Kit Board
TM
STMicro SPI serial Flash, Atmel serial DataFlash
STMicroelectronics M25P16 16 Mbit SPI serial Flash PROM
Atmel AT45DB161D 16 Mbit serial DataFlash PROM
®
Atmel DataFlash
STMicro SPI Flash
SPI Flash
select jumpers
www.st.com/stonline/products/families/memories/fl_ser/index.htm
The Spartan-3A Starter Kit board supports multiple pad landings for each SPI Flash architecture.
However, only one STMicro and one Atmel PROM are mounted on the board.
www.atmel.com/products/DataFlash/
(Jumper J1)
J1 J1
DONE
CE
GND
J46
PROM
Platform Flash Jumper
(Jumper J46)
Jumper J1 defines which SPI Flash is used for
SPI mode configuration and which is available
using a second SPI slave select signal.
Configure From:
Atmel Select Signal:
STMicro Select Signal:
M0
M1
M2
J26
Atmel STMicro
SPI_SS_B
SPI_SS_B
ALT_SS_B
ALT_SS_B
Remove Jumper J46
to configure FPGA
from SPI Flash PROM
Mode Select Jumpers
(Jumper J26)
Master SPI Mode
M[2:0]=<0:0:1>
NOTE: Jumper J1 appears on schematic Page 3.

Spartan-3A/3AN Starter Kit Board
TM
Slide switches, Rotary knob, Character LCD,
Pushbutton switches, discrete LEDs
Rotary knob switch with pushbutton switch
Eight discrete LEDs
Four pushbutton switches
Four slide switches
16-character by 2-line LCD display
Four pushbutton switches
surround rotary knob
Rotary pushbutton switch
Four slide switches
Eight discrete LEDs
16x2 character LCD

Spartan-3A/3AN Starter Kit Board
TM
DDR2 SDRAM Termination Network (1 of 2)
The DDR2 SDRAM interface has specific pin assignment
and layout requirements to support the Xilinx Memory
Interface Generator (MIG) software. See the “DDR SDRAM”
chapter in UG334: Spartan-3A/3AN Starter Kit User Guide.

Spartan-3A/3AN Starter Kit Board
TM
DDR2 SDRAM Termination Network (2 of 2)
The DDR2 SDRAM interface has specific pin assignment
and layout requirements to support the Xilinx Memory
Interface Generator (MIG) software. See the “DDR SDRAM”
chapter in UG334: Spartan-3A/3AN Starter Kit User Guide.

Spartan-3A/3AN Starter Kit Board
TM
Differential I/O Headers
2x17stake pin header 2x17stake pin header
FPGA
Bank 2
FPGA
Bank 0
Pairs of pins on the
header form potential
differential I/O pairs.
Optionally, each pin
can be a single-ended
I/O pin.
Transmit Receive
Recieve stake pins
Transmit stake pins
Each individual
differential I/O pair
is routed with matched
100-ohm impedance.
If using differential inputs, set the DIFF_TERM=TRUE constraint.
There are no external termination resistors provided on the board.
INST <I/O_BUFFER_INSTANTIATION_NAME> DIFF_TERM = “TRUE” ;
The receive clock differential
pair feeds the GCLK6 and
GCLK7 global clock inputs,
which in turn connect to the
DCM_X2Y3
top, right DCM labeled