Alphi CPCI-AD32 User manual

CPCI-AD32
Intelligent DSP Based
32 Channel Analog Input Card
for 3U CompactPCICompactPCI™ systems
REFERENCE MANUAL
751-10-000-4000
Version 1.0
September 1998
ALPHI TECHNOLOGY CORPORATION
6202 S. Maple Avenue #120
Tempe, AZ 85283 USA
Tel: [phone]
Fax: [phone]

CPCI-AD32 REFERENCE MANUAL
ALPHI TECHNOLOGY CORP. Page ii REV 1.0
Part Number : 751-10-000-4000 Copyright ALPHI Technology Corporation, 1998
NOTICE
The information in this document has been carefully checked and is believed to be
entirely reliable. While all reasonable efforts to ensure accuracy have been taken in the
preparation of this manual, ALPHI TECHNOLOGY assumes no responsibility resulting
from omissions or errors in this manual, or from the use of information contain herein.
ALPHI TECHNOLOGY reserves the right to make any changes, without notice, to this or
any of ALPHI TECHNOLOGY’s products to improve reliability, performance, function or
design.
ALPHI TECHNOLOGY does not assume any liability arising out of the application or use
of any product or circuit described herein; nor does ALPHI TECHNOLOGY convey any
license under its patent rights or the rights of others.
ALPHI TECHNOLOGY CORPORATION
All Rights Reserved
This document shall not be duplicated, nor its contents used
for any purpose, unless express permission has been granted in advance.

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TABLE OF CONTENTS
1. GENERAL DESCRIPTION_______________________________________________1
1.1 INTRODUCTION__________________________________________________________1
1.2 FUNCTIONAL DESCRIPTION _______________________________________________1
1.3 REFERENCE MATERIALS LIST _____________________________________________3
2. HOST (CPCI) SIDE ____________________________________________________4
2.1 PCI CONFIGURATION REGISTERS __________________________________________4
2.2 PCI BASE ADDRESS REGISTERS ___________________________________________4
2.3 CPCI OPERATION REGISTERS _____________________________________________4
3. C31 SIDE ____________________________________________________________5
3.1 INTERNAL ORGANIZATION ________________________________________________5
3.2 CPCI INTERFACE ________________________________________________________5
3.3 DSP MEMORY AND REGISTER MAP SUMMARY________________________________7
3.4 RESET SIGNALS ________________________________________________________11
3.5 LOCAL DSP INTERRUPT SOURCES ________________________________________11
4. JUMPER DESCRIPTIONS______________________________________________11
5. CONNECTIONS______________________________________________________12
5.1 EXTERNAL I/O CONNECTOR (P3) __________________________________________12
5.2 DAC OUTPUTS (P1, P2) __________________________________________________14
5.3 EMULATOR CONNECTION (P6) ____________________________________________14
5.4 FACTORY USE (P7)______________________________________________________14
5.5 RESERVED (P4, P5) _____________________________________________________14
5.6 32 BIT CPCI BUS (J1) ____________________________________________________14
6. STANDALONE OPERATION ___________________________________________14
6.1 CPCI RESET ___________________________________________________________14
6.2 CPCI BUS CLOCK _______________________________________________________14

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Part Number : 751-10-000-4000 Copyright ALPHI Technology Corporation, 1998
1. GENERAL DESCRIPTION
1.1 INTRODUCTION
The CPCI-AD32 is an intelligent DSP based 32 channel analog input card in a 3U CPCI
form factor. The CPCI-AD32 provides up to 32 single ended or 16 differential inputs to a 16
bit converter. The DSP allows for the offloading from the HOST CPU any necessary I/O
processing to monitor and service these channels. The primary features of the CPCI-AD32
are as follows:
•Integrated DSP (TI TMS320C31) at 60 MHz to offload I/O operation from host or for
standalone applications
•128K x 32 bit zero wait state SRAM for the DSP.
•512K by 8 bit FLASH device for customer applications
•Up to 32 single ended or 16 differential analog inputs to a pair of 16 bit converters.
•Programmable PGA allow for gains of 1, 2, 4, or 8 on a per channel basis.
•Programmable capture rates from 2 channels @ 100 KHz, to 32 channels @ 6250 Hz.
•Full support for automatic calibration of the inputs.
•2 channels of 16 bit analog output @20 KHz.
•Up to 16 bits of general purpose digital input or output.
•Bus Master DMA to offload HOST processor.
1.2 FUNCTIONAL DESCRIPTION
A functional block diagram of the CPCI-AD32 is presented below in Figure 1-1. The jumper
placement and the connector placement is depicted in Figure 1-2. The CPCI-AD32 can
operate as a slave that is managed by the host processor on the CPCI bus or it can operate
in a standalone mode of operation without a host.
The CPCI-AD32 is supported by ALPHI Technology under Windows NT by a Board
Support Package which is supplied with the card. Other documentation supplied with the
card will describe this support in full detail.
The card is also supported by a DSP Support Library providing the following features:
•Common access routines for communications with the HOST
•Identify the applicable card resources and parameters
All these are provided in a manner consistent across ALPHI Technology platforms. Other
documentation supplied with the card will describe the support in full detail.
A bootloader provided on the card allows for control by the HOST and for independent
operation in stand alone operation. User code can be downloaded to FLASH memory and
booted automatically on reset. Access to the card can be made by the HOST CPCI bus.

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Part Number : 751-10-000-4000 Copyright ALPHI Technology Corporation, 1998
PCI to Local Bus
Bridge
Bus Master DMA
Mailbox Registers
DSP C31
60 MHz
Local SRAM
128K x 32
Local FLASH
512K x 8
Local DSP
Bus
CPCI
Bus
8 bit
Digital Port
8 bit
Digital Port
16 bit
10 uS
A/D Conv
16 bit
10 uS
D/A Conv
2 X
16 Single Ended
or 8 Differential
Input Multiplexer
and Conditioning
Figure 1.1: Block Diagram
P3 P1
W8
W7
W4
P
7
P
5W6
W5
W9
P
6
Figure 1.2: Jumper and Connector Locations

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1.3 REFERENCE MATERIALS LIST
The reader should refer to the PCI Local Bus Specification for a detailed explanation of the
PCI bus architecture and timing requirements. This specification is available from the
following source:
PCI Special Interest Group
PO Box 14070
Portland, OR 97214
Tel: [phone]
Tel: [phone]
Fax: [phone]
The reader is also referred to the S5933 PCI Controller data book:
AMCC Applied Micro Circuits Corporation
6195 Lusk Boulevard
San Diego, CA 92121-2793
Tel: [phone]
http://www.amcc.com
WindowsNT and Windows95 Programming Tools:
BlueWater Systems
144 Railroad Ave. Suite #217
Edmonds, WA 98020
Tel: [phone]
Fax: [phone]
E-Mail: [email protected]
Web: http://www.bluewatersystems.com

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2. HOST (CPCI) SIDE
2.1 PCI CONFIGURATION REGISTERS
The card presents the following configuration values to the CPCI system, based on the
values stored in the NVRAM device read by the AMCC PCI interface chip.
Register Value (Meaning)
Vendor ID 0x13c5 (ALPHI Technology)
Device ID 0x010C
Revision ID 0x00
Class Code 0xff0000 (Device does not fit into defined class codes)
Interrupt Line 0xff
Interrupt Pin A
Multifunction Device No
Build In Self Test No
Latency Timer 0x00
Minimum Grant 0x00
Maximum Latency 0x00
Expansion ROM Size None
Table 2.1: CPCI Configuration Registers
2.2 PCI BASE ADDRESS REGISTERS
The card requests base address regions from the CPCI system after RESET, based on the
values stored in the NVRAM device read by the AMCC PCI interface chip.
The decode addresses of these regions are assigned by the host processor. The CPCI-
AD32 uses 1 of the 5 AMCC mapped base address registers. The AMCC is normally
programmed at the factory to request the following resource from the CPCI BIOS:
BAR From To Description Type
00x00000000 0x00000003F AMCC PCI Operation Registers MEM
Table 2.2: Base Address and Use
NOTE: The AMCC has been programmed to request memory above 1 Mbytes.
2.3 CPCI OPERATION REGISTERS
The host processor communicates with the CPCI-AD32 card via the AMCC pass-through
interface. After the base address register has been programmed by the CPCI configurator,
incoming CPCI I/O or Memory cycles are used to access the registers of the AMCC chip.
The PCI Operation Registers of the AMCC 5933 chip are depicted below:

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Offset Register Name
0x00 OMB1 Outgoing Mailbox Register 1
0x04 OMB2 Outgoing Mailbox Register 2
0x08 OMB3 Outgoing Mailbox Register 3
0x0C OMB4 Outgoing Mailbox Register 4
0x10 IMB1 Incoming Mailbox Register 1
0x14 IMB2 Incoming Mailbox Register 2
0x18 IMB3 Incoming Mailbox Register 3
0x1C IMB4 Incoming Mailbox Register 4
0x20 FIFO Register Port (bi-directional)
0x24 MWAR Master Write Address Register
0x28 MWTC Master Write Transfer Counter
0x2C MRAR Master Read Address Register
0x30 MRTC Master Read Transfer Counter
0x34 MBEF Mailbox Empty/Full Status
0x38 INTCSR Interrupt Control/Status Register
0x3C MCSR Bus Master Control/Status Register
Table 2.3: AMCC Registers (HOST)
For more information about these registers refer to the AMCC PCI controller manual.
3. C31 SIDE
3.1 INTERNAL ORGANIZATION
The CPCI-AD32 card is divided into different sections. Each section and its relationship to
other sections will be discussed. The CPCI-AD32 sections are:
•CPCI interface
•DSP Memory and Register Map
•Analog input interface
•Analog output interface
•Digital interface
3.2 CPCI INTERFACE
The local DSP processor communicates with the CPCI bus through the AMCCS9533 chip
that provides bi-directional FIFO and Mailbox registers. The CPCI-AD32 can function as
both a servant (CPCI target) or as a master (CPCI initiator) for DMA access. The following
interface descriptions refer to the CPCI interface as seen by the local DSP. The AMCC
registers are located at DSP address 0xf00080.
3.2.1 BI-DIRECTIONAL FIFO
Two separate FIFO data paths are implemented within the AMCCS9533, a read FIFO that
allows data transfers from the module to the CPCI bus and a write FIFO that transfers data

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from the CPCI to the module. Size of the FIFO is 32 bit X 8. Read and write DMA access to
the host can occur via the FIFO registers if it is supported by the software on the HOST and
is enabled. Alternatively, the FIFO registers can utilize a polled scheme on the HOST and
DSP. Both FIFOs are accessed via access to the same location as seen by the DSP, offset
0x08.
3.2.2 MAILBOX REGISTERS
The Mailbox registers of the AMCCS9533 provide a bi-directional data path that can be
used to send data or software control information between the HOST and DSP of that half
of the CPCI-AD32 module. Interrupts can be enabled based on a specific mailbox event.
There are 4 incoming mailboxes and 4 outgoing mailboxes. Each mailbox is 32 bits wide.
The address offsets for the mailboxes are shown below in Table 3-1.
3.2.3 ADDITIONAL REGISTERS
The AMCC S5933 PCI controller has a set of additional registers to control and monitor the
behavior of the CPCI interface.
The address offsets of these registers are shown below in Table 3-1.
Offset Register Name
0x00 Incoming Mailbox Reg 1
0x01 Incoming Mailbox Reg 2
0x02 Incoming Mailbox Reg 3
0x03 Incoming Mailbox Reg 4
0x04 Outgoing Mailbox Reg 1
0x05 Outgoing Mailbox Reg 2
0x06 Outgoing Mailbox Reg 3
0x07 Outgoing Mailbox Reg 4
0x08 Add-on FIFO port
0x09 Bus master write Address Register
0x0A Add-on Pass through Address
0x0B Add-on Pass trough Data
0x0C Bus master read Address Register
0x0D Add-on Mailbox Empty/full Status
0x0E Add-on Interrupt Control
0x0F Add-on General Control/Status Register
Table 3.1: AMCC Registers (DSP)
For more information about these registers refer to the AMCC PCI controller manual.

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3.3 DSP MEMORY AND REGISTER MAP SUMMARY
NAME START END DATA R/W COMMENTS
SRAM 0x000000 0x01FFFF D00-D31 R/W Zero wait state static RAM
FLASH 0x400000 0x41FFFF D00-D07 R/W 128K x 8 Protected
A/D RESULT 0xF00000 0xF00000 D00-D31 RBoth conversion results
CONTROL1 0xF00008 0xF00008 D00-D03 WControls internal settings
CONTROL2 0xF00010 0xF00010 D00-D07 WControls internal settings
CONTROL3 0xF00018 0xF00018 D00-D00 WControls internal settings
STROBE 0xF00020 0xF00020 N/A WS Start conversion
D/A OUTPUT 0xF00028 0xF00028 D00-D31 WDAC Output register
DIGITAL
PORTS 0xF00030 0xF00030 D00-D15 R/W Bidirectional digital ports
LAST CHAN 0xF00040 0xF00040 D00-D03 WEnding channel register
MODE/GAIN 0xF00060 0xF0006F D00-D07 R/W Mode and gain per channel
AMCC 0xF00080 0xF000FF D00-D31 R/W AMCC Registers
Table 3.2: DSP Memory Map
3.3.1 A/D RESULT (Read Only)
BITS 31 - 16 BITS 15 - 00
Channel 17 – 32 Result Channel 1 – 16 Result
This 32 bit register contains the conversion results from the two A/D converters. This result
must be read during the INT2 interrupt handler, or it will be overwritten with the next
conversion result. There is no status bit to indicate completion of a conversion.
3.3.2 CONTROL1 (Write Only)
BIT 03 BIT 02 BIT 01 BIT 00
CAL_MODE EX_SCAN_EN TCLK0_EN EX_GATE_EN
EX_GATE_EN External gate enable
If this bit is set to 1, then EXGATE must be low for A/D conversions. If this bit is cleared to
0, then EXGATE has no effect.
TCLK0_EN, EX_SCAN_EN A/D
These bits determine what will trigger an A/D conversion.
EX_SCAN_EN TCLK0_EN DOUT Selection
0 0 Writes to STROBE will trigger conversion.
0 1 TCLK0 from DSP will trigger conversion.
1 0 EXTRIG will trigger conversion.
1 1 Both TCLK0 and EXTRIG will trigger conversion.
Table 3.4: Signal routing to STRB_OUT