Altera CLR-HSMC User manual

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CONTENTS
UCHAPTER 1 INTRODUCTION .................................................................................................................................2
U1.1 FeaturesU.....................................................................................................................................................................2
U1.2 Getting HelpU.............................................................................................................................................................3
UCHAPTER 2 ARCHITECTURE & CONFIGURATION ..........................................................................................4
U2.1 Block DiagramU..........................................................................................................................................................5
U2.2 ConnectivityU.............................................................................................................................................................7
UCHAPTER 3 PIN DESCRIPTION ...........................................................................................................................10
U3.1 HSMC Expansion ConnectorU.................................................................................................................................10
UCHAPTER 4 COMPONENTS .................................................................................................................................18
U4.1 LVDS 28-Bit Channel LinkU....................................................................................................................................18
U4.2 3V LVDS Quad CMOS Differential Line DriverU...................................................................................................18
U4.3 Operation ModeU......................................................................................................................................................18
UCHAPTER 5 DEMONSTRATIONS ........................................................................................................................21
U5.1 Digital Camera Demonstration for DE4U.................................................................................................................21
U5.2 Digital Camera Demonstration for DE3U.................................................................................................................23
U5.3 Digital Camera Demonstration for DE2-115U..........................................................................................................25
U5.4 Digital Camera with PCI Express Interface for DE4U..............................................................................................27
UCHAPTER 6 APPENDIX .........................................................................................................................................30
U6.1 Revision HistoryU.....................................................................................................................................................30
U6.2 Copyright StatementU...............................................................................................................................................30

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Chapter 1
0B Introduction
CLR-HSMC is designed to provide Camera Link connections which are communication interfaces
for vision applications. It uses the High Speed Mezzanine Card (HSMC) to interface with other
mother board hosting HSMC/HSTC carrier such as DE4, DE3 and DE2-115.
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1. .1 1 F Fe ea at tu ur re es s
XFigure 1-1Xshows the photo of the CLR-HSMC board. The important features are listed below:
Support of standard Camera Link modes (base, medium, dual base assembly)
Serial Communication with camera
Simple interface
Automatic detection by hardware / software
Two LVDS 28-bit channel link chip (DS90CR288A)
。28 bit, 20 to 85 MHz shift clock support
。Up to 2.38 Gbps throughput
。Up to 297.5 Mbytes/sec bandwidth
Support 2.5V and 3.3 V I/O standard

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Figure 1-1 Picture of the CLR-HSMC Board
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1. .2 2 G Ge et tt ti in ng g H He el lp p
Here are some places to get help if you encounter any problem:
Email to [email protected]
Taiwan & China: [phone]
Korea : [phone]
Japan: [phone]

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Chapter 2
1B Architecture & Configuration
This chapter describes the architecture and configuration of the CLR-HSMC board including block
diagram and components.
Figure 2-1 The CLR-HSMC Board PCB and Component Diagram
A photograph of the CLR-HSMC is shown in XFigure 2-1Xand XFigure 2-2X. It depicts the layout of
the board and indicates the location of the connectors and key components.

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Figure 2-2 The CLR-HSMC Board Back Side
The following components are provided on the CLR-HSMC board:
National Semiconductor DS90CR288A for LVDS to LVTTL adapting of data signals. (U1, U3,)
National Semiconductor DS90LV047A for LVDS to LVTTL adapting of control signals. (U5,
U7)
National Semiconductor DS90LV019 for LVDS to LVTTL adapting of serial control signals.
(U4, U6)
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2. .1 1 B Bl lo oc ck k D Di ia ag gr ra am m
XFigure 2-3Xshows the block diagram of the CLR-HSMC board in base mode configuration.

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Figure 2-3 Block Diagram of the CLR-HSMC Board (Base Mode)
XFigure 2-4Xshows the block diagram of the CLR-HSMC board in medium mode configuration.
Figure 2-4 Block Diagram of the CLR-HSMC Board (Medium Mode)

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XFigure 2-5Xshows the block diagram of the CLR-HSMC board in dual-base mode configuration.
Figure 2-5 Block Diagram of the CLR-HSMC Board (Dual-base Mode)
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2. .2 2 C Co on nn ne ec ct ti iv vi it ty y
The CLR-HSMC offers connectivity to any HSMC-based host boards including the DE4, DE3 and
DE2-115.

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Figure 2-6 Camera Link Receiver Card connection to the Altera DE2-115 Development Board
Figure 2-7 Camera Link Receiver Card connection to the Altera DE3 Development System
Note. An adapter (HFF) is required to connect CLR-HSMC with DE3. It is bundled in DE3 kit.

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Figure 2-8 Camera Link Receiver Card connection to Altera DE4 Development and Education Board
Note. An adapter (HMF2) is required to connect CLR-HSMC with DE4. It is bundled in DE4 kit.

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Chapter 3
2B Pin Description
This chapter describes the detailed information of the connector interfaces, and the pin description
on the CLR-HSMC board.
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3. .1 1 H HS SM MC C E Ex xp pa an ns si io on n C Co on nn ne ec ct to or r
The CLR-HSMC board contains a HSMC connector. XFigure 3-1X, XFigure 3-2Xand XFigure 3-3Xshow
the pin-outs of the HSMC connector on the CLR-HSMC board.
The voltage level of the I/O pin on the HSMC connector can support to 3.3V and 2.5V, because the
DS90CR288AVIH are as low as 2.0V (Please refer to the DS90CR288A's datasheets)

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Figure 3-1 Pin-outs of Bank 1 on the HSMC Connector

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Figure 3-2 Pin-outs of Bank 2 on the HSMC Connector

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Figure 3-3 Pin-outs of Bank 3 on the HSMC Connector

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XTable 3-1Xshows the pin description of the HSMC connector.
Table 3-1 The pin mappings of the HSMC connector (J3)
HSMC Expansion Connector –J3
Pin Number
Signal Name
Direction
Function
37
HSMC_TDI
Input
JTAG Test loopback
38
HSMC_TDI
Output
JTAG Test loopback
39
rx_base0
Output
Base output data 0
40
rx_base1
Output
Base output data 1
41
rx_base2
Output
Base output data 2
42
rx_base7
Output
Base output data 7
43
rx_base3
Output
Base output data 3
44
rx_base8
Output
Base output data 8
45
VCC3P3
Power
Power 3.3V
46
VCC12
Power
Power 12V
47
rx_base4
Output
Base output data 4
48
rx_base9
Output
Base output data 9
49
rx_base5
Output
Base output data 5
50
rx_base10
Output
Base output data 10
51
VCC3P3
Power
Power 3.3V
52
VCC12
Power
Power 12V
53
rx_base6
Output
Base output data 6
54
rx_base12
Output
Base output data 12
55
rx_base11
Output
Base output data 11
56
rx_base13
Output
Base output data 13
57
VCC3P3
Power
Power 3.3V
58
VCC12
Power
Power 12V
59
rx_base16
output
Base output data 12
60
rx_base14
output
Base output data 14
61
rx_base18
Output
Base output data 18
62
rx_base15
Output
Base output data 15
63
VCC3P3
Power
Power 3.3V
64
VCC12
Power
Power 12V
65
rx_base19
Output
Base output data 19
66
rx_base17
Output
Base output data 17
67
rx_base20
Output
Base output data 20
68
rxcc4
Input
Camera Control 4
69
VCC3P3
Power
Power 3.3V
70
VCC12
Power
Power 12V
71
rx_base21
Output
Base output data 21
72
rxcc3
Input
Camera Control 3
73
rx_base27
Output
Base output data 27

15
74
rxcc2
Input
Camera Control 2
75
VCC3P3
Power
Power 3.3V
76
VCC12
Power
Power 12V
77
rx_base26
Output
Base output data 26
78
rxcc1
Input
Camera Control 1
79
rx_base25
Output
Base output data 25
80
rxcc_en
Input
Camera Control enable
1: Enable.
0: Disable
81
VCC3P3
Power
Power 3.3V
82
VCC12
Power
Power 12V
83
rx_base24
Output
Base output data 24
84
rxSerTFG_en
Input
SERTFG Receiver Enable (active low):
0: Enable.
1: Disable
85
rx_base22
Output
Base output data 22
86
rxSerTFG
Output
SERTFG serial data from Camera
87
VCC3P3
Power
Power 3.3V
88
VCC12
Power
Power 12V
89
rx_full14_hsmc
Output
Full output data 14
90
rxSerTC
Input
SERTC serial data from HSTC to Camera
91
rx_medium1
Output
Medium output data 1
92
rxSerTC_en
Input
SERTC Driver Enable.
1: Enable.
0: Disable
93
VCC3P3
Power
Power 3.3V
94
VCC12
Power
Power 12V
95
rx_medium2
Output
Medium output data 2
96
rxclk_base
Output
Receiver base clock
97
rx_medium3
Output
Medium output data 3
98
rxclk_full
Output
Receiver full clock
99
VCC3P3
Power
Power 3.3V
100
VCC12
Power
Power 12V
101
rx_medium4
Output
Medium output data 4
102
rx2SerTC_en
Input
SERTC Driver Enable.
1: Enable.
0: Disable
103
rx_medium5
Output
Medium output data 5
104
rxSerTFG
Output
SERTFG serial data from Camera
105
VCC3P3
Power
Power 3.3V
106
VCC12
Power
Power 12V
107
rx_medium6
Output
Medium output data 6
108
rx2SerTFG_en
Input
SERTFG Receiver Enable (active low):

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0: Enable.
1: Disable
109
rx_medium7
Output
Medium output data 7
110
rx2cc1
Input
Second camera Control 1 (for Dual Base Mode
only)
111
VCC3P3
Power
Power 3.3V
112
VCC12
Power
Power 12V
113
rx_medium8
Output
Medium output data 8
114
rx2cc2
Input
Second camera Control 2 (for Dual Base Mode
only)
115
rx_medium9
Output
Medium output data 9
116
rx2cc3
Input
Second camera Control 3 (for Dual Base Mode
only)
117
VCC3P3
Power
Power 3.3V
118
VCC12
Power
Power 12V
119
rx_medium10
Output
Medium output data 10
120
rx2cc4
Input
Second camera Control 4 (for Dual Base Mode
only)
121
rx_medium11
Output
Medium output data 11
122
rx2cc_en
Input
Second camera CC Driver enable pin
(for Dual Base Mode only)
123
VCC3P3
Power
Power 3.3V
124
VCC12
Power
Power 12V
125
rx_medium12
Output
Medium output data 12
126
rx_medium0
Output
Medium output data 0
127
rx_medium13
Output
Medium output data 13
128
rx_medium27
Output
Medium output data 27
129
VCC3P3
Power
Power 3.3V
130
VCC12
Power
Power 12V
131
rx_medium14
Output
Medium output data 14
132
rx_medium26
Output
Medium output data 26
133
rx_medium15
Output
Medium output data 15
134
rx_medium25
Output
Medium output data 25
135
VCC3P3
Power
Power 3.3V
136
VCC12
Power
Power 12V
137
rx_medium16
Output
Medium output data 16
138
rx2SerTC
Input
Second camera SERTC
(for Dual Base Mode only)
139
rx_medium17
Output
Medium output data 17
140
rx_full9_hsmc
Output
Full output data 9
141
VCC3P3
Power
Power 3.3V
142
VCC12
Power
Power 12V
143
rx_medium18
Output
Medium output data 18

17
144
rx_full10_hsmc
Output
Full output data 10
145
rx_medium19
Output
Medium output data 19
146
rx_full11_hsmc
Output
Full output data 11
147
VCC3P3
Power
Power 3.3V
148
VCC12
Power
Power 12V
149
rx_medium21
Output
Medium output data 21
150
rx_full12_hsmc
Output
Full output data 12
151
rx_medium20
Output
Medium output data 20
152
rx_full13_hsmc
Output
Full output data 13
153
VCC3P3
Power
Power 3.3V
154
VCC12
Power
Power 12V
155
rx_medium22
Output
Medium output data 22
156
rxclk_medium
Output
Receiver medium clock
157
rx_medium24
Output
Medium output data 24
158
rx_full27_hsmc
Output
Full output data 27
159
VCC3P3
Power
Power 3.3V
160
GND
Power
Power ground
165~172
GND
Power
Power ground

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Chapter 4
3B Components
This chapter gives a simple description of the on board components, such as operational mode,
signaling standard. For more detailed information you could refer to its datasheet which is available
on manufacturer’s website or from our provided system CD.
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4. .1 1 L LV VD DS S 2 28 8- -B Bi it t C Ch ha an nn ne el l L Li in nk k
Two National Semiconductor LVDS 28-bit channel link chip (DS90CR288A) is installed on the CLR board for
receiving LVDS signals from two Camera Link Receiver ports. It converts the LVDS signaling standard into
parallel LVCMOS signals, which then connect to the HSMC connector. It can support a shift clock frequency
from 20 to 85MHz. Some of the key features are listed below:
20 to 85 MHz shift clock support
Up to 2.38 Gbps throughput
Four LVDS channels
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4. .2 2 3 3V V L LV VD DS S Q Qu ua ad d C CM MO OS S D Di if ff fe er re en nt ti ia al l L Li in ne e D Dr ri iv ve er r
The CLR board features two National Semiconductor DS90LV047A 3V LVDS quad CMOS differential line
driver chip for LVCMOS signals to LVDS signals adapting. It is used to transport the control signals to the
CameraLink ports. Some of the key features are listed below:
Four LVDS channels with enable control
Above 400MHz switch rates
3.3V LVCMOS single-ended signaling and +/- 350mV differential signaling
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4. .3 3 O Op pe er ra at ti io on n M Mo od de e
With two receiver ports, the CLR supports Base, Dual Base and Medium CameraLink modes.
Which mode is in use depends on the connected digital camera. Port J2 is designed to host the base
mode CameraLink signals as well as the camera control and serial communication signals. That’s,
five twisted pairs of LVDS wires carries the Base mode CameraLink signals. Two twisted pairs of
LVDS are used for serial communication with the camera and four additional twisted pairs are used

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for camera control. Port J1 is used for Medium mode and Dual Base mode control signals. Five
twisted pairs of LVDS wires transport the Medium mode signals. Four twisted pairs of LVDS wires
carry the control signals.
Table 4-1 CameraLink Base configuration (J2)
Pin
Signal
Pin
Signal
Remarks
1
Inner shield
14
Inner Shield
2
CC4-(out)
15
CC4+(out)
Camera Control 4
3
CC3+(out)
16
CC3-(out)
Camera Control 3
4
CC2-(out)
17
CC2+(out)
Camera Control 2
5
CC1+(out)
18
CC1-(out)
Camera Control 1
6
SERTFG+(in)
19
SERTFG-(out)
Serial to Frame Grabber
7
SERTC-(out)
20
SERTC+(out)
Serial to Camera
8
X3+(in)
21
X3-(in)
CameraLink data 3 (base)
9
CLKX+(in)
22
CLKX-(in)
Camera Link clock (base)
10
X2+(in)
23
X2-(in)
CameraLink data 2 (base)
11
X1+(in)
24
X1-(in)
CameraLink data 1 (base)
12
X0+(in)
25
X0-(in)
CameraLink data 0 (base)
13
Inner Shield
26
Inner Shield
Table 4.2 CameraLink Medium configuration (J1)
Pin
Signal
Pin
Signal
Remarks
1
Inner Shield
14
Inner Shield
2
15
3
16
4
17
5
18
6
19
7
20
8
Y3+(in)
21
Y3-(in)
CameraLink data 3 (medium)
9
CLKY+(in)
22
CLKY-(in)
Camera Link clock (medium)
10
Y2+(in)
23
Y2-(in)
CameraLink data 2 (medium)
11
Y1+(in)
24
Y1-(in)
CameraLink data 1 (medium)
12
Y0+(in)
25
Y0-(in)
CameraLink data 0 (medium)
13
Inner Shield
26
Inner Shield