Altera 40GBASE-KR4 Instruction manual

Ethernet Reference Design
Quick User guide
Example on 40GBASE-KR4
Stratix V GX Signal Integrity Development Board
Date: 05/03/2016
Revision: 1.0

Contents
Introduction .................................................................................................................................................. 3
System Overview and Functional Description .............................................................................................. 4
40GBASE-KR4 Ethernet MAC and PHY IP ...................................................................................................... 5
40Gbps Ethernet MAC and PHY IP Overview................................................................................................ 6
Quick Start Guide .......................................................................................................................................... 7
Signal Integrity Stratix V GT Edition Setup................................................................................................ 9
Compile, Build, Load and Run the Software ............................................................................................. 9
Viewing the Result ..................................................................................................................................11
System Monitor Panel......................................................................................................................... 13
System Control Panel..........................................................................................................................14
Packet Monitor Panel.......................................................................................................................... 14
Possible Issues.............................................................................................................................................16
Reference Documents.................................................................................................................................17

Introduction
This reference design demonstrates the operation of Altera 40G base-KR4 Ethernet MAC and PHY IP
solution (PDF) on a Stratix V device (5SGTMC7K2F40C2). It is configured to demonstrate on a Signal
Integrity Development Kit, Stratix V GT Edition Board using Altera development tool Quartus Prime
release 15.1. This design provides a flexible test and demonstration platform which effectively control,
test, and monitor 40Gbps Ethernet packets.
This hardware demonstration reference design offers the following features:
Auto-Negotiation (AN) as defined in Clause 63 (only negotiation to 40GBASE-KR4 mode is
supported.
The 40GBASE-KR4 PMD as defined in Clause 84 which includes Link Training (LT) as defined in
Clause 72.
Forward Error Correction (FEC) as defined in Clause 74.
System Console based (GUI control and status interface) flexible, reusable, and extendable user
control interface allows users to dynamically configure and monitor any configuration registers
provided by this demo design.

System Overview and Functional Description
The hardware platform consists of three sub-systems:
The 40GBase-KR4 MAC and PHY IP
Packet Client with random packet generator and monitor
System Console for configuration and control of the system
This system can be represented by the following diagram:
Figure 1 System Overview

40GBASE-KR4 Ethernet MAC and PHY IP
The Altera 40G Ethernet MAC and PHY IP core is implemented in compliance with the IEEE 802.3ba 2010
Higher Speed Ethernet Standard. It is including Auto-Negotiation (AN), Link Training (LT) and Forward
Error Correction (FEC). This module handles the frame encapsulation and flow of data between a client
logic and Ethernet network via a 40GbE Ethernet PCS and PMA (PHY). In the TX direction, the MAC
accepts client frames, inserts inter-packet gap (IPG), preamble, start of frame delimiter (SFD), header,
padding, and checksum before passing them to the PHY. The PHY encodes the MAC frame as required
for reliable transmission over the media to the remote end. Similarly, in the RX direction, the MAC
accepts frames from the PHY, performs checks, updates statistics counters, strips out the CRC, preamble,
and SFD, and passes the rest of the frame to the client.
Packet Client with Random Packet Generator and Monitor:
The Packet Client includes a Packet Generator and a Packet Monitor. These modules have 256-bit
Avalon-ST interface for the data-path and connect to the 40G Ethernet MAC. There is also a 32-bit
Avalon-MM configuration and status interface associated with both the generator and monitor. The
generator can generate random packets. Monitor parses all packets received from MAC and checks the
integrity of the packets.
Terminal System Controller (sterm.exe):
This reference design provides a windows terminal program sterm.exe which can run on a PC (windows
based operating system). User must provide byte addresses in order to access registers on chip using
this interface.

40Gbps Ethernet MAC and PHY IP Overview
As mentioned in previous sections, the 40G Ethernet sub-system consists of 40G MAC and PHY sub-
modules. The MAC client side data path interface has two options: Avalon ST interface and Custom ST
interface. This reference design uses an Avalon-ST interface which includes interface adapter. This
adapter then provides a standard Avalon-ST interface for the MAC client. The MAC connects to the PHY
core over XLGMII interface. The 40G Ethernet IP core can be demonstrated as the following simplified
diagram:
Figure 2 Ethernet MAC and PHY IP
Additional Functional Details of 40GE Ethernet IP Core:
The additional details of the IP core can be found in the User guide. The IP core evaluation package and
the user guide can be downloaded from Altera website:
http://www.altera.com/products/ip/iup/ethernet/m-alt-40-100gb-ethernet.html

Quick Start Guide
The reference design setup essentially consists of software and hardware.
Software Requirement:
Quartus Prime 15.1 or above (with system console feature)
Transceiver Signal Integrity Development Kit –Stratix V GX Edition v12.0.0 or above (with clock
control feature) [if the software says current active Quartus version isn’t the correct version then
the board is broken, you need to switch to another board.]
Hardware Requirement:
Stratix V GX SI Development Kit
24 inch Backplane (XCEDE 715-9914-000 REV-D)
Backpanel (XCEDE SI TEST BOARD NELCO 4000-1351 PCB93 REV-P)
SMA cable*16 (ST18/SMAm/36)
120W, 20VDC @6.32A Power Supply
USB Type B cable (Square)

The relevant setups for each of these components are provided in detail as shown below:
Figure 3 Hardware Setup
The Signal Integrity Stratix V GT development board requires minimum hardware setup. Switch 6 (SW6),
all 4 pin need to set to logic 0 (close). See below.
Figure 4 Hardware Switches

Signal Integrity Stratix V GT Edition Setup
Open Integrity Stratix V GT development kit –Stratix V GX Edition v12.0.0 from Window “Start” manual
“All Program” -> “Altera” -> “Transceiver Signal Integrity Development Kit – Stratix V GX Edition v12.0.0”
-> “Clock Control”
Program Y3 clock frequency to 644.53125MHz.
Figure 5 Clock Control
Compile, Build, Load and Run the Software
1. Open the project file alt_e40_avalon_top_sv_kr4.qpf file in alt_e40_avalon_top_sv_kr4_13_1
directory.
2. Re-compiled the alt_e40_avalon_top_sv_kr4_13_1 project to generate .sof file.
3. Open the SignalTap II Logic Analyzer by double clicking on “Tool” -> “SignalTap II Logic Analyzer”.
4. Download the alt_e40_avalon_top_sv.sof to development board.
Make sure the pins are assigned as compatible pairs. In this design transceiver bank B2L is used for 4
pairs of TX/RX.

Figure 6 Transceiver Bank

Viewing the Result
Connect the cables to the corresponding pinouts. (Note that cables should be in orders of negative and
positive) Run the main_run.tcl under system_console folder in system console and go to KR4_Status tab,
change KR4 Settings by reading and writing registers.
Figure 7 System Console Interface
Figure 8 KR4 Settings

You need to reset SEQ and write register and uncheck reset SEQ and rewrite register until all registers
are as the below picture.
Click on “Read all Register”and you can access the register values.
Figure 9 KR4 Status Register
The example capture is a TX to RX loopback test setting.
1. Auto negotiation function must turn off for TX to RX loopback test.
2. Force negotiated to FEC mode.
3. Reset SEQ is the reset of initiate auto negotiate and link training function.
The KR4 status control panel needs to configure first before the device able the do auto negotiation and
link training process. Register 0xB0, 0xC0 and 0xD0 need to set as the example above.
Register 0xD0:
Bit[22:20]: 011 = rx_ctle_mode set to “Fine-gained turning at being of LT”.
Bit[23] : 1 = Search upper VOD set.
Bit[26:24]: 010 = Rx_ctle_mode set to “Trigger DFE at end of LT”.

Register 0xC0:
Bit[0] : 0 = Disable the KR4 AN function.
Register 0xB0:
Bit[0] : 1 = Force Negotiate to FEC mode set.
Bit[6:4] : 000 = no force.
Bit[19] : 1 = Force Negotiate to FEC mode.
Note: All change will effect only after “Reset SEQ” bit is set.
Note: For normal two device setup, register 0xB0 and 0xC0 don’t need to change. Only register 0xD0
needs to change to 0x82b85111 for long backplane.
System Monitor Panel
The system monitor panel contains all the error message and status information. The example of the
capture below is one of the error free conditions. The system monitor panel will not refresh
automatically. It needs to manually click on the “Update” button to refresh status.
Figure 10 System Monitor Panel

System Control Panel
There are three major functions in the system control panel, Soft Reset, Serial/parallel loopback, and
PRBs testing function. The current test doesn’t need to use those functions. See capture below.
Figure 11 System Control Panel
Packet Monitor Panel
This hardware demo design only able to generate randomize size packet. Continually generate packet
can be trigger by press “Send Pkt” button. “Stop Pkt” button is stopped the traffic generation.
The packet monitor has TX/RX packet count, Error packet count and TX and RX packet count difference.
See example capture below.
Figure 12 Packet Monitor Panel

Note: For this TX to RX loopback test, checking the TX packet count and RX packet count is one of the
methods to confirm the test pass or fail. If all TX counter are equal to RX counter, that means pass.
Otherwise it could be a hardware issue. Try to reconnect your cables, replace cables or change pinout.
Make sure your positive and negative TXs and RXs are connected correctly.

Possible Issues
In the previous update, one lane of signal didn’t work because one of the hardware pin wasn’t
transmitting data. To resolve the problem, check pin assignments and try to use alternative pins in the
same transceiver bank. Quartus strictly requires TX/RX to use compatible pins, so user might need to try
multiple pairs to find the right pair. Please see the picture below as reference for this specific design.
Figure 13 Pinout Planner

Reference Documents
Altera 40 and 100Gbps Ethernet MAC and PHY MegaCore Function User Guide
https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_40_100gbe.pdf
Signal Integrity Development Kit, Stratix V GT Edition Board
https://www.altera.com/products/boards_and_kits/dev-kits/altera/kit-sv-gt-si.html
Altera Wiki, 40G Base-KR4 Ethernet Hardware Demo
http://www.alterawiki.com/wiki/40G_Base-KR4_Ethernet_Hardware_Demo#Introduction