Altera 40GBASE-KR4 Instruction manual

Ethernet Reference Design
Quick User guide
Example on 40GBASE-KR4
Stratix V GX Signal Integrity Development Board
Date: 05/03/2016
Revision: 1.0

Contents
Introduction .................................................................................................................................................. 3
System Overview and Functional Description .............................................................................................. 4
40GBASE-KR4 Ethernet MAC and PHY IP ...................................................................................................... 5
40Gbps Ethernet MAC and PHY IP Overview................................................................................................ 6
Quick Start Guide .......................................................................................................................................... 7
Signal Integrity Stratix V GT Edition Setup................................................................................................ 9
Compile, Build, Load and Run the Software ............................................................................................. 9
Viewing the Result ..................................................................................................................................11
System Monitor Panel......................................................................................................................... 13
System Control Panel..........................................................................................................................14
Packet Monitor Panel.......................................................................................................................... 14
Possible Issues.............................................................................................................................................16
Reference Documents.................................................................................................................................17

Introduction
This reference design demonstrates the operation of Altera 40G base-KR4 Ethernet MAC and PHY IP
solution (PDF) on a Stratix V device (5SGTMC7K2F40C2). It is configured to demonstrate on a Signal
Integrity Development Kit, Stratix V GT Edition Board using Altera development tool Quartus Prime
release 15.1. This design provides a flexible test and demonstration platform which effectively control,
test, and monitor 40Gbps Ethernet packets.
This hardware demonstration reference design offers the following features:
Auto-Negotiation (AN) as defined in Clause 63 (only negotiation to 40GBASE-KR4 mode is
supported.
The 40GBASE-KR4 PMD as defined in Clause 84 which includes Link Training (LT) as defined in
Clause 72.
Forward Error Correction (FEC) as defined in Clause 74.
System Console based (GUI control and status interface) flexible, reusable, and extendable user
control interface allows users to dynamically configure and monitor any configuration registers
provided by this demo design.

System Overview and Functional Description
The hardware platform consists of three sub-systems:
The 40GBase-KR4 MAC and PHY IP
Packet Client with random packet generator and monitor
System Console for configuration and control of the system
This system can be represented by the following diagram:
Figure 1 System Overview

40GBASE-KR4 Ethernet MAC and PHY IP
The Altera 40G Ethernet MAC and PHY IP core is implemented in compliance with the IEEE 802.3ba 2010
Higher Speed Ethernet Standard. It is including Auto-Negotiation (AN), Link Training (LT) and Forward
Error Correction (FEC). This module handles the frame encapsulation and flow of data between a client
logic and Ethernet network via a 40GbE Ethernet PCS and PMA (PHY). In the TX direction, the MAC
accepts client frames, inserts inter-packet gap (IPG), preamble, start of frame delimiter (SFD), header,
padding, and checksum before passing them to the PHY. The PHY encodes the MAC frame as required
for reliable transmission over the media to the remote end. Similarly, in the RX direction, the MAC
accepts frames from the PHY, performs checks, updates statistics counters, strips out the CRC, preamble,
and SFD, and passes the rest of the frame to the client.
Packet Client with Random Packet Generator and Monitor:
The Packet Client includes a Packet Generator and a Packet Monitor. These modules have 256-bit
Avalon-ST interface for the data-path and connect to the 40G Ethernet MAC. There is also a 32-bit
Avalon-MM configuration and status interface associated with both the generator and monitor. The
generator can generate random packets. Monitor parses all packets received from MAC and checks the
integrity of the packets.
Terminal System Controller (sterm.exe):
This reference design provides a windows terminal program sterm.exe which can run on a PC (windows
based operating system). User must provide byte addresses in order to access registers on chip using
this interface.

40Gbps Ethernet MAC and PHY IP Overview
As mentioned in previous sections, the 40G Ethernet sub-system consists of 40G MAC and PHY sub-
modules. The MAC client side data path interface has two options: Avalon ST interface and Custom ST
interface. This reference design uses an Avalon-ST interface which includes interface adapter. This
adapter then provides a standard Avalon-ST interface for the MAC client. The MAC connects to the PHY
core over XLGMII interface. The 40G Ethernet IP core can be demonstrated as the following simplified
diagram:
Figure 2 Ethernet MAC and PHY IP
Additional Functional Details of 40GE Ethernet IP Core:
The additional details of the IP core can be found in the User guide. The IP core evaluation package and
the user guide can be downloaded from Altera website:
http://www.altera.com/products/ip/iup/ethernet/m-alt-40-100gb-ethernet.html

Quick Start Guide
The reference design setup essentially consists of software and hardware.
Software Requirement:
Quartus Prime 15.1 or above (with system console feature)
Transceiver Signal Integrity Development Kit –Stratix V GX Edition v12.0.0 or above (with clock
control feature) [if the software says current active Quartus version isn’t the correct version then
the board is broken, you need to switch to another board.]
Hardware Requirement:
Stratix V GX SI Development Kit
24 inch Backplane (XCEDE 715-9914-000 REV-D)
Backpanel (XCEDE SI TEST BOARD NELCO 4000-1351 PCB93 REV-P)
SMA cable*16 (ST18/SMAm/36)
120W, 20VDC @6.32A Power Supply
USB Type B cable (Square)

The relevant setups for each of these components are provided in detail as shown below:
Figure 3 Hardware Setup
The Signal Integrity Stratix V GT development board requires minimum hardware setup. Switch 6 (SW6),
all 4 pin need to set to logic 0 (close). See below.
Figure 4 Hardware Switches

Signal Integrity Stratix V GT Edition Setup
Open Integrity Stratix V GT development kit –Stratix V GX Edition v12.0.0 from Window “Start” manual
“All Program” -> “Altera” -> “Transceiver Signal Integrity Development Kit – Stratix V GX Edition v12.0.0”
-> “Clock Control”
Program Y3 clock frequency to 644.53125MHz.
Figure 5 Clock Control
Compile, Build, Load and Run the Software
1. Open the project file alt_e40_avalon_top_sv_kr4.qpf file in alt_e40_avalon_top_sv_kr4_13_1
directory.
2. Re-compiled the alt_e40_avalon_top_sv_kr4_13_1 project to generate .sof file.
3. Open the SignalTap II Logic Analyzer by double clicking on “Tool” -> “SignalTap II Logic Analyzer”.
4. Download the alt_e40_avalon_top_sv.sof to development board.
Make sure the pins are assigned as compatible pairs. In this design transceiver bank B2L is used for 4
pairs of TX/RX.

Figure 6 Transceiver Bank