AMCC PPC405 User manual

Part Number 405CPU
Revision 1.02 - September 10, 2007
AMCC Proprietary 1
PPC405 Processor Preliminary User’s Manual
405
PPC405 Processor
User’s Manual

2 AMCC Proprietary
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
Printed in the United States of America, Monday, September 10, 2007
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Preliminary User’s Manual
Contents
Figures.................................................................................................................................................. 11
Tables ................................................................................................................................................... 13
About This Book.................................................................................................................................. 17
1. Overview .......................................................................................................................................... 21
1.1 PPC405 Processor Features .................................................................................................................... 21
1.2 PowerPC Architecture .............................................................................................................................. 22
1.3 PPC405 as a PowerPC Implementation ................................................................................................... 23
1.4 RISC Processor Core Organization .......................................................................................................... 23
1.4.1 Instruction and Data Cache Controllers .......................................................................................... 23
1.4.1.1 Instruction Cache Unit ............................................................................................................. 23
1.4.1.2 Data Cache Unit ...................................................................................................................... 23
1.4.2 Memory Management Unit .............................................................................................................. 24
1.4.3 Debug .............................................................................................................................................. 25
1.4.3.1 Development Tool Support ...................................................................................................... 25
1.4.3.2 Debug Modes .......................................................................................................................... 25
1.4.4 Processor Core Interfaces .............................................................................................................. 26
1.4.4.1 Processor Local Bus ................................................................................................................ 26
1.4.4.2 Device Control Register Bus .................................................................................................... 26
1.4.4.3 Clock and Power Management ................................................................................................ 26
1.4.4.4 JTAG ........................................................................................................................................ 26
1.4.4.5 Interrupts .................................................................................................................................. 26
1.4.4.6 On-Chip Memory ..................................................................................................................... 26
1.5 Processor Programming Model ................................................................................................................ 26
1.5.1 Data Types ...................................................................................................................................... 26
1.5.2 Processor Register Set Summary ................................................................................................... 27
1.5.2.1 General Purpose Registers ..................................................................................................... 27
1.5.2.2 Special Purpose Registers ...................................................................................................... 27
1.5.2.3 Machine State Register ........................................................................................................... 27
1.5.2.4 Condition Register ................................................................................................................... 27
1.5.2.5 Device Control Registers ......................................................................................................... 27
1.5.3 Memory-Mapped I/O Registers ....................................................................................................... 28
1.5.4 Addressing Modes .......................................................................................................................... 28
2. Programming Model ....................................................................................................................... 31
2.1 User and Privileged Programming Models ............................................................................................... 31
2.2 Storage Addressing .................................................................................................................................. 31
2.2.1 Storage Attributes ........................................................................................................................... 32
2.3 Registers .................................................................................................................................................. 32
2.3.1 General Purpose Registers (GPR0-GPR31) ................................................................................... 35
2.3.2 Special Purpose Registers (SPR) ................................................................................................... 35
2.3.2.1 Count Register (CTR) .............................................................................................................. 36
2.3.2.2 Link Register (LR) .................................................................................................................... 37
2.3.2.3 Fixed Point Exception Register (XER) ..................................................................................... 37
2.3.2.4 Special Purpose Registers (USPRG0 and SPRG0–SPRG7) ................................................. 39
2.3.2.5 Processor Version Register (PVR) .......................................................................................... 39
2.3.3 Condition Register (CR) .................................................................................................................. 39
2.3.3.1 CR Fields After Compare Instructions ..................................................................................... 40
2.3.3.2 The CR0 Field .......................................................................................................................... 40

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2.3.4 The Time Base ................................................................................................................................ 41
2.3.5 Machine State Register (MSR) ........................................................................................................ 42
2.3.6 Device Control Registers ................................................................................................................. 42
2.4 Data Types and Alignment ................................................................................................................... 42
2.4.1 Alignment for Storage Reference and Cache Control Instructions .................................................. 43
2.4.2 Alignment and Endian Operation .................................................................................................... 43
2.4.3 Summary of Instructions Causing Alignment Exceptions ................................................................ 43
2.5 Byte Ordering ............................................................................................................................................ 44
2.5.1 Structure Mapping Examples .......................................................................................................... 44
2.5.1.1 Big Endian Mapping ................................................................................................................. 45
2.5.1.2 Little Endian Mapping .............................................................................................................. 45
2.5.2 Support for Little Endian Byte Ordering ........................................................................................... 45
2.5.3 Endian (E) Storage Attribute ........................................................................................................... 46
2.5.3.1 Fetching Instructions from Little Endian Storage Regions ....................................................... 46
2.5.3.2 Accessing Data in Little Endian Storage Regions .................................................................... 47
2.5.3.3 PowerPC Byte-Reverse Instructions ........................................................................................ 47
2.6 Instruction Processing .............................................................................................................................. 49
2.7 Branch Processing .................................................................................................................................... 50
2.7.1 Unconditional Branch Target Addressing Options .......................................................................... 50
2.7.2 Conditional Branch Target Addressing Options .............................................................................. 50
2.7.3 Conditional Branch Condition Register Testing ............................................................................... 51
2.7.4 BO Field on Conditional Branches .................................................................................................. 51
2.7.5 Branch Prediction ............................................................................................................................ 52
2.8 Speculative Accesses ............................................................................................................................... 53
2.8.1 Speculative Accesses in the PPC405 ............................................................................................. 53
2.8.1.1 Prefetch Distance Down an Unresolved Branch Path ............................................................. 54
2.8.1.2 Prefetch of Branches to the CTR and Branches to the LR ...................................................... 54
2.8.2 Preventing Inappropriate Speculative Accesses ............................................................................. 54
2.8.2.1 Fetching Past an Interrupt-Causing or Interrupt-Returning Instruction .................................... 54
2.8.2.2 Fetching Past tw or twi Instructions ......................................................................................... 55
2.8.2.3 Fetching Past an Unconditional Branch ................................................................................... 55
2.8.2.4 Suggested Locations of Memory-Mapped Hardware ............................................................... 55
2.8.3 Summary ......................................................................................................................................... 56
2.9 User and Supervisor Modes .................................................................................................................... 56
2.9.1 MSR Bits and Exception Handling .................................................................................................. 56
2.9.2 Privileged Instructions ..................................................................................................................... 56
2.9.3 Privileged SPRs .............................................................................................................................. 57
2.9.4 Privileged DCRs .............................................................................................................................. 58
2.10 Synchronization ...................................................................................................................................... 58
2.10.1 Context Synchronization ............................................................................................................... 58
2.10.2 Execution Synchronization ............................................................................................................ 60
2.10.3 Storage Ordering and Synchronization ......................................................................................... 60
2.11 Implemented Instruction Set Summary ................................................................................................... 61
2.11.1 Instructions Specific to the PowerPC Embedded Environment ..................................................... 62
2.11.2 Storage Reference Instructions ..................................................................................................... 62
2.11.3 Arithmetic Instructions ................................................................................................................... 63
2.11.4 Logical Instructions ........................................................................................................................ 64
2.11.5 Compare Instructions .................................................................................................................... 64
2.11.6 Branch Instructions ........................................................................................................................ 64
2.11.6.1 CR Logical Instructions .......................................................................................................... 65
2.11.6.2 Rotate Instructions ................................................................................................................. 65
2.11.6.3 Shift Instructions .................................................................................................................... 65

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2.11.6.4 Cache Management Instructions ........................................................................................... 66
2.11.7 Interrupt Control Instructions ......................................................................................................... 66
2.11.8 TLB Management Instructions ...................................................................................................... 66
2.11.9 Processor Control Instructions ...................................................................................................... 67
2.11.10 Extended Mnemonics .................................................................................................................. 67
3. Cache Operations ........................................................................................................................... 69
3.1 ICU Features ............................................................................................................................................ 69
3.2 DCU Features ........................................................................................................................................... 69
3.3 ICU Organization ...................................................................................................................................... 69
3.3.1 ICU Operations ............................................................................................................................... 71
3.3.2 Instruction Cachability Control ........................................................................................................ 71
3.3.3 Instruction Cache Synonyms .......................................................................................................... 71
3.3.4 ICU Coherency ................................................................................................................................ 72
3.4 DCU Organization .................................................................................................................................... 72
3.4.1 DCU Operations .............................................................................................................................. 73
3.4.2 DCU Write Strategies ...................................................................................................................... 74
3.4.3 DCU Load and Store Strategies ...................................................................................................... 74
3.4.4 Data Cachability Control ................................................................................................................. 75
3.4.5 DCU Coherency .............................................................................................................................. 75
3.5 Cache Instructions .................................................................................................................................... 75
3.5.1 ICU Instructions ............................................................................................................................... 75
3.5.2 DCU Instructions ............................................................................................................................. 76
3.6 Cache Control and Debugging Features ................................................................................................ 77
3.6.1 CCR0 Programming Guidelines ...................................................................................................... 79
3.6.2 ICU Debugging ................................................................................................................................ 80
3.6.3 DCU Debugging .............................................................................................................................. 81
3.7 DCU Performance .................................................................................................................................... 81
3.7.1 Pipeline Stalls .................................................................................................................................. 81
3.7.2 Cache Operation Priorities .............................................................................................................. 82
3.7.3 Simultaneous Cache Operations .................................................................................................... 82
3.7.4 Sequential Cache Operations ......................................................................................................... 82
4. On-Chip Memory (OCM) ................................................................................................................. 85
4.1 OCM Addressing ...................................................................................................................................... 86
4.2 Store Data Bypass Behavior and Memory Coherency ............................................................................. 86
4.3 OCM Registers ......................................................................................................................................... 88
5. Memory Management ..................................................................................................................... 91
5.1 MMU Overview ......................................................................................................................................... 91
5.2 Address Translation .................................................................................................................................. 91
5.3 Translation Lookaside Buffer (TLB) .......................................................................................................... 92
5.3.1 Unified TLB ..................................................................................................................................... 92
5.3.2 TLB Fields ....................................................................................................................................... 93
5.3.2.1 Page Identification Fields ......................................................................................................... 93
5.3.2.2 Translation Field ...................................................................................................................... 94
5.3.2.3 Access Control Fields .............................................................................................................. 95
5.3.2.4 Storage Attribute Fields ........................................................................................................... 95
5.3.3 Shadow Instruction TLB .................................................................................................................. 96
5.3.3.1 ITLB Accesses ......................................................................................................................... 96
5.3.4 Shadow Data TLB ........................................................................................................................... 97
5.3.4.1 1 DTLB Accesses .................................................................................................................... 97
5.3.5 Shadow TLB Consistency ............................................................................................................... 97

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5.4 TLB-Related Interrupts ............................................................................................................................. 99
5.4.1 Data Storage Interrupt ..................................................................................................................... 99
5.4.2 Instruction Storage Interrupt ............................................................................................................ 99
5.4.3 Data TLB Miss Interrupt ................................................................................................................ 100
5.4.4 Instruction TLB Miss Interrupt ....................................................................................................... 100
5.5 TLB Management ................................................................................................................................... 100
5.5.1 TLB Search Instructions (tlbsx/tlbsx.) ............................................................................................ 100
5.5.2 TLB Read/Write Instructions (tlbre/tlbwe) ...................................................................................... 101
5.5.3 TLB Invalidate Instruction (tlbia) .................................................................................................... 101
5.5.4 TLB Sync Instruction (tlbsync) ....................................................................................................... 101
5.6 Recording Page References and Changes ............................................................................................ 101
5.7 Access Protection ................................................................................................................................... 102
5.7.1 Access Protection Mechanisms in the TLB ................................................................................... 102
5.7.1.1 General Access Protection ............................................................................................... 102
5.7.1.2 Execute Permissions ............................................................................................................. 102
5.7.1.3 Write Permissions .................................................................................................................. 102
5.7.1.4 Zone Protection ...................................................................................................................... 103
5.7.2 Access Protection for Cache Control Instructions ......................................................................... 104
5.7.3 Access Protection for String Instructions ....................................................................................... 105
5.8 Real-Mode Storage Attribute Control ...................................................................................................... 105
5.8.1 Storage Attribute Control Registers ............................................................................................... 106
5.8.1.1 Data Cache Write-through Register (DCWR) ........................................................................ 106
5.8.1.2 Data Cache Cachability Register (DCCR) ............................................................................. 106
5.8.1.3 Instruction Cache Cachability Register (ICCR) ...................................................................... 107
5.8.1.4 Storage Guarded Register (SGR) .......................................................................................... 107
5.8.1.5 Storage User-defined 0 Register (SU0R) .............................................................................. 107
5.8.1.6 Storage Little-Endian Register (SLER) .................................................................................. 107
6. Interrupt Handling ......................................................................................................................... 109
6.1 Architectural Definitions and Behavior .................................................................................................... 109
6.2 Behavior of the PPC405 Implementation ................................................................................................ 110
6.3 Interrupt Handling Priorities .................................................................................................................... 111
6.4 Critical and Noncritical Interrupts ........................................................................................................... 112
6.5 General Interrupt Handling Registers ..................................................................................................... 114
6.5.1 Machine State Register (MSR) ...................................................................................................... 114
6.5.2 Save/Restore Registers 0 and 1 (SRR0–SRR1) ........................................................................... 115
6.5.3 Save/Restore Registers 2 and 3 (SRR2–SRR3) ........................................................................... 115
6.5.4 Exception Vector Prefix Register (EVPR) ..................................................................................... 116
6.5.5 Exception Syndrome Register (ESR) ............................................................................................ 116
6.5.6 Data Exception Address Register (DEAR) .................................................................................... 118
6.6 Critical Input Interrupts ............................................................................................................................ 118
6.7 Machine Check Interrupts ....................................................................................................................... 118
6.7.1 Instruction Machine Check Handling ............................................................................................. 119
6.7.2 Data Machine Check Handling ...................................................................................................... 120
6.8 Data Storage Interrupt ............................................................................................................................ 120
6.9 Instruction Storage Interrupt ................................................................................................................... 121
6.10 External Interrupt .................................................................................................................................. 122
6.10.1 External Interrupt Handling .......................................................................................................... 122
6.11 Alignment Interrupt ............................................................................................................................... 123
6.12 Program Interrupt .................................................................................................................................. 123
6.13 System Call Interrupt ............................................................................................................................ 124

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6.14 Programmable Interval Timer (PIT) Interrupt ....................................................................................... 125
6.15 Fixed Interval Timer (FIT) Interrupt ....................................................................................................... 125
6.16 Watchdog Timer Interrupt ..................................................................................................................... 126
6.17 Data TLB Miss Interrupt ........................................................................................................................ 127
6.18 Instruction TLB Miss Interrupt ............................................................................................................... 127
6.19 Debug Interrupt ..................................................................................................................................... 128
7. Timer Facilities .............................................................................................................................. 129
7.1 Time Base .............................................................................................................................................. 130
7.1.1 Reading the Time Base ................................................................................................................. 131
7.1.2 Writing the Time Base ................................................................................................................... 131
7.2 Programmable Interval Timer (PIT) ...................................................................................................... 131
7.2.1 Fixed Interval Timer (FIT) .............................................................................................................. 132
7.3 Watchdog Timer ..................................................................................................................................... 133
7.4 Timer Status Register (TSR) .................................................................................................................. 135
7.5 Timer Control Register (TCR) ................................................................................................................. 135
8. Debugging ..................................................................................................................................... 137
8.1 Development Tool Support ..................................................................................................................... 137
8.2 Debug Interfaces .................................................................................................................................... 137
8.3 IEEE 1149.1 Test Access Port (JTAG Debug Port) ............................................................................... 137
8.3.1 JTAG Connector ........................................................................................................................... 138
8.3.2 JTAG Instructions .......................................................................................................................... 138
8.3.3 JTAG Boundary Scan ................................................................................................................... 138
8.3.4 JTAG Implementation ................................................................................................................... 139
8.3.5 JTAG ID Register .......................................................................................................................... 139
8.4 Trace Port .............................................................................................................................................. 139
8.5 Debug Modes ......................................................................................................................................... 139
8.5.1 Internal Debug Mode ..................................................................................................................... 140
8.5.2 External Debug Mode ................................................................................................................... 140
8.5.3 Debug Wait Mode ......................................................................................................................... 140
8.5.4 Real-time Trace Debug Mode ....................................................................................................... 141
8.6 Processor Control ................................................................................................................................... 142
8.7 Processor Status ................................................................................................................................... 142
8.8 Debug Registers ..................................................................................................................................... 142
8.8.1 Debug Control Registers ............................................................................................................... 143
8.8.1.1 Debug Control Register 0 (DBCR0) ....................................................................................... 143
8.8.1.2 Debug Control Register 1 (DBCR1) ....................................................................................... 144
8.8.2 Debug Status Register (DBSR) .................................................................................................... 145
8.8.3 Instruction Address Compare Registers (IAC1–IAC4) ................................................................. 147
8.8.4 Data Address Compare Registers (DAC1–DAC2) ..................................................................... 147
8.8.5 Data Value Compare Registers (DVC1–DVC2) ........................................................................ 147
8.8.6 Debug Events ................................................................................................................................ 147
8.8.7 Instruction Complete Debug Event ............................................................................................... 148
8.8.8 Branch Taken Debug Event .......................................................................................................... 148
8.8.9 Exception Taken Debug Event ...................................................................................................... 148
8.8.10 Trap Taken Debug Event ............................................................................................................ 149
8.8.11 Unconditional Debug Event ......................................................................................................... 149
8.8.12 IAC Debug Event ........................................................................................................................ 149
8.8.12.1 IAC Exact Address Compare ............................................................................................... 149
8.8.12.2 IAC Range Address Compare ............................................................................................. 149
8.8.13 DAC Debug Event ....................................................................................................................... 150

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8.8.13.1 DAC Exact Address Compare ............................................................................................. 150
8.8.13.2 DAC Range Address Compare ............................................................................................ 151
8.8.13.3 DAC Applied to Cache Instructions ...................................................................................... 152
8.8.13.4 DAC Applied to String Instructions ....................................................................................... 153
8.8.14 Data Value Compare Debug Event ............................................................................................. 153
8.8.15 Imprecise Debug Event ............................................................................................................... 155
9. Instruction Set ............................................................................................................................... 157
9.1 Instruction Set Portability ........................................................................................................................ 157
9.2 Instruction Formats ................................................................................................................................. 157
9.3 Pseudocode ............................................................................................................................................ 158
9.3.1 Operator Precedence .................................................................................................................... 160
9.4 Register Usage ....................................................................................................................................... 160
9.5 Alphabetical Instruction Listing .............................................................................................................. 160
10. Register Summary ...................................................................................................................... 353
10.1 Reserved Registers .............................................................................................................................. 353
10.2 Reserved Fields .................................................................................................................................... 353
10.3 General Purpose Registers .................................................................................................................. 353
10.4 Machine State Register and Condition Register ................................................................................. 353
10.5 Special Purpose Registers ................................................................................................................... 354
10.6 Time Base Registers ............................................................................................................................ 355
10.7 Device Control Registers ...................................................................................................................... 356
Appendix A. Instruction Summary .................................................................................................. 357
A.1 Instruction Formats ................................................................................................................................ 357
A.1.1 Instruction Fields ........................................................................................................................... 357
A.1.2 Instruction Format Diagrams ......................................................................................................... 359
A.1.2.1 I-Form .................................................................................................................................... 360
A.1.2.2 B-Form ................................................................................................................................... 360
A.1.2.3 SC-Form ................................................................................................................................ 360
A.1.2.4 D-Form .................................................................................................................................. 360
A.1.2.5 X-Form ................................................................................................................................... 361
A.1.2.6 XL-Form ................................................................................................................................. 361
A.1.2.7 XFX-Form .............................................................................................................................. 362
A.1.2.8 X0-Form ................................................................................................................................. 362
A.1.2.9 M-Form .................................................................................................................................. 362
A.2 List of Implemented Instructions—Alphabetical .................................................................................... 362
A.3 List of Instructions—by Opcode ............................................................................................................ 388
Appendix B. Instructions by Category ............................................................................................ 395
B.1 Implementation-Specific Instructions ..................................................................................................... 395
B.2 Instructions in the PowerPC Embedded Environment .......................................................................... 398
B.3 Privileged Instructions ........................................................................................................................... 400
B.4 Assembler Extended Mnemonics .......................................................................................................... 402
B.5 Storage Reference Instructions ............................................................................................................. 417
B.6 Arithmetic and Logical Instructions ........................................................................................................ 420
B.7 Condition Register Logical Instructions ................................................................................................. 424
B.8 Branch Instructions ................................................................................................................................ 424
B.9 Comparison Instructions ........................................................................................................................ 425
B.10 Rotate and Shift Instructions ............................................................................................................... 426
B.11 Cache Control Instructions .................................................................................................................. 427

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B.12 Interrupt Control Instructions ............................................................................................................... 427
B.13 TLB Management Instructions ............................................................................................................ 428
B.14 Processor Management Instructions ................................................................................................... 429
Appendix C. Code Optimization and Instruction Timings ........................................................... 430
C.1 Code Optimization Guidelines .............................................................................................................. 430
C.1.1 Condition Register Bits for Boolean Variables .............................................................................. 430
C.1.2 CR Logical Instruction for Compound Branches .......................................................................... 430
C.1.3 Cache Usage ................................................................................................................................ 430
C.1.4 CR Dependencies ........................................................................................................................ 431
C.1.5 Branch Prediction ......................................................................................................................... 431
C.1.6 Alignment ...................................................................................................................................... 431
C.2 Instruction Timings ................................................................................................................................ 431
C.2.1 General Rules ............................................................................................................................... 431
C.2.2 Branches ...................................................................................................................................... 432
C.2.3 Multiplies ....................................................................................................................................... 432
C.2.4 Scalar Load Instructions ............................................................................................................... 433
C.2.5 Scalar Store Instructions .............................................................................................................. 434
C.2.6 Alignment in Scalar Load and Store Instructions .......................................................................... 434
C.2.7 String and Multiple Instructions .................................................................................................... 434
C.2.8 Loads and Store Misses ............................................................................................................... 435
C.2.9 Instruction Cache Misses ............................................................................................................. 435
Index ................................................................................................................................................... 437
Revision Log ...................................................................................................................................... 449

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Figures
Figure 2-2. PPC405 Programming Model—Registers .......................................................................................34
Figure 2-1. PPC405 Programming Model—Registers .......................................................................................34
Figure 2-3. General Purpose Registers (GPR0-GPR31) ...................................................................................35
Figure 2-4. Count Register (CTR) ......................................................................................................................36
Figure 2-5. Link Register (LR) ............................................................................................................................37
Figure 2-6. Fixed Point Exception Register (XER) .............................................................................................38
Figure 2-7. Special Purpose Register General (SPRG0–SPRG7) ....................................................................39
Figure 2-8. Processor Version Register (PVR) ..................................................................................................39
Figure 2-9. Condition Register (CR) ..................................................................................................................40
Figure 2-10. PPC405 Data Types ........................................................................................................................42
Figure 2-11. Normal Word Load or Store (Big Endian Storage Region) ..............................................................48
Figure 2-12. Byte-Reverse Word Load or Store (Little Endian Storage Region) .................................................48
Figure 2-13. Byte-Reverse Word Load or Store (Big Endian Storage Region) ....................................................48
Figure 2-14. Normal Word Load or Store (Little Endian Storage Region) ...........................................................49
Figure 2-15. PPC405 Instruction Pipeline ............................................................................................................50
Figure 3-1. Instruction Flow ...............................................................................................................................70
Figure 3-2. Core Configuration Register 0 (CCR0) ............................................................................................77
Figure 3-3. Instruction Cache Debug Data Register (ICDBDR) .........................................................................80
Figure 4-1. OCM Address Usage .......................................................................................................................86
Figure 5-1. Effective-to-Real Address Translation Flow ....................................................................................92
Figure 5-2. TLB Entries ......................................................................................................................................93
Figure 5-3. ITLB/DTLB/UTLB Address Resolution ............................................................................................98
Figure 5-4. Process ID (PID) ............................................................................................................................102
Figure 5-5. Zone Protection Register (ZPR) ....................................................................................................103
Figure 5-6. Generic Storage Attribute Control Register ...................................................................................106
Figure 6-1. Machine State Register (MSR) ......................................................................................................114
Figure 6-2. Save/Restore Register 0 (SRR0) ..................................................................................................115
Figure 6-3. Save/Restore Register 1 (SRR1) ..................................................................................................115
Figure 6-4. Save/Restore Register 2 (SRR2) ..................................................................................................115
Figure 6-5. Save/Restore Register 3 (SRR3) ..................................................................................................116
Figure 6-6. Exception Vector Prefix Register (EVPR) ......................................................................................116
Figure 6-7. Exception Syndrome Register (ESR) ............................................................................................116
Figure 6-8. Data Exception Address Register (DEAR) ....................................................................................118
Figure 7-1. Relationship of Timer Facilities to the Time Base .........................................................................129
Figure 7-2. Time Base Lower (TBL) .................................................................................................................130
Figure 7-3. Time Base Upper (TBU) ................................................................................................................130
Figure 7-4. Programmable Interval Timer (PIT) ...............................................................................................132
Figure 7-5. Watchdog State Machine ..............................................................................................................133
Figure 7-6. Timer Status Register (TSR) .........................................................................................................135
Figure 7-7. Timer Control Register (TCR) ........................................................................................................136

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Figure 8-1. Debug Control Register 0 (DBCR0) ...............................................................................................143
Figure 8-2. Debug Control Register 1 (DBCR1) ...............................................................................................144
Figure 8-3. Debug Status Register (DBSR) .....................................................................................................145
Figure 8-4. Instruction Address Compare Registers (IAC1–IAC4) ...................................................................147
Figure 8-5. Data Address Compare Registers (DAC1–DAC2) .........................................................................147
Figure 8-6. Data Value Compare Registers (DVC1–DVC2) .............................................................................147
Figure 8-7. Inclusive IAC Range Address Compares .......................................................................................150
Figure 8-8. Exclusive IAC Range Address Compares .....................................................................................150
Figure 8-9. Inclusive DAC Range Address Compares .....................................................................................151
Figure 8-10. Exclusive DAC Range Address Compares ....................................................................................152

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Tables
Table 2-1. PPC405 SPRs .................................................................................................................................36
Table 2-2. XER[CA] Updating Instructions .......................................................................................................38
Table 2-3. XER[SO,OV] Updating Instructions .................................................................................................38
Table 2-4. Time Base Registers .......................................................................................................................41
Table 2-5. Alignment Exception Summary .......................................................................................................43
Table 2-6. Big Endian Mapping ........................................................................................................................46
Table 2-7. Little Endian Mapping ......................................................................................................................46
Table 2-8. Bits of the BO Field ..........................................................................................................................51
Table 2-9. Conditional Branch BO Field ...........................................................................................................52
Table 2-10. Example Memory Mapping ..............................................................................................................55
Table 2-11. Privileged Instructions .....................................................................................................................57
Table 2-12. PPC405 Instruction Set Summary ...................................................................................................61
Table 2-13. Implementation-specific Instructions ...............................................................................................62
Table 2-14. Storage Reference Instructions .......................................................................................................62
Table 2-15. Arithmetic Instructions .....................................................................................................................63
Table 2-16. Multiply-Accumulate and Multiply Halfword Instructions ..................................................................63
Table 2-17. Logical Instructions ..........................................................................................................................64
Table 2-18. Compare Instructions ......................................................................................................................64
Table 2-19. Branch Instructions ..........................................................................................................................64
Table 2-20. CR Logical Instructions ....................................................................................................................65
Table 2-21. Rotate Instructions ...........................................................................................................................65
Table 2-22. Shift Instructions ..............................................................................................................................65
Table 2-23. Cache Management Instructions .....................................................................................................66
Table 2-24. Interrupt Control Instructions ...........................................................................................................66
Table 2-25. TLB Management Instructions .........................................................................................................67
Table 2-26. Processor Control Instructions ........................................................................................................67
Table 3-1. Instruction Cache Organization .......................................................................................................70
Table 3-2. Data Cache Organization ................................................................................................................73
Table 3-3. Priority Changes With Different Data Cache Operations .................................................................82
Table 4-1. Examples of Store Data Bypass .....................................................................................................87
Table 5-1. TLB Fields Related to Page Size .....................................................................................................94
Table 5-2. Protection Applied to Cache Control Instructions ..........................................................................104
Table 6-1. Interrupt Handling Priorities ...........................................................................................................111
Table 6-2. Interrupt Vector Offsets .................................................................................................................113
Table 6-3. ESR Alteration by Various Interrupts .............................................................................................117
Table 6-4. Register Settings during Critical Input Interrupts ...........................................................................118
Table 6-5. Register Settings during Machine Check—Instruction Interrupts ..................................................119
Table 6-6. Register Settings during Machine Check—Data Interrupts ...........................................................120
Table 6-7. Register Settings during Data Storage Interrupts ..........................................................................121
Table 6-8. Register Settings during Instruction Storage Interrupts .................................................................122

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Table 6-9. Register Settings during External Interrupts ..................................................................................122
Table 6-10. Alignment Interrupt Summary ........................................................................................................123
Table 6-11. Register Settings during Alignment Interrupts ...............................................................................123
Table 6-12. ESR Usage for Program Interrupts ................................................................................................123
Table 6-13. Register Settings during Program Interrupts ..................................................................................124
Table 6-14. Register Settings during System Call Interrupts ............................................................................125
Table 6-15. Register Settings during Programmable Interval Timer Interrupts .................................................125
Table 6-16. Register Settings during Fixed Interval Timer Interrupts ................................................................126
Table 6-17. Register Settings during Watchdog Timer Interrupts .....................................................................126
Table 6-18. Register Settings during Data TLB Miss Interrupts ........................................................................127
Table 6-19. Register Settings during Instruction TLB Miss Interrupts ...............................................................127
Table 6-20. SRR2 during Debug Interrupts .......................................................................................................128
Table 6-21. Register Settings during Debug Interrupts .....................................................................................128
Table 7-1. Time Base Access .........................................................................................................................130
Table 7-2. FIT Controls ...................................................................................................................................132
Table 7-3. Watchdog Timer Controls ..............................................................................................................133
Table 7-4. Watchdog Timer State Machine .....................................................................................................134
Table 8-1. JTAG Instructions ..........................................................................................................................138
Table 8-2. Debug Events ................................................................................................................................148
Table 8-3. DAC Applied to Cache Instructions ................................................................................................152
Table 8-4. Setting of DBSR Bits for DAC and DVC Events ............................................................................154
Table 8-5. Comparisons Based on DBCR1[DVnM] ........................................................................................154
Table 8-6. Comparisons for Aligned DVC Accesses .......................................................................................155
Table 8-7. Comparisons for Misaligned DVC Accesses .................................................................................155
Table 9-1. Implementation-Specific Instructions .............................................................................................157
Table 9-2. Operator Precedence .....................................................................................................................160
Table 9-3. Extended Mnemonics for addi .......................................................................................................164
Table 9-4. Extended Mnemonics for addic ......................................................................................................165
Table 9-5. Extended Mnemonics for addic. .....................................................................................................166
Table 9-6. Extended Mnemonics for addis ......................................................................................................167
Table 9-7. Extended Mnemonics for bc, bca, bcl, bcla ...................................................................................176
Table 9-8. Extended Mnemonics for bcctr, bcctrl ............................................................................................181
Table 9-9. Extended Mnemonics for bclr, bclrl ................................................................................................184
Table 9-10. Extended Mnemonics for cmp .......................................................................................................188
Table 9-11. Extended Mnemonics for cmpi ......................................................................................................189
Table 9-12. Extended Mnemonics for cmpl ......................................................................................................190
Table 9-13. Extended Mnemonics for cmpli .....................................................................................................191
Table 9-14. Extended Mnemonics for creqv .....................................................................................................195
Table 9-15. Extended Mnemonics for crnor ......................................................................................................197
Table 9-16. Extended Mnemonics for cror ........................................................................................................198
Table 9-17. Extended Mnemonics for crxor ......................................................................................................200

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Table 9-18. Transfer Bit Mnemonic Assignment ...............................................................................................262
Table 9-19. Extended Mnemonics for mfspr .....................................................................................................267
Table 9-20. Extended Mnemonics for mftb .......................................................................................................268
Table 9-21. Extended Mnemonics for mftb .......................................................................................................268
Table 9-22. Extended Mnemonics for mtcrf ......................................................................................................269
Table 9-23. Extended Mnemonics for mtspr .....................................................................................................273
Table 9-24. Extended Mnemonics for nor, nor. ................................................................................................292
Table 9-25. Extended Mnemonics for or, or. ....................................................................................................293
Table 9-26. Extended Mnemonics for ori ..........................................................................................................295
Table 9-27. Extended Mnemonics for rlwimi, rlwimi. .......................................................................................299
Table 9-28. Extended Mnemonics for rlwinm, rlwinm. ......................................................................................300
Table 9-29. Extended Mnemonics for rlwnm, rlwnm. .......................................................................................302
Table 9-30. Extended Mnemonics for subf, subf., subfo, subfo. .......................................................................327
Table 9-31. Extended Mnemonics for subfc, subfc., subfco, subfco. ...............................................................328
Table 9-32. Extended Mnemonics for tlbre .......................................................................................................336
Table 9-33. Extended Mnemonics for tlbwe .....................................................................................................340
Table 9-34. Extended Mnemonics for tw ..........................................................................................................342
Table 9-35. Extended Mnemonics for twi .........................................................................................................345
Table 10-1. PPC405 General Purpose Registers .............................................................................................353
Table 10-2. PPC405 General Purpose Registers .............................................................................................353
Table 10-3. Special Purpose Registers ............................................................................................................354
Table 10-4. Time Base Registers .....................................................................................................................356

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About This Book
This user’s manual provides the architectural overview, programming model, and detailed information about the
registers, the instruction set, and operations of the AMCC PowerPC™ 405 (PPC405) embedded processor. This
device contains a 32-bit reduced instruction set computer (RISC) processor.
The PPC405 RISC embedded processor features:
• PowerPC Architecture™
• Single-cycle execution for most instructions
• Instruction cache unit and data cache unit
• Support for little endian operation
• Interrupt interface for one critical and one non-critical interrupt signal
• JTAG interface
Who Should Use This Book
This book is for system hardware and software developers, and for application developers who need to understand
the PPC405. The audience should understand network processor design, network system design, operating
systems, RISC processing, and design for testability.

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How to Use This Book
This book describes the PPC405 device architecture, programming model, external interfaces, internal registers,
and instruction set. This book is organized as follows:
•Overview on page 21
•Programming Model on page 31
•Cache Operations on page 69
•Memory Management on page 91
•Interrupt Handling on page 109
•On-Chip Memory (OCM) on page 85
•Timer Facilities on page 129
•Debugging on page 137
•Instruction Set on page 157
•Register Summary on page 353
This book contains the following appendixes:
•Instruction Summary on page 357
•Instructions by Category on page 395
•Code Optimization and Instruction Timings on page 430
To help readers find material in these chapters, the book contains:
•Contents on page 3
•Figures on page 11
•Tables on page 13
•Index on page 437

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Conventions
The following is a list of notational conventions frequently used in this manual.
ActiveLow An overbar indicates an active-low signal.
nA decimal number
0xnA hexadecimal number
0bnA binary number
= Assignment
∧AND logical operator
¬NOT logical operator
∨OR logical operator
⊕Exclusive-OR (XOR) logical operator
+ Twos complement addition
– Twos complement subtraction, unary minus
×Multiplication
÷Division yielding a quotient
% Remainder of an integer division; (33 % 32) = 1.
|| Concatenation
=, ≠ Equal, not equal relations
<, > Signed comparison relations
, Unsigned comparison relations
if...then...else... Conditional execution; if condition then aelse b, where aand brepresent one or more
pseudocode statements. Indenting indicates the ranges of aand b. If bis null, the
else does not appear.
do Do loop. “to” and “by” clauses specify incrementing an iteration variable; “while” and
“until” clauses specify terminating conditions. Indenting indicates the scope of a loop.
leave Leave innermost do loop or do loop specified in a leave statement.
FLD An instruction or register field
FLDbA bit in a named instruction or register field
FLDb:b A range of bits in a named instruction or register field
FLDb,b, . . . A list of bits, by number or name, in a named instruction or register field
REGbA bit in a named register
REGb:b A range of bits in a named register
REGb,b, . . . A list of bits, by number or name, in a named register
REG[FLD] A field in a named register
REG[FLD, FLD . . .]A
list of fields in a named register
REG[FLD:FLD] A range of fields in a named register
<
u
>
u

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GPR(r) General Purpose Register (GPR) r, where 0 ≤r≤31.
(GPR(r)) The contents of GPR r, where 0 ≤r≤31.
DCR(DCRN) A Device Control Register (DCR) specified by the DCRF field in an mfdcr or mtdcr
instruction
SPR(SPRN) An SPR specified by the SPRF field in an mfspr or mtspr instruction
TBR(TBRN) A Time Base Register (TBR) specified by the TBRF field in an mftb instruction
GPRs RA, RB, . . .
(Rx) The contents of a GPR, where xis A, B, S, or T
(RA|0) The contents of the register RA or 0, if the RA field is 0.
CRFLD The field in the condition register pointed to by a field of an instruction.
c0:3 A 4-bit object used to store condition results in compare instructions.
nb The bit or bit value bis replicated ntimes.
xx Bit positions which are don’t-cares.
CEIL(x) Least integer ≥x.
EXTS(x) The result of extending xon the left with sign bits.
PC Program counter.
RESERVE Reserve bit; indicates whether a process has reserved a block of storage.
CIA Current instruction address; the 32-bit address of the instruction being described by
a sequence of pseudocode. This address is used to set the next instruction address
(NIA). Does not correspond to any architected register.
NIA Next instruction address; the 32-bit address of the next instruction to be executed. In
pseudocode, a successful branch is indicated by assigning a value to NIA. For
instructions that do not branch, the NIA is CIA +4.
MS(addr, n) The number of bytes represented by nat the location in main storage represented by
addr.
EA Effective address; the 32-bit address, derived by applying indexing or indirect
addressing rules to the specified operand, that specifies a location in main storage.
EAbA bit in an effective address.
EAb:b A range of bits in an effective address.
ROTL((RS),n) Rotate left; the contents of RS are shifted left the number of bits specified by n.
MASK(MB,ME) Mask having 1s in positions MB through ME (wrapping if MB > ME) and 0s
elsewhere.
instruction(EA) An instruction operating on a data or instruction cache block associated with an EA.