AMD AMD-761 Guide

Preliminary Information
AMD-761™ System
Controller
Software/BIOS Design Guide
Publication # 24081 Rev: D
Issue Date: February 2002

Preliminary Information
© 2001, 2002 Advanced Micro Devices, Inc. All rights reserved.
The contents of this document are provided in connection with Advanced
Micro Devices, Inc. (“AMD”) products. AMD makes no representations or
warranties with respect to the accuracy or completeness of the contents of
this publication and reserves the right to make changes to specifications and
product descriptions at any time without notice. No license, whether express,
implied, arising by estoppel or otherwise, to any intellectual property rights
is granted by this publication. Except as set forth in AMD’s Standard Terms
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any express or implied warranty, relating to its products including, but not
limited to, the implied warranty of merchantability, fitness for a particular
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AMD reserves the right to discontinue or make changes to its products at any
time without notice.
Trademarks
AMD, the AMD logo, AMD Athlon, and combinations thereof, AMD-751, AMD-760, AMD-761, AMD-762, and
AMD-766 are trademarks of Advanced Micro Devices, Inc.
Other product names used in this publication are for identification purposes only and may be trademarks of
their respective companies.

Table of Contents 3
24081D—February 2002 AMD-761™ System Controller Software/BIOS Design Guide
Preliminary Information
Contents
1Overview 1
1.1 General BIOS Initialization Requirements . . . . . . . . . . . . . . . 2
1.1.1 AMD-761™ Configuration Spaces . . . . . . . . . . . . . . . . . . 2
1.1.2 Special Configuration Sequencing Requirements . . . . 2
1.1.3 Power-On Reset Initialization . . . . . . . . . . . . . . . . . . . . . 4
1.1.4 Programming Reserved Bits . . . . . . . . . . . . . . . . . . . . . . 7
1.1.5 Power Management Considerations . . . . . . . . . . . . . . . . 7
1.2 Recommended AMD Athlon™ Processor
SYS_CONFIG Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2 AMD-761™ System Controller Programmer’s Interface 9
2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.1 Special Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.2 IACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2.3 PCI Configuration Accesses . . . . . . . . . . . . . . . . . . . . . 15
2.3 Address Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.1 Socket2000 Address Decoding . . . . . . . . . . . . . . . . . . . 16
2.3.2 PCI/AGP Master Address Decoding . . . . . . . . . . . . . . . 17
2.4 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.4.1 I/O Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.4.2 Configuration Register Access . . . . . . . . . . . . . . . . . . . 26
2.4.3 Device 0: PCI Configuration Registers . . . . . . . . . . . . . 27
2.4.4 Device 0, Function 1: DDR PDL
Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . 97
2.4.5 Device 1: PCI-to-PCI Bridge
Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . 117
2.5 Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 138
2.5.1 AMD-761 System Controller GART Cache
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
2.5.2 Memory-Mapped Register Map . . . . . . . . . . . . . . . . . . 140

4Table of Contents
AMD-761™ System Controller Software/BIOS Design Guide 24081D—February2002
Preliminary Information
3 DDR SDRAM Interface 149
3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
3.2 DDR DIMMS and DDR SDRAMs . . . . . . . . . . . . . . . . . . . . . 150
3.2.1 DDR Speed Grades . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
3.2.2 DDR DIMM Data from Serial Presence
Detect (SPD) Device . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
3.3 Memory Space Configuration . . . . . . . . . . . . . . . . . . . . . . . . 152
3.4 DDR Memory DIMM Timings . . . . . . . . . . . . . . . . . . . . . . . . 157
3.4.1 Memory Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
3.5 Additional Memory Controller Settings . . . . . . . . . . . . . . . 161
3.6 DRAM Mode/Status Settings . . . . . . . . . . . . . . . . . . . . . . . . 165
3.7 ECC and Memory Scrubbing . . . . . . . . . . . . . . . . . . . . . . . . . 169
3.7.1 ECC and Memory Scrubbing Configuration . . . . . . . 172
3.8 Programmable Delay Lines (PDL) . . . . . . . . . . . . . . . . . . . . 174
3.8.1 Manual PDL Window Detection . . . . . . . . . . . . . . . . . 180
3.9 DDR I/O Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
4 Power Management 185
4.1 C1 Halt State Requirements . . . . . . . . . . . . . . . . . . . . . . . . . 186
4.2 C2 Stop Grant State Requirements . . . . . . . . . . . . . . . . . . . 187
4.3 S1 Power-On Suspend State Requirements . . . . . . . . . . . . . 189
4.4 S3 Suspend to RAM State Requirements . . . . . . . . . . . . . . 190
4.4.1 STR Bit Control for S3 Support . . . . . . . . . . . . . . . . . . 191
4.5 Clock Throttling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
4.6 DDR DRAM Clock Enables . . . . . . . . . . . . . . . . . . . . . . . . . . 194

Table of Contents 5
24081D—February 2002 AMD-761™ System Controller Software/BIOS Design Guide
Preliminary Information
5 PCI Bus Interface 195
5.1 Delayed Transactions and Ordering Rules Usage . . . . . . . 195
5.1.1 Delayed Transactions and Target Latency . . . . . . . . 196
5.1.2 Transaction Ordering Rules . . . . . . . . . . . . . . . . . . . . 199
5.1.3 Special Arbitration Considerations
for the Southbridge . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
5.2 PCI Performance Optimization Options . . . . . . . . . . . . . . . . 202
5.2.1 Read Prefetching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
5.2.2 PCI Chaining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
5.2.3 PCI Bus Parking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
6AGPInterface 205
6.1 AGP Dynamic Compensation Requirements . . . . . . . . . . . . 205
6.1.1 The AGP 4X Dynamic Compensation Register . . . . . 206
6.1.2 Selection of 1.5- or 3.3-V AGP Signalling . . . . . . . . . . 207
6.2 Feature Override Bits for AGP Cards . . . . . . . . . . . . . . . . . 208
6.3 BIOS Initialization Requirements . . . . . . . . . . . . . . . . . . . . 209
6.4 AGP Miniport Driver Requirements . . . . . . . . . . . . . . . . . . 210
7 Recommended BIOS Settings 211
7.1 PCI Bus 0, Device 0, Function 0 Registers . . . . . . . . . . . . . 212
7.1.1 Example Settings for Memory Timing . . . . . . . . . . . . 218
7.1.2 Examples: AGP Compensation Register Settings
(0xB4-0xBB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
7.1.3 PCI Bus 0, Device 0, Function 1 Registers . . . . . . . . . 236
7.2 PCI Bus 0, Device 1, Function 0 Registers . . . . . . . . . . . . . 246

6Table of Contents
AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002
Preliminary Information

List of Figures 7
24081D—February 2002 AMD-761™ System Controller Software/BIOS Design Guide
Preliminary Information
List of Figures
Figure 1. AMD Athlon Processor Family Address Mapping . . . . . . . . . . 9
Figure 2. AMD Athlon Processor Family x86 Processor
Address Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 3. AMD-761 System Controller Logical Bus Hierarchy . . . . . . . 19
Figure 4. Two-Level GART Indexing . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Figure 5. Suspend to RAM (STR_Control) Bits Usage. . . . . . . . . . . . . 193
Figure 6. Example of System with Flag and Data Stored
across PCI Bus Domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

8List of Figures
AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002
Preliminary Information

List of Tables 9
24081D—February 2002 AMD-761™ System Controller Software/BIOS Design Guide
Preliminary Information
List of Tables
Table 1. AMD-761 System Controller Configuration Register
Bits Unknown at RESET# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 2. Recommended Settings for AMD Athlon Processor
SYSCFG Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. AMD-761 System Controller Socket2000 Memory Map . . . . . 10
Table 4. AMD Athlon Processor Special Cycle Encodings . . . . . . . . . . . 12
Table 5. I/O Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 6. Device 0, Function 0 Configuration Register Map . . . . . . . . . . 27
Table 7. AMD-761 System Controller SERR# Assertion Control
and Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 8. Wait State Settings for DRAM Timing Register . . . . . . . . . . . . 55
Table 9. I/O Pad Drive Strength and Input Type . . . . . . . . . . . . . . . . . . . 90
Table 10. DDR Memory Base Address Register Locations . . . . . . . . . . . . 95
Table 11. AMD-761 DRAM Addressing Modes . . . . . . . . . . . . . . . . . . . . . 96
Table 12. Device 0, Function 1 Configuration Register Map . . . . . . . . . . 97
Table 13. PDL Calibration Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 14. DDR PDL Configuration Register Locations. . . . . . . . . . . . . . 101
Table 15. Device 1 Configuration Register Map . . . . . . . . . . . . . . . . . . . 117
Table 16. AMD-761 System Controller Memory-Mapped Registers . . . 140
Table 17. Typical CL Parameter Settings for PC1600 and PC2100 . . . . 151
Table 18. DIMM Bank Address Bit Definition. . . . . . . . . . . . . . . . . . . . . 152
Table 19. Memory Size Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Table 20. Total Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 21. AMD-761 System Controller DDR SDRAM
Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Table 22. Memory Sizing Example, 128 Mbytes Total . . . . . . . . . . . . . . 156
Table 23. Memory Sizing Example, 320 Mbytes Total . . . . . . . . . . . . . . 157
Table 24. CAS Latency Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Table 25. DDR Device Timing Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Table 26. Dev 0:F0:0x54 Bit Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 27. System Related Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Table 28. Refresh Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

10 List of Tables
AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002
Preliminary Information
Table 29. AMD-761 System Controller ECC Behavior
(with ECC Enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Table 30. Default DQS Delay versus System Clock Frequency . . . . . . . 176
Table 31. AMD-761 System Controller Power Management
Features for ACPI Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Table 32. AMD-761 Processor System Controller PCI
Read Transaction Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Table 33. Allowable AGP Rate versus Signalling Level . . . . . . . . . . . . . 207
Table 34. AGP I/O Settings for 1.5- and 3.3-V Signalling . . . . . . . . . . . . 210

Revision History 11
24081D—February 2002 AMD-761™ System Controller Software/BIOS Design Guide
Preliminary Information
Revision History
Date Rev Description
2/2002 D
Text added in the following locations explaining that the registers must be saved and restored
when entering and exiting the S3 state:
 Section 1.1.5 on page 7, 2nd paragraph added
 Section 4 on page 185, first Note expanded
 Section 4.4 on page 190, paragraph two added
 Section 7 on page 211, paragraph added directly after last bullet in bulleted list
The following additional changes were incorporated:
 Table 34 on page 210, values for PSlewXfer and NSlewXfer changed from 01 and 00,
respectively, to 11 and 11
 Updated “Revision History”
8/2001 C Public release. Added bidirectional WSC# feature configuration register description.
4/2001 B Modified descriptions for WSC# and WSC# feature additions. NDA version only.
3/2001 A Initial public release.

12 Revision History
AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002
Preliminary Information

Chapter 1 Overview 1
24081D—February 2002 AMD-761™ System Controller Software/BIOS Design Guide
Preliminary Information
1 Overview
The AMD Athlon™ processor powers the next generation in computing
platforms, delivering the ultimate performance for cutting-edge
applications and an unprecedented computing experience.
The AMD-761™ system controller provides standard
Northbridge functionality for desktop personal computers
using the AMD Athlon™ family of processors. This
functionality includes the processor interface as well as PCI,
AGP, and main memory interface implementing state of the art
Double Data Rate (DDR) synchronous DRAM technology.
This document provides information typically required for
development of the system BIOS and device drivers to properly
program the AMD-761 system controller configuration
registers. The document is organized as follows:
 Section 1 provides an overview of the general BIOS
requirements for initializing the AMD-761 system controller
configuration registers.
 Section 2 on page 9 contains a description of all AMD-761
system controller configuration registers.
 Section 3 on page 149 contains additional information on
setup of the DDR SDRAM interface configuration registers.
 Section 4 on page 185 contains additional information on
configuration of the power management features of the
AMD-761 system controller.
 Section 5 on page 195 contains additional information on
setup of the PCI bus interface configuration registers.
 Section 6 on page 205 contains additional information on
setup of the AGP interface configuration registers.
 Section 7 on page 211 contains a list of recommended
settings for many of the AMD-761 system controller
configuration registers.

2Overview Chapter 1
AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002
Preliminary Information
1.1 General BIOS Initialization Requirements
The following sections provide general requirements for BIOS
when programming the AMD-761 system controller
configuration registers. Note that the register descriptions also
include some specific programming notes.
1.1.1 AMD-761™ Configuration Spaces
The AMD-761 system controller contains both I/O and memory-
mapped configuration spaces as listed below.
 I/O Mapped Space
•PCI configuration space address and data (CF8h, CFCh)
•Host bridge registers mapped in PCI configuration
space, device 0, function 0
•DDR interface PDL and I/O controls mapped in PCI
configuration space to device 0, function 1
•PCI to PCI bridge/AGP registers mapped in PCI
configuration space to device 1, function 0
 GART Memory-Mapped Registers
•Mapped in memory space as defined by the
programming of Base Address 1: GART Memory Mapped
Register Base
1.1.2 Special Configuration Sequencing Requirements
This section outlines a few cases in the AMD-761 system
controller configuration registers that require special handling
for proper BIOS programming.
Configuration Cycles
Enable
The AMD-761 system controller supports configuration
address space as defined by the PCI Local Bus Specification,
Revision 2.2, which defines a unique 256-byte space that is
accessed through two 32-bit index registers mapped in I/O
space.
As defined in the PCI specification, configuration cycles are
generated on the PCI bus only when bit 31 of the Configuration
Address register is set.

Chapter 1 Overview 3
24081D—February 2002 AMD-761™ System Controller Software/BIOS Design Guide
Preliminary Information
Function 1 Space The configuration registers that control the memory interface’s
Programmable Delay Lines (PDLs) and I/O drive strengths are
mapped to device 0: function 1 in the host bridge. This
configuration space is disabled by default and requires a write
to the PCI Control register’s Func1_En (Dev 0:F0:0x4C, bit 0).
The intent of this separate configuration space is that it is
configured at initial power-on, subsequently disabled, and
essentially protected from further writes.
 Note that the AMD-761 system controller does not report as
a multifunction device (bit 7 is not set in the Header_Type
field in the PCI Latency Timer and Header Type register in
Dev 0:F0:0x0C).
 Reads to the PCI header that normally occupies offsets 00h–
3Fh return all 1s—that is, the normal PCI header registers
are not implemented.
Memory-Mapped
BARs
Five DWORD registers are accessed by the AMD-761 system
controller AGP miniport driver as memory-mapped space. This
space is defined by the Base Address 1: GART Memory-
Mapped Register Base (Dev 0:F0:0x14), which provides address
bits [31:12] of the memory-mapped space. Note that this space
is defined as a 4-Kbyte region, hence the lower address bits
[11:4] are 0s.
This register must be properly programmed by BIOS to allow
the driver to access the memory-mapped space.
Memory Holes Legacy memory holes are decoded in the normal region of main
memory from 640 Kbyte to 1 Mbyte. The AMD-761 system
controller does not allow PCI masters to access DRAM in this
region unless the EV6_Mode bit is set in the PCI Arbitration
Control Register. See “Bit Definitions PCI Arbitration Control
(Dev0:F0:0x84)” on page 71.
AGP Override Bits
for 4X Rate
and Fast Writes
The AGP Status register (Dev 0:F0:0xA4) reports the AMD-761
system controller’s capability to support AGP fast writes and
the AGP-4X rate. The operating system normally reads these
bits along with the same bits in the AGP card’s status register,
and uses this information to configure the AGP Command
register (Dev 0:F0:0xA8) in the AMD-761 system controller and
the AGP card.

4Overview Chapter 1
AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002
Preliminary Information
The AMD-761 system controller provides BIOS the ability to
override the reporting of fast write and 4X rate support. This
override function is accomplished through a write to a separate
register, which is required because the AGP Status register is
specified as read-only in the AGP specification.
Refer to Section 6.2 on page 208 for details of this
implementation.
Interrupt Pin Control
R/W Attributes
The Int_Pin field in the AGP/PCI Interrupt and Bridge Control
register (Dev 1:F0:0x3C) is read-only by default and initializes
to all 0s. If the BIOS is required to initialize this field to
another value, it must first change this field to R/W by setting
the Int_Pin_Cntl bit in the Miscellaneous Device 1 Control
register (Dev 1:F0:0x40).
The AMD-761 system controller does not use the Int_Pin field
internally, the register is provided for software compatibility only.
Silicon Revisions The reader is advised to read the AMD-761™ System Controller
Revision Guide, order# 23613, for the most current information
for the version of silicon being used. The silicon revision is
available by reading the PCI revision ID and Class Code
register in Dev 0:F0:0x08.
1.1.3 Power-On Reset Initialization
All of the AMD-761 system controller’s configuration registers
must be initialized by BIOS after initial power-on, paying especially
close attention to the registers that are not initialized to a known
value.
The AMD-761 system controller is reset when the
Southbridge’s PCIRST# pin is asserted, which occurs when
transitioning from the Mechanical Off, S5, S4, or S3 sleep
states.
To accommodate support of the Advanced Configuration and
Power Interface (ACPI) S3 (suspend to RAM) power
management state, the registers listed in Table 1 on page 5 are
not initialized to a known state after reset (RESET# asserted),
and they must be initialized by BIOS after initial power-on for
proper operation. These registers retain the value programmed
by BIOS after subsequent assertions of the RESET# pin when
transitioning to and from the S3 sleep state.

Chapter 1 Overview 5
24081D—February 2002 AMD-761™ System Controller Software/BIOS Design Guide
Preliminary Information
Table 1. AMD-761™ System Controller Configuration Register Bits Unknown at RESET#
Register Name Offset Bit Name Bit(s)
ECC Mode/Status Dev 0:F0:0x48
SERR_Enable [15:14]
ECC_Diag [12]
ECC_Mode [11:10]
DRAM Timing Dev 0:F0:0x54
SBPWaitState [31]
Addr_Timing_A [30]
Addr_Timing_A [29]
RD_Wait_State [28]
Reg_DIMM_En [27]
tWTR [26]
tWR [25:24]
tRRD [23]
Idle_Cyc_Limit [18:16]
PH_Limit [15:14]
tRC [11:9]
tRP [8:7]
tRAS [6:4]
tCL [3:2]
tRCD [1:0]
DRAM Mode/Status Dev 0:F0:0x58
Burst_Ref_En [20]
Ref_Dis [19]
Reserved [18]
Cyc_Per_Ref [17:16]
CS7_X4Mode [7]
CS6_X4Mode [6]
CS5_X4Mode [5]
CS4_X4Mode [4]
CS3_X4Mode [3]
CS2_X4Mode [2]
CS1_X4Mode [1]
CS0_X4Mode [0]
Status/Control Dev 0:F0:0x70 Self_Ref_En [18]
Memory Base Address 0–7
Dev 0:F0:0xC0
through
Dev 0:F0:0xDC
CS_Base [31:23]
CS_Mask [15:7]
Addr_Mode [2:1]
CS_En [0]

6Overview Chapter 1
AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002
Preliminary Information
DDR PDL Calibration Control Dev 0:F1:0x40
SW_Recal [7]
Use_Act_Dly [6]
Auto_Cal_En [5]
Act_Dly_Inh [4]
Auto_Cal_Period [1:0]
DDR PDL Configuration 0–17
Dev 0:F1:0x44
through
Dev 0:F1:0x88
Clk_Dly [31:24]
SW_Cal_Dly [23:16]
Cal_Dly [15:8]
Act_Dly [7:0]
DDR DQS/MDAT Pad Configuration Dev 0:F1:0x8C
PSlewMDAT [29:27]
NSlewMDAT [26:24]
PDrvMDAT [19:18]
NDrvMDAT [17:16]
PSlewDQS [13:11]
NSlewDQS [10:8]
PDrvDQS [3:2]
NDrvDQS [1:0]
DDR CLK/CS Pad Configuration Dev 0:F1:0x90
PSlewCLK [29:27]
NSlewCLK [26:24]
PDrvCLK [19:18]
NDrvCLK [17:16]
PSlewCS [13:11]
NSlewCS [10:8]
PDrvCS [3:2]
NDrvCS [1:0]
DDR CMDB/CMDA Pad
Configuration Dev 0:F1:0x94
PSlewCMDB [29:27]
NSlewCMDB [26:24]
PDrvCMDB [19:18]
NDrvCMDB [17:16]
PSlewCMDA [13:11]
NSlewCMDA [10:8]
PDrvCMDA [3:2]
NDrvCMDA [1:0]
Table 1. AMD-761™ System Controller Configuration Register Bits Unknown at RESET# (Continued)
Register Name Offset Bit Name Bit(s)

Chapter 1 Overview 7
24081D—February 2002 AMD-761™ System Controller Software/BIOS Design Guide
Preliminary Information
Refer to Section 7 on page 211 for suggested values for these
configuration registers.
1.1.4 Programming Reserved Bits
The AMD-761 system controller has many bits that are
specified as reserved and which may be used in future silicon
revisions. BIOS must always write a 0 to these bits and not
depend on the value read back.
1.1.5 Power Management Considerations
There are several requirements for BIOS initialization of the
AMD-761 system controller’s configuration register when
supporting power management. Refer to Section 4 on page 185
for further details of these requirements.
For any system enabling the S3 state, a number of core logic
PCI configuration registers and processor MSRs must be saved
or restored prior to suspending or restoring S3. Also, certain
hidden bits must be unmasked. These requirements apply to all
platforms regardless of segment and whether or not AMD
PowerNow!™ is used.
DDR MAB/MAA Pad Configuration Dev 0:F1:0x98
PSlewMAB [29:27]
NSlewMAB [26:24]
PDrvMAB [19:18]
NDrvMAB [17:16]
PSlewMAA [13:11]
NSlewMAA [10:8]
PDrvMAA [3:2]
NDrvMAA [1:0]
Table 1. AMD-761™ System Controller Configuration Register Bits Unknown at RESET# (Continued)
Register Name Offset Bit Name Bit(s)

8Overview Chapter 1
AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002
Preliminary Information
1.2 Recommended AMD Athlon™ Processor
SYS_CONFIG Settings
Table 2 provides recommendations for settings in the
AMD Athlon processor System Configuration register in
systems that utilize the AMD-761 system controller.
Table 2. Recommended Settings for AMD Athlon™ Processor SYSCFG
Register
Bit Field Name BIOS
Setting Comments
[22] EvictEn 0
An Evict command, when set, is sent as
part of an INVD instruction. The Evict
command has no function in the
AMD-761™ system controller.
[17] SysUcLockEn 0
A LockToggle command, when set, is sent as
part of a LOCK instruction prefix and certain
other instructions. LockToggle has no
function in the AMD-761 system controller.
[16] ChxToDirtyDis 0 The AMD Athlon™ processor and the AMD-761 system controller support
Change-To-Dirty commands.
[13] SysFillValIsD1 0
[11] ClVicBlkEn 0
ClVicBlkEn, when set, causes all evicted
clean blocks to cause the CleanVictimBlk
system interface command. This setting
has no function with the AMD-761 system
controller.
[10:8]
SetDirtyEnE 0 There are three set-to-dirty enables: Set-
DirtyEnE, SetDirtyEnO, and SetDirtyEnS. If
a given enable is set and a cache block
must make a transition from E-to-M, O-to-
M, or S-to-M, then the AMD Athlon proces-
sor performs the action indicated by the
setting of the ChxToDirtyDis field. How-
ever, if a given enable is cleared, the pro-
cessor takes no externally visible action
when the desired transition is performed.
Change to dirty commands are not needed
by the AMD-761 system controller.
SetDirtyEnO 0
SetDirtyEnS 0