AMD AMD-761 Guide

Preliminary Information
AMD-761™ System
Controller
Software/BIOS Design Guide
Publication # 24081 Rev: D
Issue Date: February 2002

Preliminary Information
© 2001, 2002 Advanced Micro Devices, Inc. All rights reserved.
The contents of this document are provided in connection with Advanced
Micro Devices, Inc. (“AMD”) products. AMD makes no representations or
warranties with respect to the accuracy or completeness of the contents of
this publication and reserves the right to make changes to specifications and
product descriptions at any time without notice. No license, whether express,
implied, arising by estoppel or otherwise, to any intellectual property rights
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and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims
any express or implied warranty, relating to its products including, but not
limited to, the implied warranty of merchantability, fitness for a particular
purpose, or infringement of any intellectual property right.
AMD’s products are not designed, intended, authorized or warranted for use
as components in systems intended for surgical implant into the body, or in
other applications intended to support or sustain life, or in any other applica-
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sonal injury, death, or severe property or environmental damage may occur.
AMD reserves the right to discontinue or make changes to its products at any
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Trademarks
AMD, the AMD logo, AMD Athlon, and combinations thereof, AMD-751, AMD-760, AMD-761, AMD-762, and
AMD-766 are trademarks of Advanced Micro Devices, Inc.
Other product names used in this publication are for identification purposes only and may be trademarks of
their respective companies.

Table of Contents 3
24081D—February 2002 AMD-761™ System Controller Software/BIOS Design Guide
Preliminary Information
Contents
1Overview 1
1.1 General BIOS Initialization Requirements . . . . . . . . . . . . . . . 2
1.1.1 AMD-761™ Configuration Spaces . . . . . . . . . . . . . . . . . . 2
1.1.2 Special Configuration Sequencing Requirements . . . . 2
1.1.3 Power-On Reset Initialization . . . . . . . . . . . . . . . . . . . . . 4
1.1.4 Programming Reserved Bits . . . . . . . . . . . . . . . . . . . . . . 7
1.1.5 Power Management Considerations . . . . . . . . . . . . . . . . 7
1.2 Recommended AMD Athlon™ Processor
SYS_CONFIG Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2 AMD-761™ System Controller Programmer’s Interface 9
2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.1 Special Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.2 IACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2.3 PCI Configuration Accesses . . . . . . . . . . . . . . . . . . . . . 15
2.3 Address Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.1 Socket2000 Address Decoding . . . . . . . . . . . . . . . . . . . 16
2.3.2 PCI/AGP Master Address Decoding . . . . . . . . . . . . . . . 17
2.4 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.4.1 I/O Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.4.2 Configuration Register Access . . . . . . . . . . . . . . . . . . . 26
2.4.3 Device 0: PCI Configuration Registers . . . . . . . . . . . . . 27
2.4.4 Device 0, Function 1: DDR PDL
Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . 97
2.4.5 Device 1: PCI-to-PCI Bridge
Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . 117
2.5 Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 138
2.5.1 AMD-761 System Controller GART Cache
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
2.5.2 Memory-Mapped Register Map . . . . . . . . . . . . . . . . . . 140

4Table of Contents
AMD-761™ System Controller Software/BIOS Design Guide 24081D—February2002
Preliminary Information
3 DDR SDRAM Interface 149
3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
3.2 DDR DIMMS and DDR SDRAMs . . . . . . . . . . . . . . . . . . . . . 150
3.2.1 DDR Speed Grades . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
3.2.2 DDR DIMM Data from Serial Presence
Detect (SPD) Device . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
3.3 Memory Space Configuration . . . . . . . . . . . . . . . . . . . . . . . . 152
3.4 DDR Memory DIMM Timings . . . . . . . . . . . . . . . . . . . . . . . . 157
3.4.1 Memory Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
3.5 Additional Memory Controller Settings . . . . . . . . . . . . . . . 161
3.6 DRAM Mode/Status Settings . . . . . . . . . . . . . . . . . . . . . . . . 165
3.7 ECC and Memory Scrubbing . . . . . . . . . . . . . . . . . . . . . . . . . 169
3.7.1 ECC and Memory Scrubbing Configuration . . . . . . . 172
3.8 Programmable Delay Lines (PDL) . . . . . . . . . . . . . . . . . . . . 174
3.8.1 Manual PDL Window Detection . . . . . . . . . . . . . . . . . 180
3.9 DDR I/O Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
4 Power Management 185
4.1 C1 Halt State Requirements . . . . . . . . . . . . . . . . . . . . . . . . . 186
4.2 C2 Stop Grant State Requirements . . . . . . . . . . . . . . . . . . . 187
4.3 S1 Power-On Suspend State Requirements . . . . . . . . . . . . . 189
4.4 S3 Suspend to RAM State Requirements . . . . . . . . . . . . . . 190
4.4.1 STR Bit Control for S3 Support . . . . . . . . . . . . . . . . . . 191
4.5 Clock Throttling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
4.6 DDR DRAM Clock Enables . . . . . . . . . . . . . . . . . . . . . . . . . . 194

Table of Contents 5
24081D—February 2002 AMD-761™ System Controller Software/BIOS Design Guide
Preliminary Information
5 PCI Bus Interface 195
5.1 Delayed Transactions and Ordering Rules Usage . . . . . . . 195
5.1.1 Delayed Transactions and Target Latency . . . . . . . . 196
5.1.2 Transaction Ordering Rules . . . . . . . . . . . . . . . . . . . . 199
5.1.3 Special Arbitration Considerations
for the Southbridge . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
5.2 PCI Performance Optimization Options . . . . . . . . . . . . . . . . 202
5.2.1 Read Prefetching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
5.2.2 PCI Chaining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
5.2.3 PCI Bus Parking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
6AGPInterface 205
6.1 AGP Dynamic Compensation Requirements . . . . . . . . . . . . 205
6.1.1 The AGP 4X Dynamic Compensation Register . . . . . 206
6.1.2 Selection of 1.5- or 3.3-V AGP Signalling . . . . . . . . . . 207
6.2 Feature Override Bits for AGP Cards . . . . . . . . . . . . . . . . . 208
6.3 BIOS Initialization Requirements . . . . . . . . . . . . . . . . . . . . 209
6.4 AGP Miniport Driver Requirements . . . . . . . . . . . . . . . . . . 210
7 Recommended BIOS Settings 211
7.1 PCI Bus 0, Device 0, Function 0 Registers . . . . . . . . . . . . . 212
7.1.1 Example Settings for Memory Timing . . . . . . . . . . . . 218
7.1.2 Examples: AGP Compensation Register Settings
(0xB4-0xBB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
7.1.3 PCI Bus 0, Device 0, Function 1 Registers . . . . . . . . . 236
7.2 PCI Bus 0, Device 1, Function 0 Registers . . . . . . . . . . . . . 246

6Table of Contents
AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002
Preliminary Information

List of Figures 7
24081D—February 2002 AMD-761™ System Controller Software/BIOS Design Guide
Preliminary Information
List of Figures
Figure 1. AMD Athlon Processor Family Address Mapping . . . . . . . . . . 9
Figure 2. AMD Athlon Processor Family x86 Processor
Address Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 3. AMD-761 System Controller Logical Bus Hierarchy . . . . . . . 19
Figure 4. Two-Level GART Indexing . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Figure 5. Suspend to RAM (STR_Control) Bits Usage. . . . . . . . . . . . . 193
Figure 6. Example of System with Flag and Data Stored
across PCI Bus Domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

8List of Figures
AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002
Preliminary Information

List of Tables 9
24081D—February 2002 AMD-761™ System Controller Software/BIOS Design Guide
Preliminary Information
List of Tables
Table 1. AMD-761 System Controller Configuration Register
Bits Unknown at RESET# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 2. Recommended Settings for AMD Athlon Processor
SYSCFG Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. AMD-761 System Controller Socket2000 Memory Map . . . . . 10
Table 4. AMD Athlon Processor Special Cycle Encodings . . . . . . . . . . . 12
Table 5. I/O Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 6. Device 0, Function 0 Configuration Register Map . . . . . . . . . . 27
Table 7. AMD-761 System Controller SERR# Assertion Control
and Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 8. Wait State Settings for DRAM Timing Register . . . . . . . . . . . . 55
Table 9. I/O Pad Drive Strength and Input Type . . . . . . . . . . . . . . . . . . . 90
Table 10. DDR Memory Base Address Register Locations . . . . . . . . . . . . 95
Table 11. AMD-761 DRAM Addressing Modes . . . . . . . . . . . . . . . . . . . . . 96
Table 12. Device 0, Function 1 Configuration Register Map . . . . . . . . . . 97
Table 13. PDL Calibration Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 14. DDR PDL Configuration Register Locations. . . . . . . . . . . . . . 101
Table 15. Device 1 Configuration Register Map . . . . . . . . . . . . . . . . . . . 117
Table 16. AMD-761 System Controller Memory-Mapped Registers . . . 140
Table 17. Typical CL Parameter Settings for PC1600 and PC2100 . . . . 151
Table 18. DIMM Bank Address Bit Definition. . . . . . . . . . . . . . . . . . . . . 152
Table 19. Memory Size Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Table 20. Total Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 21. AMD-761 System Controller DDR SDRAM
Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Table 22. Memory Sizing Example, 128 Mbytes Total . . . . . . . . . . . . . . 156
Table 23. Memory Sizing Example, 320 Mbytes Total . . . . . . . . . . . . . . 157
Table 24. CAS Latency Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Table 25. DDR Device Timing Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Table 26. Dev 0:F0:0x54 Bit Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 27. System Related Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Table 28. Refresh Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

10 List of Tables
AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002
Preliminary Information
Table 29. AMD-761 System Controller ECC Behavior
(with ECC Enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Table 30. Default DQS Delay versus System Clock Frequency . . . . . . . 176
Table 31. AMD-761 System Controller Power Management
Features for ACPI Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Table 32. AMD-761 Processor System Controller PCI
Read Transaction Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Table 33. Allowable AGP Rate versus Signalling Level . . . . . . . . . . . . . 207
Table 34. AGP I/O Settings for 1.5- and 3.3-V Signalling . . . . . . . . . . . . 210