Analogic DBS 8700 Instructions for use

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Hardware User's Manual
I
-- ==-I
en
bus
DBS 8700/8701
VMEIVXI Data Acquisition System
The world ~esoun:;
for P~cisbnSignal Technology
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4 Programming
...................................
4.1 PROGRAMMINGOVERVIEW
4.2 DEFAULTDEVICE CONFIGURATION ......................
4.3 DRIVER FUNCTION DESCRIPTIONS .......................
4.3.1 OPEN(DEV. FLAG) .......................................
4.3.2 CLOSE (FID) .................................................
................... 4.3.3 WRITE (FID. BUFFER. COUNT)
.....................
4.3.4 READ (FID. BUFFER.COUNT)
.................. 4.3.5
IOCTL(FID. CMD. DATA. FLAG)
4.3.5.1 RESET ..........................................
4.3.5.2 RATE-DIVISOR ...........................
4.3.5.3 CLOCK-SOURCE ........................
.............................
4.3.5.4 START-MODE
4.3.5.5 RUN-AD-DIAGS ..........................
4.3.5.6 GET-DIAG-ERROR .....................
4.3.5.7 THRESHOLD ................................
4.3.5.8 TRIGGER-POLARITY ..................
4.3.5.9 READ-SRAM ................................
4.3.5.10 TIMEOUT ......................................
4.3.5.11 GET-ERROR ................................
4.3.5.1 2 PRE-POST-TRIGGER ................
4.3.5.13 THRESHOLD-TRIG .....................
4.3.5.14 PRE-TRIG-BUF-SZ ....................
4.3.5.1 5 SET-SIGNAL-TYPE ....................
4.3.5.1 6 READ-REG .................................
4.3.5.17 WRITE-REG ................................
4.4 ERROR HANDLING ...................................................
4.5 DATA ACQUISITION EXAMPLES .............................
4.5.1 SimpleAcquisition .........................................
4.5.2 PreIPostDataAcquisition ..............................
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Warranty
Analogicwarrants only tothe original purchaserthatthis product,as purchasedfrom Analogic
or anAnalogic distributor or dealer,will conformto the written specificationsfor a periodof one
year from the date of purchase. Ifthe product fails to conformto these warranties, Analogic,
as itssole and exclusive liability hereunder,will repairor replacethe productand/or its
componentswithina reasonableperiodof time
if the productis returnedto Analogic's facility at
Peabody,
MA, within the warranty period as expressedabove. These warranties are made
uponthe express condition that:
a. The purchaserpromptlynotifyAnalogic inwritingof any non-conformitywith the above
warranty including a detailed explanationof the allegeddeficiencies.
b. The productis returnedto Analogic at the buyer'sexpenseonly after obtainingthe proper
authorizationfrom Analogic.
c. When the productis returnedfor repair,a copy of the original bill of sale or invoiceissent
withthe product.
d. Analogicwill not be liablefor any incidentalor consequential damages.
e. Inthe opinion of Analogic uponinspection,the product has not been misused, altered, or
damaged dueto abnormalhandlingand/or operation.
f. Repairsto the product and/or its components have not beenmadeby anyone other than
Analogic or one of its authorized repairagents.
g. The producthas not beenmodified, altered,
or changedinany manner by anyone other
thanAnalogic or one of itsauthorizedrepair agents.
THISWARRANTY EXCLUDESALL OTHER WARRANTIES, WHETHER EXPRESSED OR
IMPLIED,ORALOR WRITTEN, INCLUDING WITHOUT LIMITATIONWARRANTIES OF
MERCHANTABILITYAND/OR FITNESS FOR A PARTICULAR PURPOSE.
Noterm, condition, understandingor agreement purportingto modifythe terms of this warranty
shallhave any legaleffectunless made inwritingandsigned by an authorized officer of
Analogic and the purchaser.
Ill
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5.2.6 Sampling Rate Select Register
(Baseaddress
+ 000AH) ...............................
5.2.7 Threshold Register
(Baseaddress
+ 001OH) ................................
........ 5.2.8
FIFO Register (Baseaddress + 001 2H)
5.2.9 AM9516 DMAController (DMAC) Pointer
................. Register (Baseaddress + 000CH)
5.2.10 AM951
6 DMAController (DMAC) Data
Register (Baseaddress
+ 000EH) .................
5.3 DMA OPERATIONS ...................................................
............................. 5.3.1 DMA Modesof Operation
5.3.2 DMAAddress Modifiers
.................................
5.4 INTERRUPTOPERATIONS .......................................
5.5 AM9516A PROGRAMMINGOVERVIEW ...................
5.5.1 Registers ........................................................
5.5.1.1 Chip-LevelRegisters
......... ; ..........
5.5.1.2 Channel-Level Registers ..............
5.5.2 Commands ....................................................
......................................................... 5.5.3 Chaining
5.5.4 Register Description
.......................................
5.5.4.1 Master Mode Register ..................
5.5.4.2 Command Register .......................
5.5.4.3 ChainControl Register ..................
5.5.4.4 Channel Mode Register ................
5.5.4.5 CurrentAddress Registers,A&B ..
5.5.4.6 BaseAddress Registers,A&B ......
5.5.4.7 Current Operation Count
Registers
.......................................
5.5.4.8 Base Operation Count ..................
5.5.4.9 Status Register ...................... ....
5.5.4.1 0 InterruptSave Register .................
5.5.4.11 ChainAddress Register ................
5.5.4.12 Chain ControlRegister ..................
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Contents
1 Introduction
1.1 SCOPEOF MANUAL ................................................. 1-1
1.2 PRODUCTDESCRIPTION
........................................ 1-1
1.3 TECHNICAL SUPPORT
............................................. 1-3
Hardware Installation
2.1 UNPACKING ..............................................................
................................
2.2 HARDWARECONFIGURATION
.......................................
2.2.1 VME SlaveAddress
2.2.2 Internal/ExternalClock
...................................
2.2.3 InternalIExternalTrigger ................................
2.2.4 DASDataOutput Format ...............................
2.2.5 VME Interrupt .................................................
2.2.6 TTLTRG Jumpers ..........................................
.........................................
2.2.7 RemoteTriggering
......................................
2.2.8 AnalogSignal Guard
.......................................
2.3 EXTERNALSIGNALINPUT
...............................................
2.3.1 Analog Signals
2.3.2 DigitalSignals
................................................
2.4 VMEBUS BACKPLANECONNECTIONS ..................
........... 2.4.1 BusGrant InloutBackplaneJumpers
2.4.2 IACKINIIACKOUTBackplaneJumper
...........
3 Software Installation
3.1 INTRODUCTION ........................................................ 3-1
.................................. 3.2 INSTALLATIONPROCEDURE 3-2
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List of Figures
Figure Page
.................................... 2-1 DBS 8701Jumper Selections 2-2
2-2 EXT TRIGvs . EXTSTARTTiming ............................ 2-8
................................................
3-1 Typical Directory Tree 3-1
..................................
5-1 DASFunctionalBlock Diagram 5-2
.............................................
5-3 ControlRegisterFormat 5-7
5-2 DeviceType RegisterFormat
.................................... 5-7
..............................................
5-4 Status Register Format 5-8
....................
5-5 Sequence RAMOffset Register Format 5-8
5-6 Scan Sequence RAMWord-Pair Format
................... 5-9
.......................................
5-7 GainIChannelWord Format 5-10
........................................
5-8 ChannelIPortWord Format 5-11
.....................................
5-9 Single Stage Delay Example 5-13
.........................................
5-1 0 Two Stage Delay Example 5-15
5-11 Three Stage Delay Example
...................................... 5-15
5-12 Single Stage Delay Examplewith S/H
....................... 5-17
.................
5-1 3 Memory DeviceAttribute Register Format 5-18
5-1
4 Sampling RateSelect Register .................................. 5-19
........................................
5-15 ThresholdRegister Format 5-20
...................................
5-1 6 Master Mode RegisterFormat 5-25
5-17 Chain Control Register
............................................... 5-27
.................................
5-18 Channel Mode RegisterFormat 5-27
5-19 Current Address Register(A
& B) Format ................. 5-29
5-20 Status Register Format
........................................... 5-30
..................................
5-21 InterruptSave Register Format 5-31
.................................
5-22 Chain Address RegisterFormat 5-31
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5 FunctionalDescription
................................................................
5.1 OVERVIEW
...........................................
5.1.1 Analog Front End
................................................
5.1.2 A/D Converter
5.1.3 Control Sequencer .........................................
........................................
5.1.4 VMENXI Interface
.........................
5.1.5 Power-Up Diagnostic Stimuli
5.1.6 DCIDC Converter ...........................................
...........................
5.2 HARDWARE DEVICE REGISTERS
DeviceIdentificationRegister
(Base address
+ 0000H) ................................
DeviceType Register
(Base address
+ 0002H) ................................
Control/StatusRegister
(Base address
+ 0004H) ...............................
Sequence RAM Offset Register
(Base address
+ 0006H) ................................
5.2.4.1 Loadingthe Scan
.............................
Sequence RAM
...................... 5.2.4.2 GainIChannelWord
....................... 5.2.4.3 ChannelIPortWord
5.2.4.4 A Typical Sequence
RAM LoadTable
...........................
5.2.4.5 SRAM Formatfor the DVX
Familyof Multiplexer Cards
..........
5.2.4.6 Order of Scan Restrictions ............
5.2.4.7
Exampleof SingleStageDelay ....
5.2.4.8 Exampleof Two Stage Delay .......
5.2.4.9 Exampleof Three Stage Delay .....
5.2.4.10 Exampleof a SingleStage Delay
with SamplelHold Multiplexer
.......
Memory DeviceAttribute Register
(Base address
+ 0008H) ...............................
vii
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DBS 8700/8701 Hardware User's Manual
Eight shielded, differential input ports are provided with both voltage
and current protection. The DAS is directly expandable
to 256
channelsusing the DVX family of multiplexer boards. The input port
signals are multiplexed via an instrumentation amplifier (IA) and a
programmable gain amplifier (PGA) with four software selectable
gains (1,2,4 and
8) and then fed into a 400 kHz, 16-bit sampling A/
D converter. The order of channelsin the scan, the selected gain for
each channel, the selected channel for data-dependent triggering as
well as the sampling rate are user programmable.
The converted data is temporarily stored in a 1024word deep FIFO.
When the FIFO is half full, it signals the powerful dual-channel on-
board DMA controller to acquire mastership of the bus. Then the
DMA controller executes fast transfers over the VME bus sending
data directly from the FIFO into the bus resident system memory
until the FIFO is empty. The DMA controller automatically reads the
necessary information regarding data set size and memory buffer
areas from the bus resident memory relieving the controlling micro-
processor of monitoring DMA operations.
Three flexible conversion trigger sourcesare available:
Q An internal trigger derived from a precision clock with acquisition
started by either the VMEbus resident host processor or the user
supplied External Start command.
Q A user supplied external trigger with acquisition started by either
the VMEbus resident host processor or the user supplied External
Start command.
Q An internally- or externally-derived trigger with the acquisition
started by the occurrence of a prespecified data dependent event
on a selected channel.
An external precision clock can be fed into the board via the Front
Panel
EXT TRIG BNC connector or ITLTRG line O,1,2or 3. The
'ITLTRG line is program selectable using the Rate Register (See
Section 5).
An external trigger can be fed to the DAS via the Front Panel EXT
START BNC connector or TTLTRG line 4,5,6or 7. The ?TLTRG
line is program selectable using the Rate Register (See Section
5).
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.......
5.5.5 Simple Exampleof the DMAOperations 5-32
5.5.6 Driver Excerptfor DMA Operations
............... 5-35
6 Specifications
Appendix
............................................
A.1 VMElVXl COMPLIANCE A-1
..........................
A.2 CONNECTOR PINASSIGNMENTS A-1
..........................
A.2.1 Analog Input Connector (Jl) A-1
..............................
A.2.2 VME BusConnector (PI) A-2
........................
A.2.3 VMElVXl BusConnector (P2) A-3
Appendix B
NOTESON DIELECTRICABSORPTION ............................
B-1
List of Tables
Table
................ BaseAddress Jumper SelectionExamples
Offset Binary Format
...................................................
Two's ComplementFormat .........................................
InterruptLevel Selections ...........................................
........................
TTLTRG Jumpersfor Control Signals
Master/SlaveJumper Selections
................................
....................
Analog Signal GuardJumper Selections
Analog Signal Input Connections
................................
......................................................
DASUNlX Drivers
.........................
Sequence RAM LoadTable Example
DMAC Registers
.........................................................
DAS Commands .........................................................
Page
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