Anaya Tech Systems ezTrainer User manual

ezTrainer
User Manual
FPGA MADE eAzY
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Anaya Tech Systems Pvt Ltd
ezTrainer FPGA Kit
User Manual Rev 1.0

ezTrainer
FGPAs made EAZY
User Manual
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Anaya Tech Systems Pvt Ltd
1.0 INTRODUCTION
Thanks for your support to help Anaya Tech Systems bring quality FPGA systems to you. The ezTrainer kit is a
valuable FPGA learning platform and helps you realize your digital and FPGA learning potentials.
1.1 KNOW YOUR BOARD
This kit comes to you along with all the required paraphernalia to help you kick start your FPGA designs. Here’s
a snap shot of the board, explaining the interfaces that you see:
Along with the board, you should have received:
- A 5V DC adapter to power the board (the board can also be USB powered)
- UART cable
- Ethernet cable
- USB cable
- A CD that contains our SW and the reference documents, along with some demo application codes.
VGA out
UART
MIC IN
SPK OUT
ETHERNET
USB
5V Adapter Input
Power Switch Reset Button
32 pin General
Purpose Header
LCD
Xilinx Spartan-3E
XC3S250E
Power, Done and
General Purpose LEDs

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As can be seen the board has been uniquely designed to:
- Help you learn basic and advanced digital design.
- Introduce technologies like USB, Ethernet, Audio etc. which are the most sought after in the industry today
- Learn Embedded design basics with flash, SDRAM and UART present on board.
- Port your DSP/multimedia applications with the FPGA supporting 250 K system gate, 12 Multipliers and 4
DCMs.
- Lets you interface you own “Custom” PCBs, general purpose boards to the 32 pin General purpose header
- The ezConnect SW lets you download your bit files to the FPGA without the need for a separate expensive
JTAG cable.
- Demo applications help you have a hands on to develop your own programs.
- The board is also available with a higher density option of XC3S500E, contact sales for details.
1.2 MAIN COMPONENTS
The board has the following main components:
• FPGA - Xilinx Spartan-3E XC3S250E, 208 pin PQFP package
• SPI Flash 8 Mbit - ST Microelectronics M25P80-VMW6
• SDRAM 128 Mbit - ISSI IS42S16800E
• USB Transceiver - FTDI FT2232H
• UART Transceiver - Maxim IX MAX3221
• Mono Audio Codec - TI TLV320AIC1106
• 10/100 Mbps Ethernet PHY - KSZ8041TL
• 16X2 character LCD Screen
• GPIO header that supports 15 differential pair or 32 single ended signals. Also contains VDD (3.3V) and
GND pins to help you power your custom PCBs
• The main design tool, XIlinx ISE (webpack edition), can be downloaded free of cost from www.xilinx.com.

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2.0 POWERING UP
The board can be powered up from a wall adapter with a DC output of 5V/1A. The adapter should have a center
pin of power +5V and outer part ground 0V. See below:
If you have the UART cable connected, a serial terminal shows up once the FPGA is loaded by the default
program present in the SPI flash. See the UART section for more details.
Optionally, the board can be powered up through USB. Change the jumper position JP200 (located to the left of
the power switch) to 2-3 to power up from USB. However, it is advisable that you power the board from the DC
wall adapter.
Green color LED200 indicates a successful power on.
Plug the adapter
cable here
Push switch left to power on

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FPGA MADE eAzY
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3.0 CLOCKS
The board has a 50 MHz clock oscillator fed to the pin 83 (Global Clock 3) of the FPGA. This can act as a
primary input for all your programs. A secondary clock can also be fed from the general purpose header pin 95
to the pin 80 (Global Clock 0) of the FPGA.

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4.0 CONFIGURATION OPTIONS
The FPGA can be programmed by TWO different methods:
4.1 DIRECT JTAG PROGRAMMING
All FPGAs on the market today support the standard JTAG interface for downloading a bit image file. You can
program the FPGA through our ezConnect software. Check for the following jumper settings before proceeding:
Jumpers shown in the figure JP400/401/402/403 should all be connected with pin 2 shorted to pin 3 (default
option given when the boards are shipped). Connect the USB cable and power on the board.
The JTAG configuration window of the software ezConnect is shown below. The software allows you to
download files in ________ and ________ formats:

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User Manual
FPGA MADE eAzY
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You can still use traditional JTAG cable to program the FPGA through the connector J305, see figures below for
pin details and location of J305
4.2 SPI PROGRAMMING
The board comes loaded with a default program in the SPI flash that can load the FPGA to run some test pro-
grams. However, ezConnect allows you to modify this flash and store your own programs. Note that the settings
for this should be the shorting of pins 1-2 on jumpers JP400/401/402/403. Also, you need to remove the default
jumpers present on J400 that short pins 1-2 and 3-4. See in the figure below. Once jumpers are removed, con-
nect the USB cable and power on the board

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The SPI configuration window of ezConnect is shown below:
Once the flash is programmed, you can remove jumpers from JP400/401/402/403. Put the jumpers back on
J400. Power up the board, and FPGA should now come up with your new image.
4.3 DONE PIN LED
Once the FPGA is programmed, a successful programming is indicated by the DONE pin going high. This is
indicated by LED400 on the board getting ON. All LEDs are located on the right of the board. See below:

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5.0 INTERFACE DETAILS
Sections below describe all interfaces of the FPGA in detail:
5.1 USB INTERFACE
A USB device FT2232H from FTDI provides the following functionalities on board
• helps to program the FPGA through JTAG
• helps to program the SPI flash on board
• Helps to download files into the on-board SDRAM (we provide sample code for this, or you can develop your
own codes)
Datasheet of this device is available on www.ftdichip.com. Table below describes the FPGA pin connections
made to this device to enhance your own development needs
5.2 SPI FLASH INTERFACE
A serial SPI flash of 8 Mbit is connected to the FPGA pins as shown in the table below. Datasheet of the flash
can be obtained from www.st.com.
Table 1:
Signal Names (as in FT2232) FPGA Pin FT2232H pin
D0 74 16
D1 75 17
D2 76 18
D3 77 19
D4 78 21
D5 89 22
D6 90 23
D7 93 24
RXF 91 26
TXE 94 27
RD 96 28
WR 97 29
SIWUA 98 30
CLKO 82 (GCLK2) 32
OE 60 33
Table 2:
Signal Names FPGA Pin M25P80 pin
SPI_DO 61 5
SPI_SK 103 6

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5.3 SDRAM INTERFACE
A 16-bit SDRAM of 128 Mbits is connected to the FPGA pins as shown in the table below. See datasheet of the
SDRAM at www.issi.com.
SPI_CS 55 1
SPI_DI 87 2
Table 3:
Signal Names FPGA Pin SDRAM pin
D0 25 2
D1 24 4
D2 23 5
D3 22 7
D4 19 8
D5 18 10
D6 16 11
D7 15 13
D8 12 42
D9 11 44
D10 9 45
D11 8 47
D12 5 48
D13 4 50
D14 3 51
D15 2 53
A0 69 23
A1 68 24
A2 65 25
A3 64 26
A4 63 29
A5 62 30
A6 50 31
A7 49 32
A8 48 33
A9 47 34
A10 45 22
Table 2:
Signal Names FPGA Pin M25P80 pin

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5.4 UART INTERFACE
A RS-232 transceiver is connected to the FPGA pins as shown in the table below. See datasheet of the
transceiver at www.maxim-ic.com.
5.5 AUDIO INTERFACE
A mono audio codec TLV320AIC1106 from texas instruments (www.ti.com) is connected to the FPGA to
provide an audio interface. 13-bit Linear as well as 9-bit u-law digital audio data is sent over the PCM interface
to the audio codec, which is then played over the speaker. Audio can also be captured over the MIC and sent
back to FPGA over PCM. Speaker Mute and code selection can be done through the jumpers JP301/300, see
below:
A11 42 35
A12 41 36
BA0 40 20
BA1 39 21
CS 34 19
CAS 36 17
RAS 33 18
WE 30 16
CKE 35 37
CLK 31 38
Table 4:
Signal Names FPGA Pin MAX3221 pin
T1N 178 11
R1OUT 175 9
Table 3:
Signal Names FPGA Pin SDRAM pin

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The connections from Audio codec to FPGA are shown in the table below:
You can connect your standard earphones (32 Ohm speaker) as well as desktop PC speakers (8 Ohm) to the
SPK interface. MIC interface is universal. Please take care to bring audio codec out of reset before any
communication can happen.
5.6 ETHERNET INTERFACE
A 10/100Base-TX Ethernet Transceiver device KSZ8041TL from Micrel (www.micrel.com) is connected to the
FPGA. The FPGA can have a simple Media Access Control (MAC) interface that talks to the transceiver over
Table 5:
Signal Names FPGA Pin CODEC pin
RESET 106 13
PCM_RX 181 16
PCM_TX 174 17
PCM_CLK 179 19
PCM_SYNC 180 18
MICMUTE 185 1

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the standard Reduced Media Independent Interface (RMII). See table below for connectivity:
Please note that the PHY should be out of reset through FPGA pin number 199, before any communication can
proceed.The Ethernet cable needs to be connected to the connector RJ300.
5.7 LCD INTERFACE
A standard 2-row (16 character each) LCD is connected to the FPGA as shown below. The LCD has to be used
in a 4-bit data format (only signals needed are RS, ENABLE, DB4-DB7. DB0-DB3 are not used.
5.8 VGA INTERFACE
A VGA monitor can be used to implement display projects using the FPGA. The interface from the FPGA to the
15-pin VGA connector is as shown below:
Table 6:
Signal Names FPGA Pin Transceiver pin
MDC 205 19
MDIO 206 18
TXEN 203 34
TXD0 202 35
TXD1 200 36
RXDV 204 27
RXD0 194 23
RXD1 184 22
RESET 199 47
CLOCK (50 MHz) 183 15
Table 7:
Signal Names FPGA Pin LCD pin
RS 205 4
ENABLE 206 6
DB4 203 11
DB5 202 12
DB6 200 13
DB7 204 14
Table 8:
Signal Names FPGA Pin VGA connector pin
RED 167 1
GREEN 168 2
BLUE 171 3

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5.9 GPIO INTERFACE
Many Engineering projects involve the control and automation of small custom PCBs that may be designed in
house. Some examples are projects needed for Robotics and control systems. For this purpose, we provide a
32-bit general purpose connector J301 where you connect these PCBs, and control them from the FPGA. As
an example, the FPGA’s UART interface can be used to take commands from a PC and control a Robot module
connected to the GPIO connector. The table below gives the pin assignments of the conector:
VERTICAL SYNC 172 14
HORIZONTAL SYNC 177 13
Table 9:
Signal Names FPGA Pin GPIO Connector pin
GPIO0 153 2
GPIO1 152 5
GPIO2 151 8
GPIO3 150 11
GPIO4 147 14
GPIO5 146 17
GPIO6 145 20
GPIO7 144 23
GPIO8 140 26
GPIO9 139 29
GPIO10 138 32
GPIO11 137 35
GPIO12 135 38
GPIO13 134 41
GPIO14 133 44
GPIO15 132 47
GPIO16 129 50
GPIO17 128 53
GPIO18 127 56
GPIO19 126 59
GPIO20 123 62
GPIO21 122 65
GPIO22 120 68
GPIO23 119 71
GPIO24 116 74
Table 8:
Signal Names FPGA Pin VGA connector pin

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Note that all these pins can be made input or output, except GPIO31 which always remains a Global clock input
of the FPGA. Also, signals are shown in pairs above. These can be used as differential pair of signals if needed.
The 32-bit connector location is shown in the board picture in section 1.1. Also note that the entire row of pins
on the board edge are 3.3V, and the entire inner row is 0V. A maximum of 1 Amp of current can be drawn from
this voltage to power your own boards. See also figure below:
5.10 LED INTERFACE
The FPGA pins drive eight general purpose green LEDs as shown in the table below. Drive the FPGA pin high
to lit the LED.
GPIO25 115 77
GPIO26 113 80
GPIO27 112 83
GPIO28 109 86
GPIO29 108 89
GPIO30 107 92
GPIO31/CLOCK 80 95
Table 9:
Signal Names FPGA Pin GPIO Connector pin
All outer row pins
All inner rown pins
are 0V
are 3.3V
All center rown pins
are GPIO signals

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Table 10:
Signal Names FPGA Pin
LED1 186
LED2 187
LED3 189
LED4 190
LED5 192
LED6 193
LED7 196
LED8 197

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6.0 DEMO APPLICATIONS
The CD also contains the source code (VHDL files) for the following demo applications with the board, you can
use these examples to develop any of your own projects. These demo codes are also easily integrated with our
USB interface controller (this comes to you in a synthesized form, so that you can merge this with your source
code to generate the final bit map).
6.1 SPI FLASH CONTROLLER
6.2 SDRAM CONTROLLER
6.3 AUDIO PLAYER CONTROLLER
6.4 UART CONTROLLER
6.5 LCD CONTROLLER
6.6 VGA CONTROLLER
6.7 BASIC EMBEDDED SYSTEM MODULE
6.8 TRAFFIC LIGHT CONTROLLER (USING ON-BOARD LEDS)
6.9 DSP FILTER IMPLEMENTATION FOR AUDIO