Aptina MT9T111 User manual

MT9T111: Developer Guide
About This Document
PDF: 4749051511/Source: 7788125767 Aptina reserves the right to change products or specifications without notice.
MT9T111_DG - Rev. B 9/10 EN 1©2007 Aptina Imaging Corporation. All rights reserved.
‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by Aptina without
notice. Products are only warranted by Aptina to meet Aptina’s production data sheet specifications.
Preliminary‡
1/4-Inch 3.1Mp System-On-A-Chip (SOC) CMOS
Digital Image Sensor
MT9T111
For the latest data sheet, refer to Aptina’s Web site: www.aptina.com
About This Document
This developer guide is a reference for hardware and software engineers developing
camera systems using the Aptina®MT9T111 CMOS digital image sensor. The MT9T111
isacompletesystem-on-a-chip(SOC)imagesensorthatintegratesseamlesslyintoday's
mobile phone applications. It incorporates sophisticated on-chip camera functions and
is programmable through a serial interface. This document provides information on
hardware interfaces, camera control, and register programming recommendations to
optimize image quality.
The system configuration section provides system-level information about the
MT9T111. This information is intended for module integrators or board-level design
engineers. It covers the MT9T111’s signal descriptions, system connections, power
supply configuration, and I/O signal states.
The architecture overview describes functions of each major block and their related
registerdescriptions inside theMT9T111.ItcoversthePLL,the two-wireserial interface,
the output interface, GPIO signals, andthe OTP memory.
The programming and operation section provides the programming procedure and
initialization process of the MT9T111. It covers how to access internal registers and vari-
ables using the two-wire serial interface. It also covers the power-on initialization
process, PLL programming, and standby mode operation. Example code is included.
The image signal processing flow and camera control section describes a variety of
featuresof the MT9MT111 including: auto focus (AF), anti-shaking, auto exposure (AE),
auto white balance (AWB), flicker detection (FD), JPEG output, lens shading correction
(LC), gamma correction, and context switching. Related registers are included.
The development tool overview provides steps to calibrate the MT9T111 for timing, lens
shading, and color tuning. It also covers how to use the Register Wizard and DevWare
tools.
There are two appendices that provide application examples for using the MT9T111 in a
dual camera system and in the demo board system environment. Appendix A describes
the system-level connections with a secondary sensor for dual camera mode. Appendix
B provides a high-level board-to-board interconnection description of the demo board
system.
Note: This developer guide is applicable to the MT9T111’s Rev3 silicon.

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MT9T111_DG - Rev. B 9/10 EN 2©2007 Aptina Imaging Corporation. All rights reserved.
MT9T111: Developer Guide
Introduction to Registers
Preliminary
Introduction to Registers
Thisdeveloperguidereferstovariousmemorylocationsandregistersthattheuserreads
from or writes to for altering the MT9T111 operation. Hardware registers appear as
followsandmay bereadorwrittenbysending theaddressanddata informationover the
two-wire serial interface.
Figure 1: Register Legend
Other memory locations are within the microcontroller block and may be accessed by
utilizing hardware registers from 0x098E through 0x0990 (see the MT9T111 data sheet
for further details on how to use these registers). These are denoted below:
Figure 2: Firmware Variable Legend
The MT9T111 was designed to facilitate customizations to optimize image quality pro-
cessing. As the image data travels through the various stages of image processing, the
user can adjust the parameters in these stages to affect the images' appearances. This
section describes most of these available adjustments.
Accessing the Firmware Drivers' Variables
R0x098E is used for the memory address and R0x0990 is used for data in the address.
Write Access
A write to the indirect access data register triggers a write to the targeted memory after
the two-wire serial interface has completed the WRITE cycle.
Read Access
Data is pre-fetched once the indirect access address register is updated; therefore, the
data is available when read from the indirect access data register.
R0x3024 [4:3]
Register # Register
Bit(s)
Indication of Register
(as opposed to driver variable)
driver.variable
Name of Firmware Driver Name of Driver’s Variable

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MT9T111_DG - Rev. B 9/10 EN 3©2007 Aptina Imaging Corporation. All rights reserved.
MT9T111: Developer Guide
Conventions and Notations
Preliminary
Refresh Mode and Refresh Commands
When some register values are changed, for example registers for cropping and
zooming, a refresh mode command (seq.seq_cmd = 6) and a refresh command
(seq.seq_cmd = 5) must be issued before the new settings will take effect. Aptina recom-
mends that the commands be issued sequentially (refresh mode then refresh). Refer to
the data sheet to determine which other registers need this command sequence.
MCU Memory
R0x098E[15:0], Indirect Access Address Register
R0x0990[15:0], Indirect Access Data Register
Conventions and Notations
This developer guide follows the conventions and notations described below.
• Hexadecimal numbers have 0x prefix
• Binary numbers have 0b prefix
Example: 0b1010 = 0xA
• Fixed point notation
0.8 (0.0 through 254/255)
1.7 (0.0 through 1 + 127/128)
• I/Osignalscan beLOW(0or DGND), HIGH (1 or VDD_IO), orfloating (highimpedance
or High-Z)
• Timing diagrams are notdrawn to scale and do not illustrate the actual number of
clocks necessary.
Table 1: R0x098E[15:0], Indirect Access Address Register
Bit Description
15 logical_word_access
This bit specifies the type of access.
0: Word access (2 bytes)
1: Byte access
14:10 This field specifies the driver number for the logical access.
9:0 This field specifies the offset for the logical access.

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MT9T111_DG - Rev. B 9/10 EN 4©2007 Aptina Imaging Corporation. All rights reserved.
MT9T111: Developer Guide
Table of Contents
Preliminary
Table of Contents
About This Document . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . ..1
Introduction to Registers. . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . .. . . . . . . . . . . . . . .2
Accessing the Firmware Drivers' Variables. . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . .2
Write Access . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . .2
Read Access. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . .. . . . . . . . . . . . . . .2
Refresh Mode and Refresh Commands . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .3
MCU Memory. . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .3
Conventions and Notations . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . .3
Overview . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . .11
System Configuration. . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .12
Signal Description. . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .14
I/O Signals . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . .16
Low-Noise Operation . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .18
Architecture Overview . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .19
PLL and Clock Divider . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .20
PIXCLK and DOUT[7:0] Timing . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .21
PLL Bypass Mode . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .24
Low Power Mode . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . .24
Example of Code to Program PLL and Clocks. . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .24
RX and TX FIFO Watermark . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . .26
Example of .ini File to Program the Watermark. . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .27
Output Slew Rate Control . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .28
GPIO Control . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . .29
Overview of GPIO Signals. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . .29
One-Time Programmable (OTP) Memory. . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .33
MT9T111 Rev3 Silicon OTP Memory Programming Procedure. . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . .34
Step 1: Sensor Setup . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .34
Step 2: Initialize the Sensor for OTP Memory Programming. . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .34
Step 3: Programming the Data . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . .. . . . . . . . . . . . . . . . . . . . . . . .34
Device ID. . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .36
Module ID . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .36
Master Two-Wire Serial Interface
and External Sensor Control Interface . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .37
Output Interface . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .38
JPEG Encoder. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .39
JPEG Encoding Highlights . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .39
JPEG Output Interface. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . .39
JPEG Data . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . .39
RGB Thumbnail. . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .40
JPEG Continuous Stream. . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . .41
JPEG Spoof Stream. . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . .42
JPEG Spoof Stream in MIPI Output Mode . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
JPEG Stream with Embedded Thumbnail Image . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . .. . . . . . . .44
Transfer Modes. . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .45
Bypass Mode. . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .45
Continuous Mode . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .45
Spoof Mode. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . .. . . . . . . . . . . . . .46
Thumbnail Index Table. . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .46
Thumbnail Index Pointer . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .. . .47
JPEG Status Segment. . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .47
Utilization of the Thumbnail Index Pointer. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .49

PDF: 4749051511/Source: 7788125767 Aptina reserves the right to change products or specifications without notice.
MT9T111_DG - Rev. B 9/10 EN 5©2007 Aptina Imaging Corporation. All rights reserved.
MT9T111: Developer Guide
Table of Contents
Preliminary
Original JPEG and Thumbnail Image Resolution . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .49
JPEG and Thumbnail Length Information . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . .. . .49
JPEG Status Information. . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . .50
Error Handling . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . .51
FIFO Underflow. . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .51
FIFO Overflow . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .. . . . . . . . . . .51
Frame Overflow . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . .51
Spoof Oversize Error. . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .52
Parallel Output Interface . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .52
Protocol . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . .52
Features . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . .52
Adaptive Clock Switching . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .. . .53
Output Interface Timing . . . . . . . . . . . . . . . .. . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . .54
Parallel Output Interface . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .54
Summary of Parallel Output Interface Options. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .54
JPEG Bypass Stream and Color Pipe Bypass Stream. . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .56
Case 1: Parallel Bypass Output with Clock Enabled. . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . .56
Case 2: Parallel Bypass Output with Clock Disabled Between Frames . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . .56
Case 3: Parallel Bypass Output with Clock Disabled Between Lines . . . . . . . . . . . . . . . . . . . . . . . .. . . . .. . . . . .57
Case 4: Parallel Bypass Output with Clock Disabled and CCIR Codes Inserted . . . . . . . . . . .. . . . . . . . . . . . . .57
JPEG Continuous Stream . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .58
Case 1: Parallel Output with Continuous Clock . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .58
Case 2: Parallel Output with Gated Clock. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .. . .59
Case 3: Parallel Output When LINE_VALID is Enabled During FRAME_VALID . . . . . . . . .. . . . . . . . . . . . . . . .59
Case 4: Parallel Output When SOI and EOI Are Enabled During FRAME_VALID. . . . . . . . . . . . . . . .. . . . . . . .60
Case 5: Parallel Output When SOI and EOI Are Enabled But Not During FRAME_VALID . . . . . . . . . . . . . . . .60
Case 6: Parallel Output with SOI/EOI, FRAME_VALID, and JPEG Status Inserted . . . . . . . . . . . . . . . . . . . .. . .61
Case 7: Parallel Output with Embedded Thumbnail Data . . . . . . . . . . . . . . .. . . . .. . . . . . . . . . . . . . . . . . . . . . . .61
Case 8: Parallel Output with Adaptive Clock Switching . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . .62
Case 9: Parallel Output with Adaptive Clock Switching andEmbedded Thumbnail Data . . . . .. . . . . . . . . . .62
Case 10: Parallel Output with Gated PIXCLK. . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .63
JPEG Spoof Stream. . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . .64
Case 1: PIXCLK Disabled Between Lines and Frames. . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .64
Case 2: PIXCLK EnabledBetween Lines But Disabled Between Frames. . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .65
Case 3: Thumbnail Stream with One Frame of Data . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .65
Case 4: Thumbnail Enabled with Less Than One Frame of Data . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .66
Case 5: Adaptive Clock Switching with PIXCLK Enabled Between Lines .. . . . . .. . . . . . . . . . . . . . . . . . . . .. . .66
Output Data Format. . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .67
Selecting Output Data Formats. . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Outputting Raw Bayer Data . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . .68
YUV Output. . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . .68
RGB Output. . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .69
Walking 1s Test Pattern . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . .70
Procedure . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . .71
Sensor Core Interface. . . . . . . . . . .. . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .72
Mirroring and Flipping the Image . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . .. . . . . . . .73
Image Test Pattern Generation . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .74
Programming and Operation . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . .75
Power-On Operation . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .77
Example of ini File for Power-On Sequence: . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . .77
Standby. . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .78
Entering Standby Mode . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .78
Exiting Standby Mode. . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .79

PDF: 4749051511/Source: 7788125767 Aptina reserves the right to change products or specifications without notice.
MT9T111_DG - Rev. B 9/10 EN 6©2007 Aptina Imaging Corporation. All rights reserved.
MT9T111: Developer Guide
Table of Contents
Preliminary
Timing Specifications. . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .80
Power-Up Sequence for Rev2 Silicon. . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . .80
Power-up Sequence for Rev3 Silicon . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . .81
Reset . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .82
Hard Reset . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . .82
Soft Reset. . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .83
Standby Modes . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . .84
Hard Standby with Shutdown Mode. . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .84
Hard Standby With Memory Retention Mode . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . .84
Soft Standby with State Retention. . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .. . .85
Image Signal Processing Flow and Camera Control . . . . . . . . . . .. . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .86
Context Switching and Output Configuration. . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .86
Setting up Preview (A) and Capture (B) Modes . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .87
Examples of Switching from One Context to Another. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . .87
Scaling. . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .88
Examples of .ini Settings for Different Output Resolutions . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . .88
Zoom. . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .89
Enabling Special Effects . . . . . .. . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .90
Examples of Programming for Special Effects . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .90
Auto Focus . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .91
AF Algorithm . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .91
AF Mode . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .92
Example of Programming Simple Full-Scan Triggering Operation. . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . .93
Anti-Shake. . . . . . . . . . . . . . . . . . .. . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .94
Introduction . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .94
Algorithm Description. . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .94
Configuration . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .95
Example of Settings for Anti-Shake . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . .95
Lens Shading Correction (LC) . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .97
Related Registers for the Lens Shading Algorithm . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .97
Example: PGA Values for LC. . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .97
Auto White Balance (AWB) . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . 100
Color Correction Procedure. . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . 100
AWB Procedure. . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . 101
Example: CCM Values for AWB. . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . 101
Auto Exposure (AE). . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. 103
Introduction . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . 103
AE Driver . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 103
Evaluation Algorithm. . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . 104
Accelerated Settling During Overexposure. . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 104
Exposure Control . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . . . . . . . . . . . . 104
Configuration . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . 104
Related Registers . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . 105
Example: AE Control . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . 105
Flicker Avoidance . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . 107
How to Use the Flicker Detection Driver . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
How to Fine-Tune the Anti-Flicker Driver Settings . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . 108
How to Verify the Anti-Flicker Driver Settings . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . 109
Gamma . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . .. . . . . . . . . . . . . . . . . . . . 110
Bright Scenes. . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . . . . . . . . . . . . 111
Dark Scenes. . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . 111
Gamma/Contrast Manual Control. . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. 112
Gamma/Contrast Automatic Control . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . .. . . . . . . . . . . . . . . .. . . . 112

PDF: 4749051511/Source: 7788125767 Aptina reserves the right to change products or specifications without notice.
MT9T111_DG - Rev. B 9/10 EN 7©2007 Aptina Imaging Corporation. All rights reserved.
MT9T111: Developer Guide
Table of Contents
Preliminary
Example: Gamma Control . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . 112
Development Tool Overview . . . . . . .. . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . 115
Register Wizard . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . 116
Procedure for Generating Frame TimingSetting . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .. . . . 116
Input Clock and PLL Output Frequencies . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . 116
Image Timing . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. 116
Register Wizard – Register Output . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. 117
Lens Calibration Procedure . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .. . . . . . 122
Equipment. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . 122
Setup . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . 122
Calibration Procedure. . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . 123
Using DevWare for the Lens Calibration. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . 125
Calibration Procedure Summary. . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .. . . . 128
Color Tuning Procedure . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . 129
Calibration of True Gray (TG) Limits . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . 139
Appendix A – Dual Camera Implementation . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . 141
Appendix B – Demo Board Systems . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . .. . . . 145
Revision History. . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 147

PDF: 4749051511/Source: 7788125767 Aptina reserves the right to change products or specifications without notice.
MT9T111_DG - Rev. B 9/10 EN 8©2007 Aptina Imaging Corporation. All rights reserved.
MT9T111: Developer Guide
List of Figures
Preliminary
List of Figures
Figure 1: Register Legend. . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . .2
Figure 2: Firmware Variable Legend . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . .2
Figure 3: Typical Configuration (connection). . . . . . . .. . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .12
Figure 4: SOC Block Diagram . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . .. . .19
Figure 5: Clock Distribution . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .. . . . . .22
Figure 6: Watermark Block Diagram . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .26
Figure 7: Output Slew Rate Defined. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .28
Figure 8: GPIO[0] . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .30
Figure 9: GPIO[1] . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .31
Figure 10: GPIO[2] . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .31
Figure 11: GPIO[3] . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .32
Figure 12: VGPIO[7:0] . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .32
Figure 13: Output Interface Block . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .38
Figure 14: JPEG Continuous Data Output . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .41
Figure 15: JPEG SOI and EOI Inserted. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .41
Figure 16: JPEG Spoof Mode Timing with Continuous Clock . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . .42
Figure 17: JPEG Spoof Mode Timing with Adaptive Clock . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .43
Figure 18: JPEG Spoof Mode Timing with Thumbnail. . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . .44
Figure 19: Contents of Status Segment . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . .47
Figure 20: JPEG Data Segment Structure . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .48
Figure 21: Timing of Parallel Bypass Output with Clock Enabled. . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . .56
Figure 22: Timing of Parallel Bypass Output with Clock Disabled Between Frames . . . . . . . . . . . .. . . . .. . . . . .56
Figure 23: Timing of Parallel Bypass Output with Clock Disabled Between Lines . . . . . . . . . . .. . . . . . . . . . . . . .57
Figure 24: Timing of ParallelBypass Output with Clock Disabledand CCIR Codes Inserted. . . . . . . . . . . . . . . .57
Figure 25: Timing of Parallel Output with ContinuousClock . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .58
Figure 26: Timing of Parallel Output with Gated Clock. . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . .59
Figure 27: Timing of Parallel Output with Gated Clock. . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . .59
Figure 28: Timing of Parallel Output When SOI and EOI Are Enabled DuringFRAME_VALID . . . . . . . . . . .. . .60
Figure 29: Timingof Parallel Output When SOI and EOI Are Enabled But Not During FRAME_VALID . . . . . .60
Figure 30: Timing of Parallel Output with SOI/EOI, FRAME_VALID, and JPEG Status Inserted . . . . . . . . . . . . .61
Figure 31: Timing of Parallel Output with Embedded Thumbnail Data . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .61
Figure 32: Timingof Parallel Output with Adaptive Clock Switching .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .62
Figure 33: Timing of Parallel Output with Adaptive Clock Switching and Embedded Thumbnail Data . . . . . .62
Figure 34: Timing of Parallel Output with Gated PIXCLK. . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .63
Figure 35: Timing of PIXCLK Disabled Between Lines and Frames . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .64
Figure 36: Timing of PIXCLK Enabled Between Lines But Disabled Between Frames. . . . . . . . . . .. . . . . . . . . . .65
Figure 37: Timing of Thumbnail Stream with One Frame of Data . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .65
Figure 38: Timing of Thumbnail Stream with Less Than One Frame of Data . . . . .. . . . . . . . . . . . . . . . . . . . .. . .66
Figure 39: Timing of Adaptive Clock Switching with PIXCLK Enabled Between Line . . . . . . . . . . . . . . . .. . . . . .66
Figure 40: Sample Operation on One Line. . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .70
Figure 41: Sample Operation for Multiple Lines with Horizontal Blanking . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .71
Figure 42: Spatial Illustration of Image Readout. . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .72
Figure 43: Register and Variable Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . .75
Figure 44: Power-Up Sequence Rev2 silicon . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . .80
Figure 45: Power-Up Sequence Rev3 silicon . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . .81
Figure 46: Hard Reset Signal Sequence. . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . .82
Figure 47: Soft Reset Signal Sequence. . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . .83
Figure 48: Hard Standby Signal Sequence Mode . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .84
Figure 49: Soft Standby Signal Sequence . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . .85
Figure 50: State Machine for Context Switching. . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .86
Figure 51: Auto Focus Functional Block Diagram . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .91
Figure 52: Full-Scan Mode AF. . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . .. . .92
Figure 53: Hill Climbing AF Mode . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .93
Figure 54: Anti-Shake Algorithm . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .94
Figure 55: Gamma Correction in Bright Scenes . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . 111
Figure 56: Gamma Correction in Dark Scenes. . . . . . . . . . . . . . . . . . .. . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . 111

PDF: 4749051511/Source: 7788125767 Aptina reserves the right to change products or specifications without notice.
MT9T111_DG - Rev. B 9/10 EN 9©2007 Aptina Imaging Corporation. All rights reserved.
MT9T111: Developer Guide
List of Figures
Preliminary
Figure 57: Development Tool Overview . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . 115
Figure 58: Register Wizard PLL Menu . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . 117
Figure 59: Lens Calibration Equipment Setup. . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 122
Figure 60: Check Image to See if it is Flipped Correctly. . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . 124
Figure 61: Lens Regions . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .. . . . 125
Figure 62: Sensor Array and Row Column Selection . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . 125
Figure 63: Lens Correction Curves. . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. 126
Figure 64: Curve Percentages . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . 127
Figure 65: Color Tuning Lab Setup . . . . . . . . . . . . . . . . . . . . . . .. . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . 129
Figure 66: Dual Camera System Level. . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . 141
Figure 67: Dual Camera Data Flow Diagram . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . 142
Figure 68: Dual Camera Typical Interconnect. . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . 143
Figure 69: Demo Board (Parallel Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . 145
Figure 70: Demo Board (Serial Mode). . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 146

PDF: 4749051511/Source:7788125767 Aptina reserves the right to change products or specifications without notice.
MT9T111_DG - Rev. B 9/10 EN 10 ©2007 Aptina Imaging Corporation. All rights reserved.
MT9T111: Developer Guide
List of Tables
Preliminary
List of Tables
Table 1: R0x098E[15:0], Indirect Access AddressRegister. . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . .3
Table 2: SignalDescriptions. . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . .14
Table 3: Attributes of I/O and Power Supply Signals . . . . . . . . . . . . . . . . . . .. . . . . .. . . . . . . . . . . . . . . . . . . . . . . .16
Table 4: Output Signal States During Reset and Standby . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .17
Table 5: Power Supply Descriptions . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . .18
Table 6: Recommended System Power Connections (5 pins) . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . .18
Table 7: Recommended System Power Connections (4 pins) . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . .18
Table 8: Polarity of PIXCLK . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . .21
Table 9: MT9T111 Clock Calculation Summary . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . .22
Table 10: PLL and Clock Related Registers and Variables . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .23
Table 11: Watermark Values to be Programmed. . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .26
Table 12: Slew Rate Control Related Registers. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . .28
Table 13: GPIO Related Registers and Variables . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .29
Table 14: GPIO Input / Output Multiplexer Control. . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .30
Table 15: Device ID Related Registers and Variables . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . .36
Table 16: Control of an External Secondary Sensor . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . .37
Table 17: Transfer Modes and Sources . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .45
Table 18: Resolution Field . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . .49
Table 19: JPEG Status Description . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .50
Table 20: Clock Switching Criteria . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . .53
Table 21: Parallel Output Interface Options. . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .54
Table 22: Changing Output Format Variables . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .67
Table 23: Output Format Option Configuration Settings . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Table 24: YCrCb Output Data Ordering. . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . .68
Table 25: RGB Ordering in Default Mode . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .. . .69
Table 26: Summary of MT9T111 Registers and Variables . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .76
Table 27: Standby Operation in Different Modes . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .78
Table 28: Power-Up Signal Timing for Rev2 Silicon . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .80
Table 29: Power-Up Signal Timing Rev3 Silicon . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .81
Table 30: Hard Reset Signal Timing . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . .82
Table 31: Soft Reset Signal Timing . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .83
Table 32: Hard Standby Signal Timing . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . .85
Table 33: Soft Standby Signal Timing. . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . .85
Table 34: Auto Focus ICs Supported by the MT9T111 . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .92
Table 35: Color Correction Matrix Structure . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. 100
Table 36: Recommended Equipment and Settings. . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . .. . . . 122

MT9T111: Developer Guide
Overview
PDF: 4749051511/Source:7788125767 Aptina eserves the right to change products or specifications without notice.
MT9T111_DG - Rev. B 9/10 EN 11 ©2007 Aptina Imaging Corporation All rights reserved.
Preliminary
Overview
The MT9T111 is a 3.1Mp CMOS sensor with Aptina’s the latest image signal processing
(ISP) and 1.75µm pixel technology. The MT9T111’s features include:
• 2048 x 1536 visible pixels in 1.75µm technology
• 30 fps maximum with 1024 x 768 YUV output
• 15 fps maximum with 2048 x 1536 JPEG output
• Parallel output, MIPI transmitter, MIPI receiver, and two-wire serial interface
• Dual camera support with the MT9V013 or the MT9V113
• Anti-Shake and auto focus features
• JPEG and thumbnail through parallel and MIPI output
• Fully enhanced next-generation ISP engine
• Hard standby, with and without memory retention
• Soft standby with memory retention

PDF: 4749051511/Source:7788125767 Aptina reserves the right to change products or specifications without notice.
MT9T111_DG - Rev. B 9/10 EN 12 ©2007 Aptina Imaging Corporation. All rights reserved.
MT9T111: Developer Guide
System Configuration
Preliminary
System Configuration
Figure 3 shows typical device connections for the MT9T111.
Figure 3: Typical Configuration (connection)
VAA
Analog
Power
SDATA
SCLK
FRAME_VALID
PIXCLK
LINE_VALID
STANDBY
GND_IO AGND
I/O
Power
Digital
Core
Power
VDD
PLL
Power
VDD_PLL
VAA6VAA_PIX6
Slave two-wire
serial interface
To parallel
camera
port
OR4
RPULL-UP5
RESET_BAR
VPP7
General purpose I/Os
(FLASH, OE_BAR,
D
OUT _LSB[1:0])
GPI0[3:0]3
SADDR
Standby mode
EXTCLK
External clock in
(6–54 MHz)
Active LOW reset
DGND
DOUT[7:0]
VDD
CLK_P
DOUT_P
CLK_N
To serial
camera
port
DOUT_N
V DD IO_TX2VAA_PIX
VDD_PLLVDDIO_RX
V
DD
IO_TX2
MIPI
Power
TX
VDD_IO VDD_VGPIO9
S DATA_ 2
SCLK_2
GND_VGPIO9
VGPI0[7:0]9
EXTCLK_OUT8
RESET_BAR_OUT8
STANDBY_OUT8
RX_DP8
RX_DN8
RX_CP8
RX_CN8
AF Control I/Os
V
DD
IO_RX
MIPI
Power
RX
GNDIO_TX2
GNDIO_RX
VDD_IO
From
external
Sensor
Master two-wire
serial interface
OTP memory
programming voltage

MT9T111: Developer Guide
System Configuration
PDF: 4749051511/Source:7788125767 Aptina eserves the right to change products or specifications without notice.
MT9T111_DG - Rev. B 9/10 EN 13 ©2007 Aptina Imaging Corporation All rights reserved.
Preliminary
Notes: 1. This typical configuration shows only one scenario (out of multiple possible variations) for this sensor.
2. If a MIPI Interface is not required, the VDDIO_TX and VDDIO_RX pads must be connected to VDD and the
GNDIO_TX and GNDIO_RX pads must be connected to DGND. The following signals must be left floating:
DOUT_P, DOUT_N, CLK_P, and CLK_N.
3. The GPIO pads can serve multiple features that can be reconfigured. The function and direction will vary
by applications.
4. Only one of the output modes (serial or parallel) can be used at any time.
5. Aptina recommends a resistor value of 1.5KΩ to VDD_IO for the two-wire serial interface RPULL-UP; how-
ever, greater values may be used for slower transmission speed.
6. VAA and VAA_PIX must be tied together.
7. VPP is the one-time programmable (OTP) memory programming voltage and should be left floating dur-
ing normal operation.
8. If the bridging function to the MT9V013 is not required, the following signals can be left floating:
EXTCLK_OUT, RESET_BAR_OUT, STANDBY_OUT, RX_DP, RX_DN, RX_CP, and RX_CN.
9. If auto focus (AF) is not required, the following pads can be left floating: VDD_VGPIO, GND_VGPIO, and
VGPIO[7:0].
10. Aptina recommends that 0.1μF and 1μF decoupling capacitors for each power supply are mounted as
close as possible to the pad. Actual values and results may vary, depending on layout and design consid-
erations.

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MT9T111_DG - Rev. B 9/10 EN 14 ©2007 Aptina Imaging Corporation. All rights reserved.
MT9T111: Developer Guide
Signal Description
Preliminary
Signal Description
Table 2 provides the signal descriptions for the MT9T111.
Table 2: Signal Descriptions
Name Type Description
STANDBY Input Controls sensor’s standby mode, active HIGH.
RESET_BAR Input Master reset signal, active LOW (can be left floating if not used).
EXTCLK Input Input clock signal 6–54 MHz.
RX_DN Input Differential MIPI data from the MT9V013 (sub-LVDS, negative) (must be left floating if not used).
RX_DP Input Differential MIPI data from the MT9V013 (sub-LVDS, positive) (must be left floating if not used).
RX_CN Input Differential MIPI clock from the MT9V013 (sub-LVDS, negative) (must be left floating if not used).
RX_CP Input Differential MIPI clock from the MT9V013 (sub-LVDS, positive) (must be left floating if not used).
VPP Input High voltage programming signal for anti-fuse of module ID and other features (must be left floating
for normal operation).
SCLK Input Slave two-wire serial interface clock from the host processor.
SADDR Input Selects device address for the slave two-wire serial interface. The address is 0x78 when SADDR is tied
LOW, 0x7A if tied HIGH.
SDATA I/O Slave two-wire serial interface data to and from the host processor.
SCLK_2 Output Master two-wire serial interface clock to the MT9V013 and peripheral devices, such as AF mechanics.
SDATA_2 I/O Master two-wire serial interface data to and from the MT9V013 and peripheral devices, such as AF
mechanics.
GPIO[3:0] I/O General purpose digital I/O, could be configured for FLASH/SHUTTER/DOUT_LSB0/DOUT_LSB1/
OE_BAR.
VGPIO[7:0] I/O General purpose digital I/O, used for AF function (can be left floating if not used).
DOUT[7:0] Output Eight-bit image data output or most significant bits (MSB) of 10-bit SOC bypass mode.
PIXCLK Output Pixel clock. Used for sampling DOUT, FRAME_VALID, and LINE_VALID.
LINE_VALID Output Identifies pixels in the active line.
FRAME_VALID Output Identifies rows in the active image.
DOUT_N Output Differential MIPI data (sub-LVDS, negative) (must be left floating if not used).
DOUT_P Output Differential MIPI data (sub-LVDS, positive) (must be left floating if not used).
CLK_N Output Differential MIPI clock (sub-LVDS, negative) (must be left floating if not used).
CLK_P Output Differential MIPI clock (sub-LVDS, positive) (must be left floating if not used).
RESET_BAR_OUT Output Master reset signal to the MT9V013, active LOW.
EXTCLK_OUT Output Input clock signal to the MT9V013.
STANDBY_OUT Output Standby mode control for the MT9V013, active HIGH.
VDD Supply Digital power (1.8V typical).
VAA_PIX Supply Pixel array power (2.8V typical).
VAA Supply Analog power (2.8V typical).
VDD_PLL Supply PLL power (2.8V typical).
VDD_IO Supply I/O power supply (1.8V or 2.8V typical).
GND_IO Supply I/O ground.
DGND Supply Digital ground.
AGND Supply Analog ground.
VDDIO_TX Supply I/O power supply for the MIPI output interface, 1.8V typical (must be connected to VDD, even if the
interface is not used).
GNDIO_TX Supply I/O ground supply for the MIPI output interface (must be connected to DGND even if the interface is
not used).

MT9T111: Developer Guide
Signal Description
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Preliminary
VDDIO_RX Supply I/O power supply for the MIPI input interface, 1.8V typical (must be connected to VDD, even if the
interface is not used).
GNDIO_RX Supply I/O ground supply for the MIPI input interface (must be connected to DGND, even if the interface is not
used).
VDD_VGPIO Supply I/O power supply for VGPIO[7:0] signals (can be left floating if the interface is not used).
GND_VGPIO Supply I/O ground for VGPIO[7:0].
Table 2: Signal Descriptions (continued)
Name Type Description

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MT9T111: Developer Guide
I/O Signals
Preliminary
I/O Signals
The MT9T111 has digital I/O signals like a typical CMOS circuit.
•I/Ovoltage(V
DD_IO) is separate from core voltages (VDD and VDD_PLL) and analog
voltages (VAA and VAA_PIX).
• If an input signal is not used, it must be tied to HIGH (VDD_IO) or LOW (DGND).
• Input signals with internal pull-up or pull-down resistors can be left floating (see
Table 3 for details).
• If an output signal is not used, leave it floating.
• If a bidirectional signal is not used, it must be either configured as an output, or if
configured as an input, it must be tied to either HIGH or LOW.
• Never exceed the absolute maximum electrical specification (refer to the electrical
specifications section of the MT9T111 data sheet).
In general, when VDD_IOis on,allthe input signalsmust be drivenbythe host, whilethe
output signals are driven bythe sensor. The MT9T111 implements a fail-safe I/O for all
I/O signals to prevent I/O failure when VDD_IO is not applied.
Ifsome of thefeaturesarenotused inthesensor,the inputsignalsmust beconnected to
either HIGH or LOW, as shown in Table 3.
Table 3: Attributes of I/O and Power Supply Signals
Signal Name Type Supply Reference
Fail–
Safe
I/O If Unused Slew Rate Hysteresis Input
Internal
Pull-Up/
Down
EXTCLK Input VDD_IO/DGND Yes N/A N/A Yes No
RESET_BAR Input VDD_IO/DGND Yes N/A N/A N/A Yes (PU)
SADDR Input VDD_IO/DGND Yes N/A N/A N/A No
SCLK Input VDD_IO/DGND Yes N/A N/A Yes No
STANDBY Input VDD_IO/DGND Yes DGND N/A N/A No
RX_DN Input VDDIO_RX/
GNDIO_RX
N/A No connection N/A N/A No
RX_DP Input VDDIO_RX/
GNDIO_RX
N/A No connection N/A N/A No
RX_CN Input VDDIO_RX/
GNDIO_RX
N/A No connection N/A N/A No
RX_CP Input VDDIO_RX/
GNDIO_RX
N/A No connection N/A N/A No
GPIO[3:0] I/O VDD_IO/DGND Yes DGND or VDD_IO R0x001E[6:4] N/A No
SDATA1I/O VDD_IO/DGND Yes N/A N/A Yes No
SDATA_21I/O VDD_IO/DGND N/A No connection N/A N/A No
VGPIO[7:0] I/O VDD_VGPIO/
GND_VGPIO
N/A No connection N/A N/A No
DOUT[7:0] Output VDD_IO/DGND Yes No connection R0x001E[2:0] N/A No
FRAME_VALID Output VDD_IO/DGND Yes No connection R0x001E[2:0] N/A No
LINE_VALID Output VDD_IO/DGND Yes No connection R0x001E[2:0] N/A No
PIXCLK Output VDD_IO/DGND Yes No connection R0x001E[10:8] N/A No
DOUT_P Output VDDIO_TX/
GNDIO_TX
N/A No connection N/A N/A No
DOUT_N Output VDDIO_TX/
GNDIO_TX
N/A No connection N/A N/A No

MT9T111: Developer Guide
I/O Signals
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MT9T111_DG - Rev. B 9/10 EN 17 ©2007 Aptina Imaging Corporation All rights reserved.
Preliminary
Notes: 1. Output is open drain.
Table 4 shows the MT9T111 output states during reset and standby.
CLK_P Output VDDIO_TX/
GNDIO_TX
N/A No connection N/A N/A No
CLK_N Output VDDIO_TX/
GNDIO_TX
N/A No connection N/A N/A No
SCLK_2 Output VDD_IO/DGND N/A No connection N/A N/A No
RESET_BAR_OUT Output VDD_IO/DGND N/A No connection N/A N/A No
EXTCLK_OUT Output VDD_IO/DGND N/A No connection N/A N/A No
STANDBY_OUT Output VDD_IO/DGND N/A No connection N/A N/A No
AGND Supply VAA, VAA_PIX N/A N/A N/A N/A No
DGND Supply VDD_IO/DGND N/A N/A N/A N/A No
VAA Supply AGND N/A N/A N/A N/A No
VAA_PIX Supply AGND N/A N/A N/A N/A No
VDD Supply DGND N/A N/A N/A N/A No
VDD_IO Supply DGND N/A N/A N/A N/A No
VDD_PLL Supply DGND N/A N/A N/A N/A No
VPP Supply DGND N/A No connection N/A N/A No
VDDIO_TX Supply GNDIO_TX N/A VDD N/A N/A No
GNDIO_TX Supply VDDIO_TX N/A DGND N/A N/A No
VDDIO_RX Supply GNDIO_RX N/A VDD N/A N/A No
GNDIO_RX Supply VDDIO_RX N/A DGND N/A N/A No
VDD_VGPIO Supply GND_VGPIO N/A No connection N/A N/A No
GND_VGPIO Supply VDD_VGPIO N/A No connection N/A N/A No
Table 4: Output Signal States During Reset and Standby
Signal Reset Standby
DOUT[7:0] High-Z High-Z
PIXCLK High-Z High-Z
LINE_VALID High-Z High-Z
FRAME_VALID High-Z High-Z
DATA_N 0 0
DATA_P 0 0
CLK_N 0 0
CLK_P 0 0
GPIO[3:0] High-Z High-Z
VGPIO[7:0] High-Z High-Z
RESET_BAR_OUT High-Z High-Z
EXTCLK_OUT High-Z High-Z
STANDBY_OUT High-Z High-Z
Table 3: Attributes of I/O and Power Supply Signals (continued)
Signal Name Type Supply Reference
Fail–
Safe
I/O If Unused Slew Rate Hysteresis Input
Internal
Pull-Up/
Down

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MT9T111: Developer Guide
I/O Signals
Preliminary
Low-Noise Operation
For low-noise operation, the MT9T111 requires separate power supplies for analog and
digital. Incoming digital and analog groundconductors need to be separated in the
imager module. Both power supply rails should be decoupled from ground, using capac-
itors located as close as possible to the die. The use of inductance filters is not recom-
mended on the power supplies or output signals.
The MT9T111 also supports different digital core, MIPI, and I/O power domains, as
shown in Table 5. The PLL and analog domains require clean power sources.
Notes: 1. DGND and GND_IO are tied together to meet ESD standards.
2. AGND and DGND are all isolated internally.
If there are five pins available for system power connections, Aptina recommends the
connections, as shown in Table 6.
If there are only four pins available forsystem power connections, Aptina recommends
the connections, as shown in Table 7.
Table 5: Power Supply Descriptions
Voltage Name Description Voltage Ground Reference Note
VDD Digital logic 1.8V DGND 1, 2
VDD_IO Input/output 1.8V or 2.8V GND_IO 1, 2
VPP OTP memory 8.5V DGND –
VDD_PLL PLL 2.8V DGND 2
VDDIO_Tx MIPI TX 1.8V GNDIO_TX –
VDDIO_RX MIPI RX 1.8V GNDIO_RX –
VDDIO_VGPIO VGPIO 2.8V GNDIO_VPGIO –
VAA Analog circuitry 2.8V AGND 2
VAA_PIX Pixel array 2.8V AGND 2
Table 6: Recommended System Power Connections (5 pins)
Pin Number Power/Ground Type Voltage Power Supply Signals
1 Digital power 1.8V VDD,VDDIO_TX, VDDIO_RX
2 Digital power 1.8V or 2.8V VDD_IO, VDDIO_VGPIO
3Analogpower2.8V V
AA,VAA_PIX,VDD_PLL
4D
GND DGND, GND_IO, GNDIO_TX, GNDIO_RX, GNDIO_VGPIO
5A
GND AGND
Table 7: Recommended System Power Connections (4 pins)
Pin Number Power Type Voltage Power Supply Signals
1 Digital power 1.8V VDD,VDD_IO, VDDIO_TX, VDDIO_RX, VDDIO_VGPIO
2 Analog power 2.8V VAA,VAA_PIX,VDD_PLL
3D
GND DGND, GND_IO, GNDIO_TX, GNDIO_RX, GNDIO_VGPIO
4A
GND AGND

MT9T111: Developer Guide
Architecture Overview
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MT9T111_DG - Rev. B 9/10 EN 19 ©2007 Aptina Imaging Corporation All rights reserved.
Preliminary
Architecture Overview
The MT9T111 combines a 3.1Mp sensor core with an image processor (image flow pipe-
line) to form a stand-alone solution that includes both image acquisition and
processing, as shown in Figure 4. Both the sensor core and the image flow pipeline have
internal registers that can be controlled by the user. In normal operation, an integrated
microcontrollerautonomously controlsmostaspects ofoperation.Theprocessed image
data is transmitted to the host system, either through a parallel bus or a serial data bus
through the output interface.
Figure 4: SOC Block Diagram
Output Interface
Parallel
Interface
MIPI
Transmitter
TX
FIFO
Sensor
MIPI
Receiver
External
Secondary
Sensor
(MT9V013)
or
(MT9V113)
MT9T013
Sensor
Core
MCU
Microcontroller
RAM
ROM
System Interface
Two wire
Interface
(Master)
GPIO
POR
PLL
Ima ge Flow
Processor
Color
Pipeline
Two wire
Interface
(Slave)
JPEG
MT9T111
Auto Focus
Module OTPM
RX
FIFO

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MT9T111: Developer Guide
PLL and Clock Divider
Preliminary
PLL and Clock Divider
The MT9T111 requires a single input clock source (EXTCLK) to operate. EXTCLK is used
as the reference clock to the PLL, which generates all the internal clocks. The sensor
provides three output clocks (PIXCLK, external sensor CLK, and MIPI CLK). PIXCLK is
used for the parallel output data bus, whereas the MIPICLK is used for the serial MIPI
output. The MT9T111 also provides the clock for an external sensor to be used in dual
camera applications.
ThePLL canacceptan inputclockwith afrequencybetween6 and54 MHz.APLL circuit
in the MT9T111 synthesizes an arbitrary clock frequency to be used as the time base
within the device. It allows flexible system design where the clock supplied to the device
through EXTCLK may be higher or lower than the desired PIXCLK output frequency.
On power-up, the PLL is bypassed and the MT9T111 initially runs off of the EXTCLK.
When the PLL is enabled, the MT9T111 uses the PLL output (VCO) clock to generate all
the internal clocks. All of the clocks shown in Figure 5 on page 22 are derived from the
VCO (see Table 10 on page 23). Table 9 on page 22 shows how to calculate the internal
clock frequencies.
The PLL dividerregisters mustbe programmed before the PLL isenabled. Aptina recom-
mends using the MT9T111’s Register Wizard (part of DevWare), a frame rate and timing
calculating tool, to generate the register values. The user only needs to specify input
clock frequency (EXTCLK), desired output clock frequency (PIXCLK), and frame rate
requirements.
The sensor clock will be calculated based on frame rate requirements. Based on sensor
clock frequency and the required pixel clock, the SOC clock frequencyis calculated. The
SOC clock frequency should be as low as possible to provide the lowest power consump-
tion, but still maintain continuous data flow from sensor to the output interface. A RX
FIFO and a TX FIFO with programmable watermarks allows for the continuous flow of
image data.
For programming the external sensor clock, refer to “Master Two-Wire Serial Interface
and External Sensor Control Interface” on page 37.
For more detailed programming of the sensor core clock with frame rate calculation,
refer to the MT9T013 1/4-Inch 3.1Mp CMOS digital image sensor data sheet.