ARTERY AT32F421 Series User manual

AT32F421 Series Reference Manual
2021.11.17Page 1 Ver 2.00
ARM®-based 32-bit Cortex®-M4 MCU with 16 to 64 KB Flash, sLib, 10 timers,
ADC, 7 communication interfaces
Feature
Core: ARM®32-bit Cortex®-M4F CPU
−120 MHz maximum frequency, with a
Memory Protection Unit (MPU), single-cycle
multiplication and hardware division
−DSP instructions
Memories
−16 to 64 KBytes of internal Flash memory
−4 Kbytes of boot code area used as a
Bootloader or as a general instruction/data
memory (one-time-configured)
−sLib: configurable part of main Flash set as a
library area with code executable but
secured, non-readable
−8 to 16 KBytes of SRAM
Clock, reset and power control
−2.4 V ~ 3.6 V application suppy and I/Os
−Power-on reset (POR)/ low-voltage reset
(LVR), and power voltage monitor (PVM)
−4 to 25 MHz crystal (HEXT)
−Internal 8 MHz factory-trimmed clock (HICK),
accuracy 1% at TA=25 °C, 2 % at TA=-40 to
+105 °C
−Internal 40 kHz RC oscillator
−32 kHz crystal oscillator (LEXT)
Low power
−Sleep, Deepsleep, and Standby modes
1 x 12-bit A/D converter (up to 15 input
channels)
−Conversion range: 0 V to 3.6 V
1 x COMP, 5 x external input channels
and 1 x internal reference voltage
channel
DMA: 5-channel DMA controller
−Peripherals supported: timers, ADC, I2S,
SPI, I2C and USART
Debug mode
−Serial wire debug (SWD) and JTAG
Up to 39 fast GPIOs
−All mapable to external interrupt vectors
−Almost5 V-tolerant
−All fast I/Os,registersaccessible with fAHBspeed
Up to 10 Timers (TMR)
−1 x 16-bit 7-channel advanced timer, 6-channel
PWM outout with dead-time generator and
emergencystop
−5 x 16-bit timers, each with 4 IC/OC/PWM or
pulse counter and encoder input
−1 x 16-bit basic timer
−2x Watchdog timers (WDTandWWDT)
−SysTick timer: 24-bit downcounter
ERTC: enhanced RTC
Up to 7 communication interfaces
−2 x I2C interfaces (SMBus/PMBus support)
−2x USARTs/UART (ISO7816 interface,LIN,
IrDA and modem control)
−2 x SPIs, both with I2S interface multiplexed
−Infrared transmitter
CRC Calculation Unit
96-bit ID (UID)
Packaging
−LQFP48 7 x 7 mm
−LQFP32 7 x 7 mm
−QFN32 5 x 5 mm
−QFN32 4 x 4 mm
−QFN28 4 x 4mm
−TSSOP20 6.5 x 4.4 mm
List of Models
Internal Flash
Model
64 KBytes
AT32F421C8T7, AT32F421K8T7
AT32F421K8U7, AT32F421K8U7-4
AT32F421F8P7, AT32F421G8U7
32 KBytes
AT32F421C6T7, AT32F421K6T7
AT32F421K6U7, AT32F421K6U7-4
AT32F421F6P7, AT32F421G6U7
16 KBytes
AT32F421C4T7, AT32F421K4T7
AT32F421K4U7, AT32F421K4U7-4
AT32F421F4P7, AT32F421G4U7

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Contents
1System architecture...................................................................... 24
1.1 System overview..........................................................................26
1.1.1 ARM CortexTM-M4 processor........................................................ 26
1.1.2 Bit band...................................................................................... 26
1.1.3 Interrupt and exception vectors .................................................... 28
1.1.4 System Tick (SysTick) ................................................................. 30
1.1.5 Reset ......................................................................................... 30
1.2 List of abbreviations for registers ..................................................32
1.3 Device characteristics information.................................................32
1.3.1 Flash memory size register .......................................................... 32
1.3.2 Device electronic signature.......................................................... 32
2Memory resources ........................................................................ 33
2.1 Internal memory address map.......................................................33
2.2 Flash memory..............................................................................34
2.3 SRAM memory.............................................................................34
2.4 Peripheral address map................................................................35
3Power control (PWC)..................................................................... 38
3.1 Introduction .................................................................................38
3.2 Main Features .............................................................................38
3.3 POR/LVR ....................................................................................39
3.4 Power voltage monitor (PVM)........................................................39
3.5 Power domain..............................................................................40
3.6 Power saving modes ....................................................................40
3.7 PWC registers .............................................................................42
3.7.1 Power control register (PWC_CTRL) ............................................ 42
3.7.2 Power control/status register (PWC_CTRLSTS) ............................ 43
3.7.3 Power control register 2 (PWC_CTRL2)........................................ 43
4Clock and reset manage (CRM) ..................................................... 44
4.1 Clock ..........................................................................................44

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4.1.1 Clock sources ............................................................................. 44
4.1.2 System clock............................................................................... 45
4.1.3 Peripheral clock .......................................................................... 45
4.1.4 Clock fail detector ....................................................................... 46
4.1.5 Auto step-by-step system clock switch.......................................... 46
4.1.6 Internal clock output.................................................................... 46
4.1.7 Interrupts.................................................................................... 46
4.2 Reset..........................................................................................46
4.2.1 System reset............................................................................... 46
4.2.2 Battery powered domain reset...................................................... 47
4.3 CRM registers .............................................................................47
4.3.1 Clock control register (CRM_CTRL).............................................. 48
4.3.2 Clock configuration register (CRM_CFG) ...................................... 49
4.3.3 Clock interrupt register (CRM_CLKINT) ........................................ 50
4.3.4 APB2 peripheral reset register (CRM_APB2RST) .......................... 51
4.3.5 APB1 peripheral reset register1 (CRM_APB1RST) ........................ 52
4.3.6 AHB peripheral clock enable register (CRM_AHBEN) .................... 53
4.3.7 APB2 peripheral clock enable register (CRM_APB2EN) ................. 54
4.3.8 APB1 peripheral clock enable register (CRM_APB1EN) ................. 55
4.3.9 Battery powered domain control register (CRM_BPDC).................. 56
4.3.10 Control/status register (CRM_CTRLSTS) ...................................... 56
4.3.11 AHB peripheral reset register (CRM_AHBRST) ............................. 57
4.3.12 PLL configuration register (CRM_PLL).......................................... 58
4.3.13 Additional register (CRM_MISC1)................................................. 58
4.3.14 Additional register (CRM_MISC2)................................................. 59
5Flash memory controller (FLASH)................................................. 60
5.1 FLASH introduction......................................................................60
5.2 Flash memory operation ...............................................................62
5.2.1 Unlock/lock ................................................................................. 62
5.2.2 Erase operation........................................................................... 62
5.2.3 Programming operation................................................................ 64
5.2.4 Read operation ........................................................................... 65
5.3 Main Flash memory extension area ...............................................65
5.4 User system data area ................................................................. 65

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5.4.1 Unlock/lock ................................................................................. 65
5.4.2 Erase operation........................................................................... 66
5.4.3 Programming operation................................................................ 67
5.4.4 Read operation ........................................................................... 68
5.5 Flash memory protection ..............................................................68
5.5.1 Access protection........................................................................ 68
5.5.2 Erase/program protection............................................................. 69
5.6 Special functions .........................................................................69
5.6.1 Security library settings ............................................................... 69
5.6.2 Bootloader code area used as Flash memory extension................. 70
5.6.3 CRC verify .................................................................................. 70
5.7 Flash memory registers ................................................................71
5.7.1 Flash performance select register (FLASH_PSR) .......................... 71
5.7.2 Flash unlock register (FLASH_UNLOCK) ...................................... 72
5.7.3 Flash user system data unlock register (FLASH_USD_UNLOCK) ... 72
5.7.4 Flash status register (FLASH_STS) .............................................. 72
5.7.5 Flash control register (FLASH_CTRL)........................................... 73
5.7.6 Flash address register (FLASH_ADDR) ........................................ 74
5.7.7 User system data register (FLASH_USD)...................................... 74
5.7.8 Erase/program protection status register (FLASH_EPPS) .............. 74
5.7.9 Flash security library status register0 (SLIB_STS0)....................... 75
5.7.10 Flash security library status register1 (SLIB_STS1)....................... 75
5.7.11 Security library password clear register (SLIB_PWD_CLR) ............ 75
5.7.12 Security library additional status register (SLIB_MISC_STS).......... 76
5.7.13 Flash CRC address register (FLASH_CRC_ARR) .......................... 76
5.7.14 Flash CRC control register (FLASH_CRC_CTRL) .......................... 76
5.7.15 Flash CRC check result register (FLASH_CRC_CHKR).................. 76
5.7.16 Security library password setting register (SLIB_SET_PWD).......... 77
5.7.17 Security library address setting register (SLIB_SET_RANGE) ........ 77
5.7.18 Flash extension memory security library setting register
(EM_SLIB_SET).................................................................................... 78
5.7.19 Boot mode setting register (BTM_MODE_SET) ............................. 78
5.7.20 Security library unlock register (FLASH_UNLOCK) ........................ 78
6General-purpose I/Os (GPIOs)....................................................... 79

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6.1 Introduction .................................................................................79
6.2 Functional overview .....................................................................79
6.2.1 GPIO structure ............................................................................ 79
6.2.2 GPIO reset status........................................................................ 79
6.2.3 General-purpose input configuration............................................. 80
6.2.4 Analog input/output configuration ................................................. 80
6.2.5 General-purpose output configuration........................................... 80
6.2.6 GPIO port protection ................................................................... 80
6.2.7 IOMUX structure ......................................................................... 81
6.2.8 Multiplexed function input configuration ........................................ 81
6.2.9 IOMUX function input/output ........................................................ 82
6.2.10 Peripheral multiplexed function configuration ................................ 84
6.2.11 IOMUX map priority ..................................................................... 84
6.2.12 External interrupt/wake-up lines ................................................... 84
6.3 GPIO registers.............................................................................84
6.3.1 GPIO configuration register (GPIOx_CFGR) (x=A…H) ................... 85
6.3.2 GPIO input mode register (GPIOx_OMODE) (x=A…H) ................... 85
6.3.3 GPIO drive capability register (GPIOx_ODRVR) (x=A..H)............... 85
6.3.4 GPIO pull-up/pull-down register (GPIOx_PULL) (x=A..H) ............... 85
6.3.5 GPIO input data register (GPIOx_IDT) (x=A…H) ........................... 86
6.3.6 GPIO output data register (GPIOx_ODT) (x= A…H) ....................... 86
6.3.7 GPIO set/clear register (GPIOx_SCR) (x=A…H) ............................ 86
6.3.8 GPIO write protection register (GPIOx_WPR) (x=A…H) ................. 86
6.3.9 GPIO multiplexed function low register (GPIOx_MUXL) (x=A..H) .... 87
6.3.10 GPIO multiplexed function high register (GPIOx_MUXH) (x=A..H) .. 87
6.3.11 GPIO bit clear register (GPIOx_CLR) (x=A…H) ............................. 87
6.3.12 GPIO huge current control register (GPIOx_HDRV) (x=A..H).......... 87
7System configuration controller (SCFG) ....................................... 88
7.1 Introduction .................................................................................88
7.2 SCFG registers............................................................................88
7.2.1 SCFG configuration register1 (SCFG_CFG1) ................................ 88
7.2.2 SCFG external interrupt configuration register1 (SCFG_ EXINTC1) 89
7.2.3 SCFG external interrupt configuration register2 (SCFG_ EXINTC2) 90
7.2.4 SCFG external interrupt configuration register3 (SCFG_ EXINTC3) 90

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7.2.5 SCFG external interrupt configuration register4 (SCFG_ EXINTC4) 91
8External interrupt/Event controller (EXINT) .................................. 92
8.1 EXINT introduction.......................................................................92
8.2 Function overview and configuration procedure ..............................92
8.3 EXINT registers ...........................................................................93
8.3.1 Interrupt enable register (EXINT_INTEN)...................................... 93
8.3.2 Event enable register (EXINT_EVTEN) ......................................... 93
8.3.3 Polarity configuration register1 (EXINT_POLCFG1)....................... 93
8.3.4 Polarity configuration register2 (EXINT_POLCFG2)....................... 94
8.3.5 Software trigger register (EXINT_ SWTRG)................................... 94
8.3.6 Interrupt status register (EXINT_ INTSTS) .................................... 94
9DMA controller (DMA) ................................................................... 95
9.1 Introduction .................................................................................95
9.2 Main features ..............................................................................95
9.3 Functional overview .....................................................................95
9.3.1 DMA configuration....................................................................... 95
9.3.2 Handshake mechanism................................................................ 96
9.3.3 Arbiter ........................................................................................ 96
9.3.4 Programmable data transfer width ................................................ 97
9.3.5 Errors ......................................................................................... 98
9.3.6 Interrupts.................................................................................... 98
9.3.7 Fixed DMA request mapping ........................................................ 98
9.4 DMA registers..............................................................................99
9.4.1 DMA interrupt status register (DMA_STS)....................................100
9.4.2 DMA interrupt flag clear register (DMA_CLR)...............................101
9.4.3 DMA channel-x configuration register (DMA_CxCTRL) (x = 1…5) ..102
9.4.4 DMA channel-x number of data register (DMA_CxDTCNT)
(x = 1…5) ............................................................................................103
9.4.5 DMA channel-x peripheral address register (DMA_CxPADDR)
(x = 1…5) ............................................................................................103
9.4.6 DMA channel-x memory address register (DMA_CxMADDR)
(x = 1…5) ............................................................................................103
10 CRC calculation unit (CRC)......................................................... 104

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10.1 CRC introduction ....................................................................... 104
10.2 CRC registers............................................................................ 104
10.2.1 Data register (CRC_DT)..............................................................104
10.2.2 Common data register (CRC_CDT)..............................................104
10.2.3 Control register (CRC_CTRL)......................................................105
10.2.4 Initialization register (CRC_IDT) .................................................105
11 I2C interface ................................................................................ 106
11.1 I2C introduction.......................................................................... 106
11.2 I2C main features....................................................................... 106
11.3 I2C functional overview............................................................... 106
11.4 I2C interface .............................................................................. 107
11.4.1 I2C slave communication flow......................................................108
11.4.2 I2C master communication flow ...................................................111
11.4.3 Data transfer using DMA.............................................................117
11.4.4 SMBus.......................................................................................118
11.4.5 I2C interrupt requests .................................................................119
11.4.6 I2C debug mode .........................................................................120
11.5 I2C registers .............................................................................. 120
11.5.1 Control register1 (I2C_CTRL1)....................................................120
11.5.2 Control register2 (I2C_CTRL2)....................................................121
11.5.3 Own address register1 (I2C_OADDR1) ........................................122
11.5.4 Own address register2 (I2C_OADDR2) ........................................122
11.5.5 Data register (I2C_DT) ...............................................................123
11.5.6 Status register1 (I2C_STS1) .......................................................123
11.5.7 Status register2 (I2C_STS2) .......................................................125
11.5.8 Clock control register (I2C_ CLKCTRL) .......................................126
12 Universal synchronous/asynchronous receiver/transmitter (USART)127
12.1 USART introduction ................................................................... 127
12.2 Full-duplex/half-duplex selector .................................................. 129
12.3 Mode selector............................................................................ 129
12.3.1 Introduction................................................................................129
12.3.2 Configuration procedure .............................................................129
12.4 USART frame format and configuration........................................ 130

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12.5 DMA transfer introduction........................................................... 130
12.5.1 Transmission using DMA ............................................................130
12.5.2 Reception using DMA .................................................................130
12.6 Baud rate generation.................................................................. 131
12.6.1 Introduction................................................................................131
12.6.2 Configuration .............................................................................131
12.7 Transmitter................................................................................ 132
12.7.1 Transmitter introduction..............................................................132
12.7.2 Transmitter configuration ............................................................132
12.8 Receiver ................................................................................... 132
12.8.1 Receiver introduction..................................................................132
12.8.2 Receiver configuration................................................................133
12.8.3 Start bit and noise detection .......................................................134
12.9 Tx/Rx swap ............................................................................... 134
12.10Interrupt requests ...................................................................... 135
12.11I/O pin control............................................................................ 136
12.12USART registers........................................................................ 136
12.12.1 Status register (USART_STS) ..................................................137
12.12.2 Data register (USART_DT).......................................................138
12.12.3 Baud rate register (USART_BAUDR) ........................................138
12.12.4 Control register1 (USART_CTRL1) ...........................................138
12.12.5 Control register2 (USART_CTRL2) ...........................................139
12.12.6 Control register3 (USART_CTRL3) ...........................................140
12.12.7 Guard time and divider register (USART_GDIV) ........................141
13 Serial peripheral interface (SPI).................................................. 142
13.1 SPI introduction......................................................................... 142
13.2 Functional overview ................................................................... 142
13.2.1 SPI description...........................................................................142
13.2.2 Full-duplex/half-duplex selector ..................................................143
13.2.3 Chip select controller..................................................................145
13.2.4 SPI_SCK controller ....................................................................145
13.2.5 CRC ..........................................................................................145
13.2.6 DMA transfer..............................................................................146

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13.2.7 Transmitter ................................................................................147
13.2.8 Receiver ....................................................................................147
13.2.9 Motorola mode ...........................................................................148
13.2.10 Interrupts ................................................................................150
13.2.11 IO pin control ..........................................................................151
13.2.12 Precautions.............................................................................151
13.3 I2S functional description ........................................................... 151
13.3.1 I2S introduction ..........................................................................151
13.3.2 Operation mode selector.............................................................152
13.3.3 Audio protocol selector ...............................................................153
13.3.4 I2S_CLK controller .....................................................................154
13.3.5 DMA transfer..............................................................................156
13.3.6 Transmitter/Receiver ..................................................................157
13.3.7 I2S communication timings .........................................................158
13.3.8 Interrupts...................................................................................158
13.3.9 IO pin control .............................................................................158
13.4 SPI registers ............................................................................. 159
13.4.1 SPI control register1 (SPI_CTRL1) (Not used in I2S mode) ...........159
13.4.2SPI control register2 (SPI_CTRL2) ..............................................160
13.4.3 SPI status register (SPI_STS) .....................................................161
13.4.4 SPI data register (SPI_DT) .........................................................161
13.4.5 SPICRC register (SPI_CPOLY) (Not used in I2S mode).................161
13.4.6 SPIRxCRC register (SPI_RCRC) (Not used in I2S mode) ..............162
13.4.7 SPITxCRC register (SPI_TCRC)..................................................162
13.4.8 SPI_I2S configuration register (SPI_I2SCTRL).............................162
13.4.9 SPI_I2S prescaler register (SPI_I2SCLKP) ..................................163
14 Timer .......................................................................................... 164
14.1 General-purpose timer (TMR6).................................................... 165
14.1.1 TMR6 introduction ......................................................................165
14.1.2 TMR6 main features ...................................................................165
14.1.3 TMR6 functional overview ...........................................................165
14.1.3.1Count clock .............................................................................165
14.1.3.2 Counting mode ..................................................................... 165
14.1.3.3 Debug mode ......................................................................... 166

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14.1.4 TMR6 registers ..........................................................................166
14.1.4.1 TMR6 control register1 (TMRx_CTRL1) .................................. 167
14.1.4.2 TMR6 control register2 (TMRx_CTRL2) .................................. 167
14.1.4.3 TMR6 DMA/interrupt enable register (TMRx_IDEN).................. 167
14.1.4.4 TMR6 interrupt status register (TMRx_ISTS) ........................... 168
14.1.4.5 TMR6 software event register (TMRx_SWEVT)........................ 168
14.1.4.6 TMR6 counter value (TMRx_CVAL) ........................................ 168
14.1.4.7 TMR6 division (TMRx_DIV).................................................... 168
14.1.4.8 TMR6 period register (TMRx_PR)........................................... 168
14.2 General-purpose timer (TMR3).................................................... 169
14.2.1 TMR3 introduction ......................................................................169
14.2.2 TMR3 main features ...................................................................169
14.2.3 TMR3 functional overview ...........................................................169
14.2.3.1 Count clock .......................................................................... 169
14.2.3.2 Counting mode ..................................................................... 171
14.2.3.3 TMR input function................................................................ 173
14.2.3.4 TMR output function.............................................................. 174
14.2.3.5 TMR synchronization............................................................. 177
14.2.3.6 Debug mode ......................................................................... 179
14.2.4 TMR3 registers ..........................................................................179
14.2.4.1 Control register1 (TMR3_CTRL1) ........................................... 180
14.2.4.2 Control register2 (TMR3_CTRL2) ........................................... 181
14.2.4.3 Slave timer control register (TMR3_STCTRL) .......................... 181
14.2.4.4 DMA/interrupt enable register (TMR3_IDEN) ........................... 182
14.2.4.5 Interrupt status register (TMR3_ISTS) .................................... 183
14.2.4.6 Software event register (TMR3_SWEVT)................................. 184
14.2.4.7 Channel mode register1 (TMRx_CM1) .................................... 184
14.2.4.8 Channel mode register2 (TMR3_CM2) .................................... 186
14.2.4.9 Channel control register (TMR3_CCTRL) ................................ 187
14.2.4.10 Counter value (TMR3_CVAL) ............................................. 187
14.2.4.11 Division value (TMR3_DIV) ................................................ 188
14.2.4.12 Period register (TMR3_PR)................................................ 188
14.2.4.13 Channel 1 data register (TMR3_C1DT) ............................... 188
14.2.4.14 Channel 2 data register (TMR3_C2DT) ............................... 188
14.2.4.15 Channel 3 data register (TMR3_C3DT) ............................... 188
14.2.4.16 Channel 4 data register (TMR3_C4DT) ............................... 189
14.2.4.17 DMA control register (TMR3_DMACTRL)............................. 189
14.2.4.18 DMA data register (TMR3_DMADT) .................................... 189

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14.3 General-purpose timer (TMR14).................................................. 190
14.3.1 TMR14 introduction ....................................................................190
14.3.2 TMR14 main features .................................................................190
14.3.3 TMR14 functional overview .........................................................190
14.3.3.1 Count clock .......................................................................... 190
14.3.3.2 Counting mode ..................................................................... 191
14.3.3.3 TMR input function................................................................ 192
14.3.3.4 TMR output function.............................................................. 193
14.3.3.5 Debug mode ......................................................................... 194
14.3.4 TMR14 registers.........................................................................194
14.3.4.1 Control register1 (TMR14_CTRL1) ......................................... 195
14.3.4.2 Interrupt enable register (TMR14_IDEN) ................................. 195
14.3.4.3 Interrupt status register (TMR14_ISTS) .................................. 195
14.3.4.4 Software event register (TMR14_SWEVT) ............................... 196
14.3.4.5 Channel mode register1 (TMR14_CM1) .................................. 196
14.3.4.6 Channel control register (TMR14_CCTRL) .............................. 198
14.3.4.7 Counter value (TMR14_CVAL) ............................................... 198
14.3.4.8 Division value (TMR14_DIV) .................................................. 198
14.3.4.9 Period register (TMR14_PR) .................................................. 198
14.3.4.10 Channel 1 data register (TMR14_C1DT) ............................. 198
14.4 General-purpose timer (TMR15).................................................. 199
14.4.1 TMR15 introduction ....................................................................199
14.4.2 TMR15 main features .................................................................199
14.4.3 TMR15 functional overview .........................................................199
14.4.3.1 Count clock .......................................................................... 199
14.4.3.2 Counting mode ..................................................................... 201
14.4.3.3 TMR input function................................................................ 202
14.4.3.4 TMR output function.............................................................. 203
14.4.3.5 TMR break function............................................................... 205
14.4.3.6 TMR synchronization............................................................. 206
14.4.3.7 Debug mode ......................................................................... 207
14.4.4 TMR15 registers.........................................................................208
14.4.4.1 Control register1 (TMR15_CTRL1) ......................................... 208
14.4.4.2 Control register2 (TMR15_CTRL2) ......................................... 209
14.4.4.3 TMR15 slave timer control register (TMR15_STCTRL) ............. 209
14.4.4.4 TMR15 DMA/interrupt enable register (TMR15_IDEN) .............. 210
14.4.4.5 TMR15 interrupt status register (TMR15_ISTS) ....................... 211

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14.4.4.6 TMR15 software event register (TMR15_SWEVT) .................... 212
14.4.4.7 TMR15 channel mode register1 (TMR15_CM1) ........................ 212
14.4.4.8 TMR15 channel control register (TMR15_CCTRL).................... 215
14.4.4.9 TMR15 Counter value (TMR15_CVAL) .................................... 217
14.4.4.10 TMR15 Division value (TMR15_DIV)................................... 217
14.4.4.11 TMR15 period register (TMR15_PR) ................................... 217
14.4.4.12 TMR15 repetition period register (TMR15_RPR) .................. 217
14.4.4.13 TMR15 channel 1 data register (TMR15_C1DT) ................... 217
14.4.4.14 TMR15 channel 2 data register (TMR15_C2DT) ................... 217
14.4.4.15 TMR15 break register (TMR15_BRK) .................................. 218
14.4.4.16 TMR15 DMA control register (TMR15_DMACTRL)................ 219
14.4.4.17 TMR15 DMA data register (TMR15_DMADT) ....................... 219
14.5 General-purpose timer (TMR16 and TMR17) ................................ 220
14.5.1 TMR16 and TMR17 introduction ..................................................220
14.5.2 TMR16 and TMR17 main features ...............................................220
14.5.3 TMR16 and TMR17 functional overview .......................................220
14.5.3.1 Count clock .......................................................................... 220
14.5.3.2 Counting mode ..................................................................... 220
14.5.3.3 TMR input function................................................................ 221
14.5.3.4 TMR output function.............................................................. 222
14.5.3.5 TMR break function............................................................... 224
14.5.3.6 Debug mode ......................................................................... 225
14.5.4 TMR16 and TMR17 registers.......................................................226
14.5.4.1 TMR16 and TMR17 control register1 (TMRx_CTRL1) ............... 226
14.5.4.2 TMR16 and TMR17 control register2 (TMRx_CTRL2) ............... 227
14.5.4.3 TMR16 and TMR17 DMA/interrupt enable register (TMRx_IDEN)227
14.5.4.4 TMR16 and TMR17 interrupt status register (TMRx_ISTS)........ 228
14.5.4.5 TMR16 and TMR17 software event register (TMRx_SWEVT) .... 228
14.5.4.6 TMR16 and TMR17 channel mode register1 (TMRx_CM1) ........ 229
14.5.4.7 TMR16 and TMR17 channel control register (TMRx_CCTRL).... 231
14.5.4.8 TMR16 and TMR17 counter value (TMRx_CVAL) ..................... 232
14.5.4.9 TMR16 and TMR17 division value (TMRx_DIV)........................ 232
14.5.4.10 TMR16 and TMR17 period register (TMRx_PR) ................... 232
14.5.4.11 TMR16 and TMR17 repetition period register (TMRx_RPR) .. 232
14.5.4.12 TMR16 and TMR17 channel 1 data register (TMRx_C1DT) ... 232
14.5.4.13 TMR16 and TMR17 break register (TMRx_BRK) .................. 233
14.5.4.14 TMR16 and TMR17 DMA control register (TMRx_DMACTRL) 234
14.5.4.15 TMR16 and TMR17 DMA data register (TMRx_DMADT) ....... 234

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14.6 Advanced-control timers (TMR1) ................................................. 235
14.6.1 TMR1 introduction ......................................................................235
14.6.2 TMR1 main features ...................................................................235
14.6.3 TMR1 functional overview ...........................................................235
14.6.3.1 Count clock .......................................................................... 235
14.6.3.2 Counting mode ..................................................................... 237
14.6.3.3 TMR input function................................................................ 240
14.6.3.4 TMR output function.............................................................. 241
14.6.3.5 TMR break function............................................................... 244
14.6.3.6 TMR synchronization............................................................. 244
14.6.3.7 Debug mode ......................................................................... 245
14.6.4 TMR1 registers ..........................................................................246
14.6.4.1 TMR1 control register1 (TMR1_CTRL1) .................................. 246
14.6.4.2 TMR1 control register2 (TMR1_CTRL2) .................................. 247
14.6.4.3 TMR1 slave timer control register (TMR1_STCTRL) ................. 248
14.6.4.4 TMR1 DMA/interrupt enable register (TMR1_IDEN).................. 249
14.6.4.5 TMR1 interrupt status register (TMR1_ISTS) ........................... 250
14.6.4.6 TMR1 software event register (TMR1_SWEVT)........................ 251
14.6.4.7 TMR1 channel mode register1 (TMR1_CM1) ........................... 251
14.6.4.8 TMR1 channel mode register2 (TMR1_CM2) ........................... 253
14.6.4.9 TMR1 Channel control register (TMR1_CCTRL)....................... 254
14.6.4.10 TMR1 counter value (TMR1_CVAL) .................................... 256
14.6.4.11 TMR1 division value (TMR1_DIV) ....................................... 256
14.6.4.12 TMR1 period register (TMR1_PR)....................................... 256
14.6.4.13 TMR1 repetition period register (TMR1_RPR)...................... 256
14.6.4.14 TMR1 channel 1 data register (TMR1_C1DT) ...................... 256
14.6.4.15 TMR1 channel 2 data register (TMR1_C2DT) ...................... 256
14.6.4.16 TMR1 channel 3 data register (TMR1_C3DT) ...................... 257
14.6.4.17 TMR1 channel 4 data register (TMR1_C4DT) ...................... 257
14.6.4.18 TMR1 break register (TMR1_BRK)...................................... 257
14.6.4.19 TMR1 DMA control register (TMR1_DMACTRL) ................... 258
14.6.4.20 TMR1 DMA data register (TMR1_DMADT)........................... 258
15 Window watchdog timer (WWDT) ................................................ 259
15.1 WWDT introduction .................................................................... 259
15.2 WWDT main features ................................................................. 259
15.3 WWDT functional overview ......................................................... 259

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15.4 Debug mode.............................................................................. 260
15.5 WWDT registers ........................................................................ 260
15.5.1 Control register (WWDT_CTRL) ..................................................260
15.5.2 Configuration register (WWDT_CFG)...........................................261
15.5.3 Status register (WWDT_STS)......................................................261
16 Watchdog timer (WDT) ................................................................ 262
16.1 WDT introduction ....................................................................... 262
16.2 WDT main features .................................................................... 262
16.3 WDT functional overview ............................................................ 262
16.4 Debug mode.............................................................................. 263
16.5 WDT registers ........................................................................... 263
16.5.1 Command register (WDT_CMD) ..................................................263
16.5.2 Divider register (WDT_DIV).........................................................263
16.5.3 Reload register (WDT_RLD)........................................................264
16.5.4 Status register (WDT_STS).........................................................264
17 Enhanced real-time clock (ERTC) ............................................... 265
17.1 ERTC introduction...................................................................... 265
17.2 ERTC main features................................................................... 265
17.3 ERTC functional overview........................................................... 265
17.3.1 ERTC clock................................................................................265
17.3.2 ERTC initialization......................................................................266
17.3.3 ERTC calibration ........................................................................268
17.3.4 Time stamp................................................................................268
17.3.5 Tamper detection .......................................................................269
17.3.6 Multiplexed function output .........................................................269
17.3.7 ERTC wakeup ............................................................................269
17.4 ERTC registers.......................................................................... 270
17.4.1 ERTC time register (ERTC_TIME) ...............................................270
17.4.2 ERTC date register (ERTC_DATE) ..............................................271
17.4.3 ERTC control register (ERTC_CTRL)...........................................271
17.4.4 ERTC initialization and status register (ERTC_STS).....................272
17.4.5 ERTC divider register (ERTC_DIV)..............................................273
17.4.6 ERTC alarm clock A register (ERTC_ALA) ...................................273

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17.4.7 ERTC write protection register (ERTC_WP) .................................274
17.4.8 ERTC subsecond register (ERTC_SBS) .......................................274
17.4.9 ERTC time adjustment register (ERTC_TADJ)..............................274
17.4.10 ERTC time stamp time register (ERTC_TSTM) ..........................274
17.4.11 ERTC time stamp date register (ERTC_TSDT) ..........................275
17.4.12 ERTC time stamp subsecond register (ERTC_TSSBS)...............275
17.4.13 ERTC smooth calibration register (ERTC_SCAL) .......................275
17.4.14 ERTC tamper configuration register (ERTC_TAMP) ...................275
17.4.15 ERTC alarm clock A subsecond register (ERTC_ALASBS) .........277
17.4.16 ERTC battery powered domain data register (ERTC_BPRx) .......277
18 Analog-to-digital converter (ADC)............................................... 278
18.1 ADC introduction ....................................................................... 278
18.2 ADC main features..................................................................... 278
18.3 ADC structure............................................................................ 278
18.4 ADC functional overview............................................................. 279
18.4.1 Channel management.................................................................279
18.4.1.1 Internal temperature sensor ................................................... 280
18.4.1.2 Internal reference voltage...................................................... 280
18.4.2 ADC operation process ...............................................................280
18.4.2.1 Power-on and calibration ....................................................... 280
18.4.2.2 Trigger................................................................................. 281
18.4.2.3 Sampling and conversion sequence........................................ 282
18.4.3 Conversion sequence management .............................................282
18.4.3.1 Sequence mode .................................................................... 282
18.4.3.2 Automatic preempted group conversion mode ......................... 282
18.4.3.3 Repetition mode.................................................................... 283
18.4.3.4 Partition mode ...................................................................... 283
18.4.4 Data management ......................................................................284
18.4.4.1 Data alignment ..................................................................... 284
18.4.4.2 Data read ............................................................................. 284
18.4.5 Voltage monitoring .....................................................................285
18.4.6 Status flag and interrupts............................................................285
18.5 ADC registers............................................................................ 285
18.5.1 ADC status register (ADC_STS) ..................................................286
18.5.2 ADC control register1 (ADC_CTRL1) ...........................................286

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18.5.3 ADC control register2 (ADC_CTRL2) ...........................................287
18.5.4 ADC sampling time register 1 (ADC_SPT1)..................................289
18.5.5 ADC sampling time register 2 (ADC_SPT2)..................................290
18.5.6 ADC preempted channel data offset register x
(ADC_ PCDTOx) (x=1..4)......................................................................292
18.5.7 ADC voltage monitor high threshold register (ADC_VWHB)...........292
18.5.8 ADC voltage monitor low threshold register (ADC_ VWLB)............292
18.5.9 ADC ordinary sequence register 1 (ADC_ OSQ1) .........................293
18.5.10 ADC ordinary sequence register 2 (ADC_OSQ2) .......................293
18.5.11 ADC ordinary sequence register 3 (ADC_OSQ3) .......................293
18.5.12 ADC preempted sequence register (ADC_ PSQ)........................294
18.5.13 ADC preempted data register x (ADC_ PDTx) (x=1..4) ...............294
18.5.14 ADC ordinary data register (ADC_ ODT) ...................................294
19 Comparator (COMP) .................................................................... 295
19.1 COMP introduction..................................................................... 295
19.2 Main features ............................................................................ 295
19.3 Interrupt management ................................................................ 295
19.4 Design tips................................................................................ 296
19.5 Functional overview ................................................................... 296
19.5.1 Analog comparator .....................................................................296
19.5.2 Glitch filter.................................................................................297
19.6 CMP registers............................................................................ 297
19.6.1 Comparator control and status register 1 (COMP_CTRLSTS)........298
19.6.2 Glitch filter enable register (G_FILTER_EN) ................................299
19.6.3 Glitch filter high pulse count (HIGH-PULSE) ................................299
19.6.4 Glitch filter low pulse count (LOW-PULSE) ..................................300
20 Infrared timer (IRTMR) ................................................................ 301
21 Debug (DEBUG) .......................................................................... 302
21.1 Debug introduction..................................................................... 302
21.2 Debug and trace ........................................................................ 302
21.3 I/O pin control............................................................................ 302
21.4 DEBUG registers ....................................................................... 302

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21.4.1 DEBUG device ID (DEBUG_IDCODE)..........................................303
21.4.2 DEBUG control register (DEBUG_CTRL) .....................................304
22 Revision history.......................................................................... 306

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List of figures
Figure 1-1 AT32F421 Series microcontrollers system architecture................................................................. 25
Figure 1-2 Internal block diagram of Cortex®-M4........................................................................................ 26
Figure 1-3 Comparison between bit-band region and its alias region: image A ......................................... 26
Figure 1-4 Comparison between bit-band region and its alias region: image B ......................................... 27
Figure 1-5 Reset process ............................................................................................................................ 30
Figure 1-6 Example of MSP and PC initialization........................................................................................ 31
Figure 2-1AT32F421 address mapping....................................................................................................... 33
Figure 3-1 Block diagram of each power supply......................................................................................... 38
Figure 3-2 Power-on reset/Low voltage reset waveform............................................................................. 39
Figure 3-3 PVM threshold and output ......................................................................................................... 40
Figure 4-1 AT32F421 clock tree .................................................................................................................. 44
Figure 4-2 System reset circuit.................................................................................................................... 47
Figure 5-1 Flash memory page erase process ........................................................................................... 63
Figure 5-2 Flash memory mass erase process........................................................................................... 64
Figure 5-3 Flash memory programming process ........................................................................................ 65
Figure 5-4 System data area erase process ............................................................................................... 66
Figure 5-5 System data area programming process................................................................................... 67
Figure 6-1 GPIO basic structure.................................................................................................................. 79
Figure 6-2 IOMUX structure ........................................................................................................................ 81
Figure 8-1 External interrupt/Event controller block diagram...................................................................... 92
Figure 9-1 DMA block diagram .................................................................................................................... 95
Figure 9-2 Re-arbitrae after request/acknowledge...................................................................................... 96
Figure 9-3 PWIDTH: byte, MWIDTH: half-word .......................................................................................... 97
Figure 9-4 PWIDTH: half-word, MWIDTH: word ......................................................................................... 97
Figure 9-5 PWIDTH: word, MWIDTH: byte ................................................................................................. 97
Figure 11-1 I2C bus protocol ...................................................................................................................... 106
Figure 11-2 I2C function block diagram ..................................................................................................... 107
Figure 11-3 Transfer sequence of slave transmitter.................................................................................. 109
Figure 11-4 Transfer sequence of slave receiver .......................................................................................110
Figure 11-5 Transfer sequence of master transmitter ................................................................................111
Figure 11-6 Transfer sequence of master receiver.....................................................................................113
Figure 11-7 Transfer sequence of master receiver when N>2...................................................................114
Figure 11-8 Transfer sequence of master receiver when N=2...................................................................115
Figure 11-9 Transfer sequence of master receiver when N=1...................................................................116
Figure 12-1 USART block diagram............................................................................................................ 127
Figure 12-2 Tx/Rx swap............................................................................................................................. 135
Figure 12-3 USART interrupt map diagram............................................................................................... 135
Figure 13-1 SPI block diagram .................................................................................................................. 142
Figure 13-2 SPI two-wire unidirectional full-duplex connection ................................................................ 143
Figure 13-3 Single-wire unidirectional receive only in SPI master mode.................................................. 143
Figure 13-4 Single-wire unidirectional receive only in SPI slave mode .................................................... 144
Figure 13-5 Single-wire bidirectional half-duplex mode ............................................................................ 144
Figure 13-6 Master full-duplex communications ....................................................................................... 148

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Figure 13-7 Slave full-duplex communications.......................................................................................... 149
Figure 13-8 Slave full-duplex communications.......................................................................................... 149
Figure 13-9 Slave half-duplex receive....................................................................................................... 149
Figure 13-10 Slave half-duplex transmit.................................................................................................... 150
Figure 13-11 Master half-duplex receive................................................................................................... 150
Figure 13-12 SPI interrupts ....................................................................................................................... 150
Figure 13-7 I2S block diagram ................................................................................................................... 151
Figure 13-14 I2S slave device transmission .............................................................................................. 152
Figure 13-15 I2S slave device reception.................................................................................................... 152
Figure 13-16 I2S master device transmission............................................................................................ 153
Figure 13-17 I2S master device reception ................................................................................................. 153
Figure 13-18 CK & MCK source in master mode...................................................................................... 155
Figure 13-19 Audio standard timings......................................................................................................... 158
Figure 13-13 I2S interrrupts ....................................................................................................................... 158
Figure 14-1 Basic timer block diagram...................................................................................................... 165
Figure 14-2 Counter timing diagram, CK_INT divided by 1 ...................................................................... 165
Figure 14-3 Overflow event when PRBEN=0............................................................................................ 166
Figure 14-4 Overflow event when PRBEN=1............................................................................................ 166
Figure 14-5 Counting timing diagram when the prescaler division is 4 .................................................... 166
Figure 14-6 Block diagram of general-purpose......................................................................................... 169
Figure 14-7 Counter timing diagram, CK_INT divided by 1 ...................................................................... 169
Figure 14-8 Block diagram of external clock mode A................................................................................ 170
Figure 14-9 Counter timing diagram in external clock mode A ................................................................. 170
Figure 14-10 Block diagram of external clock mode B.............................................................................. 170
Figure 14-11 Counter timing diagram in external clock mode B ............................................................... 171
Figure 14-12 Counter timing with prescaler value changing from 1 to 4 .................................................. 171
Figure 14-13 Overflow event when PRBEN=0.......................................................................................... 172
Figure 14-14 Overflow event when PRBEN=1.......................................................................................... 172
Figure 14-15 Counter timing diagram, internal clock divided by 4............................................................ 172
Figure 14-16 Counter timing diagram with internal clock divided by 1 and TMR3_PR=0x32 .................. 172
Figure 14-17 Example of counter behavior in encoder interface mode (encoder mode C)...................... 173
Figure 14-18 Input/output channel 1 main circuit ...................................................................................... 173
Figure 14-19 Channel 1 input stage .......................................................................................................... 173
Figure 14-20 Capture/compare channel output stage (channel 1 to 4) .................................................... 174
Figure 14-21 C1ORAW toggles when counter value matches the C1DT value ....................................... 175
Figure 14-22 Upcounting mode and PWM mode A................................................................................... 175
Figure 14-23 Up/down counting mode and PWM mode A........................................................................ 176
Figure 14-24 One-pulse mode................................................................................................................... 176
Figure 14-25 Clearing CxORAW(PWM mode A) by EXT input................................................................. 176
Figure 14-26 Example of reset mode ........................................................................................................ 177
Figure 14-27 Example of suspend mode .................................................................................................. 177
Figure 14-28 Example of trigger mode...................................................................................................... 177
Figure 14-29 Master/slave timer connection ............................................................................................. 178
Figure 14-30 Using master timer to start slave timer ................................................................................ 178
Figure 14-31 Starting master and slave timers synchronously by an external trigger.............................. 179

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Figure 14-32 Block diagram of general-purpose TMR14.......................................................................... 190
Figure 14-33 Counter timing diagram, CK_INT divided by 1 .................................................................... 190
Figure 14-34 Counter timing with prescaler value changing from 1 to 4 .................................................. 191
Figure 14-35 Overflow event when PRBEN=0.......................................................................................... 191
Figure 14-36 Overflow event when PRBEN=1.......................................................................................... 191
Figure 14-37 Input/output channel 1 main circuit ...................................................................................... 192
Figure 14-38 Channel 1 input stage .......................................................................................................... 192
Figure 14-39 Capture/compare channel output stage (channel 1) ........................................................... 193
Figure 14-40 C1ORAW toggles when counter value matches the C1DT value ....................................... 193
Figure 14-41 Upcounting mode and PWM mode A................................................................................... 194
Figure 14-42 Block diagram of general-purpose TMR15.......................................................................... 199
Figure 14-43 Counter timing diagram, CK_INT divided by 1 .................................................................... 199
Figure 14-44 Block diagram of external clock mode A.............................................................................. 200
Figure 14-45 Counter timing diagram in external clock mode A ............................................................... 200
Figure 14-46 Counter timing with prescaler value changing from 1 to 4 .................................................. 200
Figure 14-47 Overflow event when PRBEN=0.......................................................................................... 201
Figure 14-48 Overflow event when PRBEN=1.......................................................................................... 201
Figure 14-49 OVFIF when RPR=2 ............................................................................................................ 201
Figure 14-50 Input/output channel 1 main circuit...................................................................................... 202
Figure 14-51 Channel 1 input stage .......................................................................................................... 202
Figure 14-52 Channel 1 output stage........................................................................................................ 203
Figure 14-53 Channel 2 output stage........................................................................................................ 203
Figure 14-54 C1ORAW toggles when counter value matches the C1DT value ....................................... 204
Figure 14-55 Upcounting mode and PWM mode A................................................................................... 204
Figure 14-56 One-pulse mode................................................................................................................... 204
Figure 14-57 Complementary output with dead-time insertion ................................................................. 205
Figure 14-58 Example of TMR break function........................................................................................... 206
Figure 14-59 Example of reset mode ........................................................................................................ 206
Figure 14-60 Example of suspend mode .................................................................................................. 207
Figure 14-61 Example of trigger mode...................................................................................................... 207
Figure 14-62 Block diagram of general-purpose TMR16 and TMR17...................................................... 220
Figure 14-63 Counter timing diagram, CK_INT divided by 1 .................................................................... 220
Figure 14-64 Overflow event when PRBEN=0.......................................................................................... 221
Figure 14-65 Overflow event when PRBEN=1.......................................................................................... 221
Figure 14-66 OVFIF when RPR=2 ............................................................................................................ 221
Figure 14-67 Input/output channel 1 main circuit ...................................................................................... 221
Figure 14-68 Channel 1 input stage .......................................................................................................... 222
Figure 14-69 Channel 1 output stage........................................................................................................ 222
Figure 14-70 C1ORAW toggles when counter value matches the C1DT value ....................................... 223
Figure 14-71 Upcounting mode and PWM mode A................................................................................... 223
Figure 14-72 One-pulse mode................................................................................................................... 224
Figure 14-73 Complementary output with dead-time insertion ................................................................. 224
Figure 14-74 Example of TMR break function........................................................................................... 225
Figure 14-75 Block diagram of advanced-control timer ............................................................................ 235
Figure 14-76 Control circuit with CK_INT divided by 1 ............................................................................. 236