ARTERY AT32F421 Series User manual

AT32F421 Series Reference Manual
2021.11.17Page 1 Ver 2.00
ARM®-based 32-bit Cortex®-M4 MCU with 16 to 64 KB Flash, sLib, 10 timers,
ADC, 7 communication interfaces
Feature
Core: ARM®32-bit Cortex®-M4F CPU
−120 MHz maximum frequency, with a
Memory Protection Unit (MPU), single-cycle
multiplication and hardware division
−DSP instructions
Memories
−16 to 64 KBytes of internal Flash memory
−4 Kbytes of boot code area used as a
Bootloader or as a general instruction/data
memory (one-time-configured)
−sLib: configurable part of main Flash set as a
library area with code executable but
secured, non-readable
−8 to 16 KBytes of SRAM
Clock, reset and power control
−2.4 V ~ 3.6 V application suppy and I/Os
−Power-on reset (POR)/ low-voltage reset
(LVR), and power voltage monitor (PVM)
−4 to 25 MHz crystal (HEXT)
−Internal 8 MHz factory-trimmed clock (HICK),
accuracy 1% at TA=25 °C, 2 % at TA=-40 to
+105 °C
−Internal 40 kHz RC oscillator
−32 kHz crystal oscillator (LEXT)
Low power
−Sleep, Deepsleep, and Standby modes
1 x 12-bit A/D converter (up to 15 input
channels)
−Conversion range: 0 V to 3.6 V
1 x COMP, 5 x external input channels
and 1 x internal reference voltage
channel
DMA: 5-channel DMA controller
−Peripherals supported: timers, ADC, I2S,
SPI, I2C and USART
Debug mode
−Serial wire debug (SWD) and JTAG
Up to 39 fast GPIOs
−All mapable to external interrupt vectors
−Almost5 V-tolerant
−All fast I/Os,registersaccessible with fAHBspeed
Up to 10 Timers (TMR)
−1 x 16-bit 7-channel advanced timer, 6-channel
PWM outout with dead-time generator and
emergencystop
−5 x 16-bit timers, each with 4 IC/OC/PWM or
pulse counter and encoder input
−1 x 16-bit basic timer
−2x Watchdog timers (WDTandWWDT)
−SysTick timer: 24-bit downcounter
ERTC: enhanced RTC
Up to 7 communication interfaces
−2 x I2C interfaces (SMBus/PMBus support)
−2x USARTs/UART (ISO7816 interface,LIN,
IrDA and modem control)
−2 x SPIs, both with I2S interface multiplexed
−Infrared transmitter
CRC Calculation Unit
96-bit ID (UID)
Packaging
−LQFP48 7 x 7 mm
−LQFP32 7 x 7 mm
−QFN32 5 x 5 mm
−QFN32 4 x 4 mm
−QFN28 4 x 4mm
−TSSOP20 6.5 x 4.4 mm
List of Models
Internal Flash
Model
64 KBytes
AT32F421C8T7, AT32F421K8T7
AT32F421K8U7, AT32F421K8U7-4
AT32F421F8P7, AT32F421G8U7
32 KBytes
AT32F421C6T7, AT32F421K6T7
AT32F421K6U7, AT32F421K6U7-4
AT32F421F6P7, AT32F421G6U7
16 KBytes
AT32F421C4T7, AT32F421K4T7
AT32F421K4U7, AT32F421K4U7-4
AT32F421F4P7, AT32F421G4U7

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Contents
1System architecture...................................................................... 24
1.1 System overview..........................................................................26
1.1.1 ARM CortexTM-M4 processor........................................................ 26
1.1.2 Bit band...................................................................................... 26
1.1.3 Interrupt and exception vectors .................................................... 28
1.1.4 System Tick (SysTick) ................................................................. 30
1.1.5 Reset ......................................................................................... 30
1.2 List of abbreviations for registers ..................................................32
1.3 Device characteristics information.................................................32
1.3.1 Flash memory size register .......................................................... 32
1.3.2 Device electronic signature.......................................................... 32
2Memory resources ........................................................................ 33
2.1 Internal memory address map.......................................................33
2.2 Flash memory..............................................................................34
2.3 SRAM memory.............................................................................34
2.4 Peripheral address map................................................................35
3Power control (PWC)..................................................................... 38
3.1 Introduction .................................................................................38
3.2 Main Features .............................................................................38
3.3 POR/LVR ....................................................................................39
3.4 Power voltage monitor (PVM)........................................................39
3.5 Power domain..............................................................................40
3.6 Power saving modes ....................................................................40
3.7 PWC registers .............................................................................42
3.7.1 Power control register (PWC_CTRL) ............................................ 42
3.7.2 Power control/status register (PWC_CTRLSTS) ............................ 43
3.7.3 Power control register 2 (PWC_CTRL2)........................................ 43
4Clock and reset manage (CRM) ..................................................... 44
4.1 Clock ..........................................................................................44

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4.1.1 Clock sources ............................................................................. 44
4.1.2 System clock............................................................................... 45
4.1.3 Peripheral clock .......................................................................... 45
4.1.4 Clock fail detector ....................................................................... 46
4.1.5 Auto step-by-step system clock switch.......................................... 46
4.1.6 Internal clock output.................................................................... 46
4.1.7 Interrupts.................................................................................... 46
4.2 Reset..........................................................................................46
4.2.1 System reset............................................................................... 46
4.2.2 Battery powered domain reset...................................................... 47
4.3 CRM registers .............................................................................47
4.3.1 Clock control register (CRM_CTRL).............................................. 48
4.3.2 Clock configuration register (CRM_CFG) ...................................... 49
4.3.3 Clock interrupt register (CRM_CLKINT) ........................................ 50
4.3.4 APB2 peripheral reset register (CRM_APB2RST) .......................... 51
4.3.5 APB1 peripheral reset register1 (CRM_APB1RST) ........................ 52
4.3.6 AHB peripheral clock enable register (CRM_AHBEN) .................... 53
4.3.7 APB2 peripheral clock enable register (CRM_APB2EN) ................. 54
4.3.8 APB1 peripheral clock enable register (CRM_APB1EN) ................. 55
4.3.9 Battery powered domain control register (CRM_BPDC).................. 56
4.3.10 Control/status register (CRM_CTRLSTS) ...................................... 56
4.3.11 AHB peripheral reset register (CRM_AHBRST) ............................. 57
4.3.12 PLL configuration register (CRM_PLL).......................................... 58
4.3.13 Additional register (CRM_MISC1)................................................. 58
4.3.14 Additional register (CRM_MISC2)................................................. 59
5Flash memory controller (FLASH)................................................. 60
5.1 FLASH introduction......................................................................60
5.2 Flash memory operation ...............................................................62
5.2.1 Unlock/lock ................................................................................. 62
5.2.2 Erase operation........................................................................... 62
5.2.3 Programming operation................................................................ 64
5.2.4 Read operation ........................................................................... 65
5.3 Main Flash memory extension area ...............................................65
5.4 User system data area ................................................................. 65

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5.4.1 Unlock/lock ................................................................................. 65
5.4.2 Erase operation........................................................................... 66
5.4.3 Programming operation................................................................ 67
5.4.4 Read operation ........................................................................... 68
5.5 Flash memory protection ..............................................................68
5.5.1 Access protection........................................................................ 68
5.5.2 Erase/program protection............................................................. 69
5.6 Special functions .........................................................................69
5.6.1 Security library settings ............................................................... 69
5.6.2 Bootloader code area used as Flash memory extension................. 70
5.6.3 CRC verify .................................................................................. 70
5.7 Flash memory registers ................................................................71
5.7.1 Flash performance select register (FLASH_PSR) .......................... 71
5.7.2 Flash unlock register (FLASH_UNLOCK) ...................................... 72
5.7.3 Flash user system data unlock register (FLASH_USD_UNLOCK) ... 72
5.7.4 Flash status register (FLASH_STS) .............................................. 72
5.7.5 Flash control register (FLASH_CTRL)........................................... 73
5.7.6 Flash address register (FLASH_ADDR) ........................................ 74
5.7.7 User system data register (FLASH_USD)...................................... 74
5.7.8 Erase/program protection status register (FLASH_EPPS) .............. 74
5.7.9 Flash security library status register0 (SLIB_STS0)....................... 75
5.7.10 Flash security library status register1 (SLIB_STS1)....................... 75
5.7.11 Security library password clear register (SLIB_PWD_CLR) ............ 75
5.7.12 Security library additional status register (SLIB_MISC_STS).......... 76
5.7.13 Flash CRC address register (FLASH_CRC_ARR) .......................... 76
5.7.14 Flash CRC control register (FLASH_CRC_CTRL) .......................... 76
5.7.15 Flash CRC check result register (FLASH_CRC_CHKR).................. 76
5.7.16 Security library password setting register (SLIB_SET_PWD).......... 77
5.7.17 Security library address setting register (SLIB_SET_RANGE) ........ 77
5.7.18 Flash extension memory security library setting register
(EM_SLIB_SET).................................................................................... 78
5.7.19 Boot mode setting register (BTM_MODE_SET) ............................. 78
5.7.20 Security library unlock register (FLASH_UNLOCK) ........................ 78
6General-purpose I/Os (GPIOs)....................................................... 79

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6.1 Introduction .................................................................................79
6.2 Functional overview .....................................................................79
6.2.1 GPIO structure ............................................................................ 79
6.2.2 GPIO reset status........................................................................ 79
6.2.3 General-purpose input configuration............................................. 80
6.2.4 Analog input/output configuration ................................................. 80
6.2.5 General-purpose output configuration........................................... 80
6.2.6 GPIO port protection ................................................................... 80
6.2.7 IOMUX structure ......................................................................... 81
6.2.8 Multiplexed function input configuration ........................................ 81
6.2.9 IOMUX function input/output ........................................................ 82
6.2.10 Peripheral multiplexed function configuration ................................ 84
6.2.11 IOMUX map priority ..................................................................... 84
6.2.12 External interrupt/wake-up lines ................................................... 84
6.3 GPIO registers.............................................................................84
6.3.1 GPIO configuration register (GPIOx_CFGR) (x=A…H) ................... 85
6.3.2 GPIO input mode register (GPIOx_OMODE) (x=A…H) ................... 85
6.3.3 GPIO drive capability register (GPIOx_ODRVR) (x=A..H)............... 85
6.3.4 GPIO pull-up/pull-down register (GPIOx_PULL) (x=A..H) ............... 85
6.3.5 GPIO input data register (GPIOx_IDT) (x=A…H) ........................... 86
6.3.6 GPIO output data register (GPIOx_ODT) (x= A…H) ....................... 86
6.3.7 GPIO set/clear register (GPIOx_SCR) (x=A…H) ............................ 86
6.3.8 GPIO write protection register (GPIOx_WPR) (x=A…H) ................. 86
6.3.9 GPIO multiplexed function low register (GPIOx_MUXL) (x=A..H) .... 87
6.3.10 GPIO multiplexed function high register (GPIOx_MUXH) (x=A..H) .. 87
6.3.11 GPIO bit clear register (GPIOx_CLR) (x=A…H) ............................. 87
6.3.12 GPIO huge current control register (GPIOx_HDRV) (x=A..H).......... 87
7System configuration controller (SCFG) ....................................... 88
7.1 Introduction .................................................................................88
7.2 SCFG registers............................................................................88
7.2.1 SCFG configuration register1 (SCFG_CFG1) ................................ 88
7.2.2 SCFG external interrupt configuration register1 (SCFG_ EXINTC1) 89
7.2.3 SCFG external interrupt configuration register2 (SCFG_ EXINTC2) 90
7.2.4 SCFG external interrupt configuration register3 (SCFG_ EXINTC3) 90

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7.2.5 SCFG external interrupt configuration register4 (SCFG_ EXINTC4) 91
8External interrupt/Event controller (EXINT) .................................. 92
8.1 EXINT introduction.......................................................................92
8.2 Function overview and configuration procedure ..............................92
8.3 EXINT registers ...........................................................................93
8.3.1 Interrupt enable register (EXINT_INTEN)...................................... 93
8.3.2 Event enable register (EXINT_EVTEN) ......................................... 93
8.3.3 Polarity configuration register1 (EXINT_POLCFG1)....................... 93
8.3.4 Polarity configuration register2 (EXINT_POLCFG2)....................... 94
8.3.5 Software trigger register (EXINT_ SWTRG)................................... 94
8.3.6 Interrupt status register (EXINT_ INTSTS) .................................... 94
9DMA controller (DMA) ................................................................... 95
9.1 Introduction .................................................................................95
9.2 Main features ..............................................................................95
9.3 Functional overview .....................................................................95
9.3.1 DMA configuration....................................................................... 95
9.3.2 Handshake mechanism................................................................ 96
9.3.3 Arbiter ........................................................................................ 96
9.3.4 Programmable data transfer width ................................................ 97
9.3.5 Errors ......................................................................................... 98
9.3.6 Interrupts.................................................................................... 98
9.3.7 Fixed DMA request mapping ........................................................ 98
9.4 DMA registers..............................................................................99
9.4.1 DMA interrupt status register (DMA_STS)....................................100
9.4.2 DMA interrupt flag clear register (DMA_CLR)...............................101
9.4.3 DMA channel-x configuration register (DMA_CxCTRL) (x = 1…5) ..102
9.4.4 DMA channel-x number of data register (DMA_CxDTCNT)
(x = 1…5) ............................................................................................103
9.4.5 DMA channel-x peripheral address register (DMA_CxPADDR)
(x = 1…5) ............................................................................................103
9.4.6 DMA channel-x memory address register (DMA_CxMADDR)
(x = 1…5) ............................................................................................103
10 CRC calculation unit (CRC)......................................................... 104

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10.1 CRC introduction ....................................................................... 104
10.2 CRC registers............................................................................ 104
10.2.1 Data register (CRC_DT)..............................................................104
10.2.2 Common data register (CRC_CDT)..............................................104
10.2.3 Control register (CRC_CTRL)......................................................105
10.2.4 Initialization register (CRC_IDT) .................................................105
11 I2C interface ................................................................................ 106
11.1 I2C introduction.......................................................................... 106
11.2 I2C main features....................................................................... 106
11.3 I2C functional overview............................................................... 106
11.4 I2C interface .............................................................................. 107
11.4.1 I2C slave communication flow......................................................108
11.4.2 I2C master communication flow ...................................................111
11.4.3 Data transfer using DMA.............................................................117
11.4.4 SMBus.......................................................................................118
11.4.5 I2C interrupt requests .................................................................119
11.4.6 I2C debug mode .........................................................................120
11.5 I2C registers .............................................................................. 120
11.5.1 Control register1 (I2C_CTRL1)....................................................120
11.5.2 Control register2 (I2C_CTRL2)....................................................121
11.5.3 Own address register1 (I2C_OADDR1) ........................................122
11.5.4 Own address register2 (I2C_OADDR2) ........................................122
11.5.5 Data register (I2C_DT) ...............................................................123
11.5.6 Status register1 (I2C_STS1) .......................................................123
11.5.7 Status register2 (I2C_STS2) .......................................................125
11.5.8 Clock control register (I2C_ CLKCTRL) .......................................126
12 Universal synchronous/asynchronous receiver/transmitter (USART)127
12.1 USART introduction ................................................................... 127
12.2 Full-duplex/half-duplex selector .................................................. 129
12.3 Mode selector............................................................................ 129
12.3.1 Introduction................................................................................129
12.3.2 Configuration procedure .............................................................129
12.4 USART frame format and configuration........................................ 130

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12.5 DMA transfer introduction........................................................... 130
12.5.1 Transmission using DMA ............................................................130
12.5.2 Reception using DMA .................................................................130
12.6 Baud rate generation.................................................................. 131
12.6.1 Introduction................................................................................131
12.6.2 Configuration .............................................................................131
12.7 Transmitter................................................................................ 132
12.7.1 Transmitter introduction..............................................................132
12.7.2 Transmitter configuration ............................................................132
12.8 Receiver ................................................................................... 132
12.8.1 Receiver introduction..................................................................132
12.8.2 Receiver configuration................................................................133
12.8.3 Start bit and noise detection .......................................................134
12.9 Tx/Rx swap ............................................................................... 134
12.10Interrupt requests ...................................................................... 135
12.11I/O pin control............................................................................ 136
12.12USART registers........................................................................ 136
12.12.1 Status register (USART_STS) ..................................................137
12.12.2 Data register (USART_DT).......................................................138
12.12.3 Baud rate register (USART_BAUDR) ........................................138
12.12.4 Control register1 (USART_CTRL1) ...........................................138
12.12.5 Control register2 (USART_CTRL2) ...........................................139
12.12.6 Control register3 (USART_CTRL3) ...........................................140
12.12.7 Guard time and divider register (USART_GDIV) ........................141
13 Serial peripheral interface (SPI).................................................. 142
13.1 SPI introduction......................................................................... 142
13.2 Functional overview ................................................................... 142
13.2.1 SPI description...........................................................................142
13.2.2 Full-duplex/half-duplex selector ..................................................143
13.2.3 Chip select controller..................................................................145
13.2.4 SPI_SCK controller ....................................................................145
13.2.5 CRC ..........................................................................................145
13.2.6 DMA transfer..............................................................................146

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13.2.7 Transmitter ................................................................................147
13.2.8 Receiver ....................................................................................147
13.2.9 Motorola mode ...........................................................................148
13.2.10 Interrupts ................................................................................150
13.2.11 IO pin control ..........................................................................151
13.2.12 Precautions.............................................................................151
13.3 I2S functional description ........................................................... 151
13.3.1 I2S introduction ..........................................................................151
13.3.2 Operation mode selector.............................................................152
13.3.3 Audio protocol selector ...............................................................153
13.3.4 I2S_CLK controller .....................................................................154
13.3.5 DMA transfer..............................................................................156
13.3.6 Transmitter/Receiver ..................................................................157
13.3.7 I2S communication timings .........................................................158
13.3.8 Interrupts...................................................................................158
13.3.9 IO pin control .............................................................................158
13.4 SPI registers ............................................................................. 159
13.4.1 SPI control register1 (SPI_CTRL1) (Not used in I2S mode) ...........159
13.4.2SPI control register2 (SPI_CTRL2) ..............................................160
13.4.3 SPI status register (SPI_STS) .....................................................161
13.4.4 SPI data register (SPI_DT) .........................................................161
13.4.5 SPICRC register (SPI_CPOLY) (Not used in I2S mode).................161
13.4.6 SPIRxCRC register (SPI_RCRC) (Not used in I2S mode) ..............162
13.4.7 SPITxCRC register (SPI_TCRC)..................................................162
13.4.8 SPI_I2S configuration register (SPI_I2SCTRL).............................162
13.4.9 SPI_I2S prescaler register (SPI_I2SCLKP) ..................................163
14 Timer .......................................................................................... 164
14.1 General-purpose timer (TMR6).................................................... 165
14.1.1 TMR6 introduction ......................................................................165
14.1.2 TMR6 main features ...................................................................165
14.1.3 TMR6 functional overview ...........................................................165
14.1.3.1Count clock .............................................................................165
14.1.3.2 Counting mode ..................................................................... 165
14.1.3.3 Debug mode ......................................................................... 166

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14.1.4 TMR6 registers ..........................................................................166
14.1.4.1 TMR6 control register1 (TMRx_CTRL1) .................................. 167
14.1.4.2 TMR6 control register2 (TMRx_CTRL2) .................................. 167
14.1.4.3 TMR6 DMA/interrupt enable register (TMRx_IDEN).................. 167
14.1.4.4 TMR6 interrupt status register (TMRx_ISTS) ........................... 168
14.1.4.5 TMR6 software event register (TMRx_SWEVT)........................ 168
14.1.4.6 TMR6 counter value (TMRx_CVAL) ........................................ 168
14.1.4.7 TMR6 division (TMRx_DIV).................................................... 168
14.1.4.8 TMR6 period register (TMRx_PR)........................................... 168
14.2 General-purpose timer (TMR3).................................................... 169
14.2.1 TMR3 introduction ......................................................................169
14.2.2 TMR3 main features ...................................................................169
14.2.3 TMR3 functional overview ...........................................................169
14.2.3.1 Count clock .......................................................................... 169
14.2.3.2 Counting mode ..................................................................... 171
14.2.3.3 TMR input function................................................................ 173
14.2.3.4 TMR output function.............................................................. 174
14.2.3.5 TMR synchronization............................................................. 177
14.2.3.6 Debug mode ......................................................................... 179
14.2.4 TMR3 registers ..........................................................................179
14.2.4.1 Control register1 (TMR3_CTRL1) ........................................... 180
14.2.4.2 Control register2 (TMR3_CTRL2) ........................................... 181
14.2.4.3 Slave timer control register (TMR3_STCTRL) .......................... 181
14.2.4.4 DMA/interrupt enable register (TMR3_IDEN) ........................... 182
14.2.4.5 Interrupt status register (TMR3_ISTS) .................................... 183
14.2.4.6 Software event register (TMR3_SWEVT)................................. 184
14.2.4.7 Channel mode register1 (TMRx_CM1) .................................... 184
14.2.4.8 Channel mode register2 (TMR3_CM2) .................................... 186
14.2.4.9 Channel control register (TMR3_CCTRL) ................................ 187
14.2.4.10 Counter value (TMR3_CVAL) ............................................. 187
14.2.4.11 Division value (TMR3_DIV) ................................................ 188
14.2.4.12 Period register (TMR3_PR)................................................ 188
14.2.4.13 Channel 1 data register (TMR3_C1DT) ............................... 188
14.2.4.14 Channel 2 data register (TMR3_C2DT) ............................... 188
14.2.4.15 Channel 3 data register (TMR3_C3DT) ............................... 188
14.2.4.16 Channel 4 data register (TMR3_C4DT) ............................... 189
14.2.4.17 DMA control register (TMR3_DMACTRL)............................. 189
14.2.4.18 DMA data register (TMR3_DMADT) .................................... 189