Astronics PXIe-1209 User manual
PXIe-1209
Dual 100 MHz Pulse Generator
User Manual
Publication No. 981050 REV. A
Astronics Test Systems Inc.
4 Goodyear, Irvine, CA 92618
Tel: (800) 722-2528, (949) 859-8999; Fax: (949) 859-7139
Copyright 2017 by Astronics Test Systems Inc. Printed in the United States of America. All rights reserved.
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FOR YOUR SAFETY
Before undertaking any troubleshooting, maintenance or exploratory procedure, read carefully the
WARNINGS and CAUTION notices.
This equipment contains voltage hazardous to
human life and safety, and is capable of inflicting
personal injury.
If this instrument is to be powered from the AC line (mains) through an autotransformer,
ensure the common connector is connected to the neutral (earth pole) of the power
supply.
Before operating the unit, ensure the conductor (green wire) is connected to the ground
(earth) conductor of the power outlet. Do not use a two-conductor extension cord or a
three-prong/two-prong adapter. This will defeat the protective feature of the third
conductor in the power cord.
Maintenance and calibration procedures sometimes call for operation of the unit with
power applied and protective covers removed. Read the procedures and heed warnings
to avoid “live” circuit points.
Before operating this instrument:
1. Ensure the proper fuse is in place for the power source to operate.
2. Ensure all other devices connected to or in proximity to this instrument are properly grounded or
connected to the protective third-wire earth ground.
If the instrument:
- fails to operate satisfactorily
- shows visible damage
- has been stored under unfavorable conditions
- has sustained stress
Do not operate until performance is checked by qualified personnel.
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Astronics Test Systems i
Table of Contents
Chapter 1 ...........................................................................................................................1-1
Overview and Features.....................................................................................................1-1
Functional Description.................................................................................................................... 1-2
PXIe Interface ............................................................................................................................ 1-3
Pulse and Timing Control Logic ................................................................................................. 1-3
Microcontroller............................................................................................................................ 1-3
Direct Digital Synthesizer (DDS)................................................................................................ 1-3
VCXO ......................................................................................................................................... 1-4
Pin Drivers.................................................................................................................................. 1-4
Front Panel Input Signals........................................................................................................... 1-4
Backplane Trigger Signals ..................................................................................................... 1-4
Operational Modes..................................................................................................................... 1-4
Frequency (Pulse Repetition Rate)............................................................................................ 1-5
Pulse Width ................................................................................................................................ 1-5
Pulse Delay and Double Pulse Spacing .................................................................................... 1-5
Single Pulse or Double Pulse .................................................................................................... 1-5
Run Modes................................................................................................................................. 1-5
Pulse Output .............................................................................................................................. 1-6
Sync Out .................................................................................................................................... 1-6
External Trigger.......................................................................................................................... 1-6
External Gate ............................................................................................................................. 1-6
External Reference Clock .......................................................................................................... 1-6
Hardware Configuration ................................................................................................................. 1-6
Front Panel Signals A & B Input Impedance ............................................................................. 1-7
Sync Out Level........................................................................................................................... 1-7
Mode .......................................................................................................................................... 1-8
Input/Output Signals....................................................................................................................... 1-8
Chapter 2 ...........................................................................................................................2-1
Specifications....................................................................................................................2-1
Maximum Ratings Per Module............................................................................................... 2-1
AC Characteristics Per Channel ............................................................................................ 2-1
Mechanical ............................................................................................................................. 2-3
Bus Compliance ..................................................................................................................... 2-3
Environmental ........................................................................................................................ 2-3
Mechanical ............................................................................................................................. 2-4
Chapter 3 ...........................................................................................................................3-1
Installation.........................................................................................................................3-1
Unpacking and Inspection.............................................................................................................. 3-1
Installing the Module into a PXIe Chassis...................................................................................... 3-1
PXIe-1209 User Manual Publication No. 981050 REV. A
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Software Installation ...................................................................................................................... 3-1
Installing the VISA driver ........................................................................................................... 3-1
Installing the PXI device driver .................................................................................................. 3-2
Installing the LabVIEW instrument driver .................................................................................. 3-2
Installing the LabWindows/CVI instrument driver...................................................................... 3-3
Chapter 4........................................................................................................................... 4-1
Operation .......................................................................................................................... 4-1
Programming ................................................................................................................................. 4-1
Writing Register Values ............................................................................................................. 4-1
Pulse Programming ................................................................................................................... 4-1
Pulse Delay............................................................................................................................ 4-1
Sync Out ................................................................................................................................ 4-2
Frequency (Internal Pulse Repetition Rate) .......................................................................... 4-2
Single Pulse vs. Double Pulse................................................................................................... 4-2
Single, Continuous, and Burst Modes ....................................................................................... 4-3
Follow Trigger Mode .................................................................................................................. 4-3
Pulse Gating .............................................................................................................................. 4-3
Calibration...................................................................................................................................... 4-3
Reference Disciplining ................................................................................................................... 4-4
Interrupts........................................................................................................................................ 4-4
Chapter 5........................................................................................................................... 5-1
Software Operation.......................................................................................................... 5-1
Using the Soft Front Panel............................................................................................................. 5-1
Starting the Soft Front Panel ..................................................................................................... 5-1
Using the LabWindows / CVI Driver .............................................................................................. 5-9
Using the LabVIEW Driver........................................................................................................... 5-11
Chapter 6........................................................................................................................... 6-1
Identification and Configuration Registers.................................................................... 6-1
I/O Registers .................................................................................................................................. 6-1
Control Status ............................................................................................................................ 6-2
Interrupt Control......................................................................................................................... 6-3
Trigger/Gate Control.................................................................................................................. 6-4
Version Info* .............................................................................................................................. 6-4
DDS Frequency - Low ............................................................................................................... 6-5
DDS Frequency - High .............................................................................................................. 6-5
Frequency Divider – Low........................................................................................................... 6-5
Frequency Divider – High .......................................................................................................... 6-5
Pulse Width - Low...................................................................................................................... 6-6
Pulse Width - Mid....................................................................................................................... 6-6
Pulse Width - High ..................................................................................................................... 6-6
Pulse Delay - Low...................................................................................................................... 6-7
Pulse Delay - Mid....................................................................................................................... 6-7
Pulse Delay - High ..................................................................................................................... 6-7
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Astronics Test Systems iii
Double Pulse Spacing - Low...................................................................................................... 6-8
Double Pulse Spacing - Mid....................................................................................................... 6-8
Double Pulse Spacing - High ..................................................................................................... 6-8
Burst Count - Low ...................................................................................................................... 6-9
Burst Count - High...................................................................................................................... 6-9
Output Amplitude – Low Level ................................................................................................... 6-9
Output Amplitude – Low Level ................................................................................................... 6-9
Slew Rate................................................................................................................................. 6-10
Input Threshold Level .............................................................................................................. 6-10
Calibration Control ................................................................................................................... 6-10
Reference Count - Low ............................................................................................................ 6-11
Reference Count - High ........................................................................................................... 6-11
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List of Figures
Figure 1-1, PXIe-1209....................................................................................................................... 1-2
Figure 1-2, PXIe-1209 Functional Block Diagram ............................................................................ 1-3
Figure 1-3, Pulse Terms and Relationships...................................................................................... 1-5
Figure 1-4, PXIe-1209 Hardware Configuration Switches ................................................................ 1-7
Figure 1-5, Front Panel ..................................................................................................................... 1-8
Figure 5-1, Starting Soft Front Panel ................................................................................................ 5-1
Figure 5-2, RI1209e Main Panel ....................................................................................................... 5-2
Figure 5-3, Instrument Menu............................................................................................................. 5-3
Figure 5-4, Configure Menu .............................................................................................................. 5-3
Figure 5-5, Pulse Output Configuration Window .............................................................................. 5-4
Figure 5-6, Sync Output Configuration Window ............................................................................... 5-4
Figure 5-7, Gate & Trigger Configuration Window............................................................................ 5-5
Figure 5-8, M-Triggers Routing Window ........................................................................................... 5-5
Figure 5-9, Gate and Trigger Subwindow ......................................................................................... 5-7
Figure 5-10, External Reference Configuration Window .................................................................. 5-8
Figure 5-11, Front Panel Inputs Configuration Window.................................................................... 5-9
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List of Tables
Table 6-1, I/O Address Map/Command Summary............................................................................ 6-1
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DOCUMENT CHANGE HISTORY
Revision Date Description of Change
Initial Astronics Test Systems release
Publication No. 981050 REV. A PXIe-1209 User Manual
Astronics Test Systems Overview and Features 1-1
Chapter 1
Overview and Features
The PXIe-1209 (Figure 1-1) is a fully programmable, dual independent pulse
generator that allows the generation of precisely-timed pulses of programmable
frequency, pulse width, delay, and amplitude in two channels simultaneously.
Each channel offers operational modes which include single, continuous, burst,
and follow trigger functions. Single, double, and inverted pulses are supported.
Extensive trigger and gating logic provide comprehensive control of pulse timing
independently. Within each channel, the internal base clock can be disciplined to
an external reference clock for long-term stability.
The PXIe-1209 can be used in a wide variety of applications including functional
verification of digital systems, signal simulation, design verification, and research
and development.
Key Features:
Dual Independent Channels
0.1 Hz – 100 MHz
Programmable Pulse Width, Pulse Delay, and Double Pulse Spacing
-1.5 V to +6.5 V Programmable Pulse Output
Programmable Rise/Fall Time
Single Pulse or Continuous Pulsing
Single Pulse, Double Pulse, and Inverted Pulse Modes
Burst Mode (1 to >2B pulses output on command or trigger)
Follow Trigger Mode
External Triggering
Asynchronous or Synchronous Gating Modes
On-board can be disciplined to 1 PPS, 100 PPS, or 10 MHz external clock
for long-term stability
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Overview and Features 1-2 Astronics Test Systems
Figure 1-1, PXIe-1209
Functional Description
The PXIe-1209 utilizes programmable gate array logic, a microcontroller,
digital/analog converters, pin driver devices, and variety of other digital and analog
electronics to provide the pulse generation function. Register-based commands
are received through the PXI interface and acted upon either directly by the pulse
generation logic or the microcontroller. In many cases, the microcontroller
translates the register data into appropriate DAC or programmable clock values to
produce the desired functionality. A simplified block diagram is shown in Figure
1-2.
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Astronics Test Systems Overview and Features 1-3
PULSE
ENABLE
SLEW RATE ADJ
VHI ADJ
VLO ADJ
SYNC OUT
PXIe
Interface
Both
Channels
FPSIGB
FPSIGA
POUT
LEVEL AND IMPEDANCE
SWITCH SELECTABLE
50MHz
VCXO
DDS
PIN
DRIVER -1.5 TO +6.5V
50IMP.
PROG SLEW
+5V OR +6.5V
50IMP.
FIXED SLEW
TRIGA
TRIGB
GATE
TRIG
ENABLE
SYNC
DAC
DAC
MICRO-
CONTROLLER
DAC
PULSE OR SYNC
OEN
A
PULSE OR SYNC
OENB
PIN
DRIVER
PULSE AND TIMING
CONTROL LOGIC
REFCLK
Figure 1-2, PXIe-1209 Functional Block Diagram
PXIe Interface
The PXIe Interface allows communication between the PXIe-1209 and the carrier
module. The interface is an asynchronous 32-bit data bus with interrupt and
trigger capabilities. A single PXIe channel controls both Channel 1 and Channel 2
via internal bus interfaces with address allocations for both channels. The internal
bus interfaces are not user accessible.
Pulse and Timing Control Logic
The pulse and timing control logic provides the main control and generation of the
raw pulse. It contains the user programmable control and status registers, the
delay lock loop elements for precise clock control, the interface logic for the
microcontroller and other functions, and numerous counters and control logic
elements for the pulse formatting functions.
Microcontroller
The microcontroller performs extensive interface functions to program the DDS,
DACs, driver, counter registers, and delay values to produce the desired pulse.
The DDS and DACs are programmed through the pulse and timing control logic
via a serial interface to set the appropriate frequency, delay values, and pin driver
amplitude. New values are computed anytime a user modifies a user register.
Direct Digital Synthesizer (DDS)
The DDS produces the main internal clock that controls the output pulse repetition
rate. The DDS output is converted to a square wave clock signal using a high
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Overview and Features 1-4 Astronics Test Systems
speed comparator.
VCXO
The voltage controlled oscillator (VCXO) provides the base clock for the module.
Even though the internal VCXO is fairly accurate and stable on its own, it can also
be disciplined to a high precision 1 PPS, 100 PPS, or 10 MHz external clock, if one
is available.
Pin Drivers
The pin driver provides the output voltage, current, and slew rate of the output
pulse and Sync Out signals. The output impedance of both pulses is fixed at 50 Ω.
Front Panel Input Signals
Two front panel trigger signals are provided for trigger, gate, or clock reference
control from an external source. The inputs have switch selectable input
impedance and threshold level control.
Backplane Trigger Signals
Four backplane PXI trigger signals are provided via trigger bus allocation via DLL
drivers. As inputs, these signals can be used for external control of the trigger,
gate, or clock reference. As outputs, they can be used to output the pulse and
Sync Out signals. To utilize this feature, the PXI carrier must support triggers
(third row on PXI interface). Trigger operation differs depending on the carrier; see
your carrier’s documentation for details.
Operational Modes
The PXIe-1209 can be configured for many different operating modes. In order to
fully understand the operation, it is important to have a clear understanding of the
terminology used and relationship of the various signals as shown in Figure 1-3.
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Astronics Test Systems Overview and Features 1-5
Figure 1-3, Pulse Terms and Relationships
Frequency (Pulse Repetition Rate)
The frequency of the output pulse can be controlled internally using the frequency
value and mode registers or externally using an external trigger signal.
Pulse Width
The width of the output pulse can be controlled internally using the pulse width
register or externally using an external trigger signal.
Pulse Delay and Double Pulse Spacing
The time from the Sync Out signal to the first output pulse and the space between
the first pulse and second pulse, if Double Pulse is enabled, is programmable
using the pulse delay and double pulse spacing registers.
Single Pulse or Double Pulse
The output pulse can be either a single or a double pulse. In Double Pulse mode,
the widths of both pulses are the same.
Run Modes
There are four run modes: single, continuous, burst, and follow trigger. In all
cases, except follow trigger, the output pulse can be a single pulse or a double
pulse. The run event can be initiated by software or an external trigger. Single
pulse mode produces one pulse (or a double pulse) for each software or trigger
signal. Continuous mode continues pulsing until software disables the run. Burst
mode allows a preset number of pulses to be produced. In the follow trigger
mode, the output pulse follows both the pulse width and period of the trigger input.
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Overview and Features 1-6 Astronics Test Systems
Pulse Output
The amplitude of the output pulse is programmable using the high and low level
amplitude registers. The high level of the pulse and the low level of the pulse are
controlled separately. The output can be enabled or disabled (placed in a high-
impedance state) and the polarity (active-high or active-low) and slew rate are
programmable. The output impedance is fixed at 50 Ω.
Sync Out
The Sync Out signal indicates the start (T0) of the pulse generation internal timing.
The signal output can be enabled or disabled (placed in a high-impedance state)
and its polarity (active-high or active-low) is programmable. The output level is
switch selectable for 5.0 V or 6.5 V. The output impedance is fixed at 50 Ω.
External Trigger
An external signal can be used to control the pulse repetition rate, instead of the
internal counter. Either the positive going or negative going transition can be
used. Additionally, the output pulse can follow the pulse width and period of the
trigger input signal.
External Gate
The module can be configured to enable pulsing only during the presence of an
external signal. The gate operation can be asynchronous or synchronous (see
Pulse Gating in Chapter 4 for details). The external gate can be active-high or
active-low.
External Reference Clock
An external 1 PPS, 100 PPS, or 10 MHz signal can be used to discipline the
internal clock. After an initial 10-minute module warm-up period, the internal clock
will discipline in typically 30 seconds to within one decade of the external
reference, up to the specified stability. Software register bits allow enabling the
disciplining operation and provide status of the state of the reference and the
internal clock.
Hardware Configuration
The PXIe-1209 contains three sets of four switches that select the input
impedance of the FPSIGA and FPSIGB front panel inputs, the mode of operation
for the pulse generation logic, and the Sync Out level and impedance. The
switches are located as shown in Figure 1-4. The switches are only accessible
with the module removed from the carrier.
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Astronics Test Systems Overview and Features 1-7
Figure 1-4, PXIe-1209 Hardware Configuration Switches
Front Panel Signals A & B Input Impedance
These switches select the input impedance of the signal A and signal B front
connector signals.
Input Signal A Impedance Switch
INA
>100 KΩOFF
50 ΩON
Input Signal B Impedance Switch
INB
>100 KΩOFF
50 ΩON
Sync Out Level
These switches control the output level and impedance of the Sync Out signal.
Sync Out Level (no load) Switch
CONFIG 3
+5 V OFF
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Overview and Features 1-8 Astronics Test Systems
+6.5 V ON
Mode
These switches control special modes of operation. These modes are undefined
at this time, but are available for future implementations with special purpose
modes.
Special Mode 1 Switch
CONFIG 1
Normal OFF
Factory Debug Mode* ON
Special Mode 2 Switch
CONFIG 2
Undefined OFF
Undefined ON
CONFIG Switch 4 is not used.
Input/Output Signals
The front panel input/output signals for each channel are as shown in Figure 1-5
and are briefly described below. The connector shield of each of the connectors
are tied to chassis ground.
Figure 1-5, Front Panel
INA This MCX connector is the input signal A. This input is software
configurable as the trigger, gate, or reference clock signal. The threshold
level and input active high/low are programmable. The input impedance
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