Bose BUILT-INvisible TA-1 User manual

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CONTENTS
PROPRIETARY INFORMATION
THIS DOCUMENT CONTAINS PROPRIETARY INFORMATION OF
BOSE CORPORATION WHICH IS BEING FURNISHED ONLY FOR THE
PURPOSE OF SERVICING THE IDENTIFIED BOSE PRODUCT BY AN
AUTHORIZED BOSE SERVICE CENTER OR OWNER OF THE BOSE
PRODUCT, AND SHALL NOT BE REPRODUCED OR USED FOR ANY
OTHER PURPOSE.
CAUTION: The Bose® BUILT-INvisible® TA-1 amplifier con ains
no user-serviceable par s. To preven warran y infrac ions,
refer servicing o warran y service s a ions or fac ory service.
Safe y Informa ion ............................................................................................................................2
Elec ros a ic Discharge Sensi ive (ESDS) Device Handling .........................................................2
Warran y .............................................................................................................................................2
Specifica ions ....................................................................................................................................3
Speaker EQ Curves ..........................................................................................................................4
Theory of Opera ion ................................................................................................................... 5-21
Disassembly/Assembly Procedures ....................................................................................... 21-22
Tes Procedures ........................................................................................................................ 23-30
Par Lis No es.................................................................................................................................31
Main Par Lis , Digi al BUILT-INvisible® Amplifier (see Figures 1, 2 and 3) ................................31
Figure 1. I put/Output PCB, DSP PCB a d Chassis Exploded View .............................................32
Figure 2. Amplifier PCB Assembly with Heatsi k Exploded View ..................................................33
Figure 3. Assembled Amplifier with Heatsi k Ope ........................................................................34
Elec rical Par Lis s ................................................................................................................... 35-55
I/O PCB Elec rical Par Lis ...................................................................................................... 35-41
DSP PCB Elec rical Par Lis ................................................................................................... 42-48
Amplifier PCB Elec rical Par Lis ........................................................................................... 49-55
Packaging Par Lis , Digi al BUILT-INvisible Sys em (see Figure 4) ...........................................56
Figure 4. Digital BUILT-INvisible System Packagi g View ..............................................................56
In egra ed Circui Diagrams ..................................................................................................... 57-61
Appendix.................................................................................................................................... 62-80
Accessories used wi h he TA-1 Amplifier.............................................................................. 62-63
CD-50 Sys em Assembly Par Lis ................................................................................................63
BUILT-INvisible Series II Bass Module .........................................................................................64
SE-1 Audio/Video Swi cher ............................................................................................................65
Figure 5. SE-1 Audio/Video Switcher Packi g Diagram .................................................................65
CI-1 Con rol In egra or ...................................................................................................................66
Figure 6. CI-1 Co trol I tegrator Packi g Diagram .........................................................................66
Figure 7. TA-1 Amplifier Test Setup Diagram ...................................................................................67
Figure 8. TA-1 Amplifier Co ectio Diagram .................................................................................68
Table 1. Satellite Speaker EQ DIP Switch Setti gs ........................................................................71
Compu er Se up Procedure ..................................................................................................... 72-73
Amplifier Firmware Upgrade Procedure.......................................................................................74
TA-1 Amplifier TAP Command Tables ..................................................................................... 75-78
Sys em Troubleshoo ing Informa ion ..................................................................................... 79-80
Figure 9. TS-200 System Co ectio Details .................................................................................81
Figure 10. TS-400 System Co ectio Details ...............................................................................82
Figure 11. TS-600 System Co ectio Details ...............................................................................83

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SAFETY INFORMATION
ELECTROSTATIC DISCHARGE SENSITIVE (ESDS)
DEVICE HANDLING
This u it co tai s ESDS devices. We recomme d the followi g precautio s whe repairi g,
replaci g or tra sporti g ESDS devices:
• Perform work at a electrically grou ded work statio .
• Wear wrist straps that co ect to the statio or heel straps that co ect to co ductive
floor mats.
• Avoid touchi g the leads or co tacts of ESDS devices or PC boards eve if properly
grou ded. Ha dle boards by the edges o ly.
• Tra sport or store ESDS devices i ESD protective bags, bi s, or totes. Do ot i sert
u protected devices i to materials such as plastic, polystyre e foam, clear plastic bags,
bubble wrap or plastic trays.
The Bose® BUILT-INvisible® TA-1 Theater Amplifier is covered by a 1-year tra sferable
limited warra ty
WARRANTY
1. Parts that have special safety characteristics are ide tified by the symbol o schematics
or by special otes o the parts list. Use o ly replaceme t parts that have critical characteristics
recomme ded by the ma ufacturer.
2. Make leakage curre t or resista ce measureme ts to determi e that exposed parts are
acceptably i sulated from the supply circuit before retur i g the u it to the customer.
Use the followi g checks to perform these measureme ts:
A. Leakage Curren Ho Check-With the u it completely reassembled, plug the AC li e cord
directly i to a 120V AC outlet. Do ot use a isolatio tra sformer duri g this test. Use a leakage
curre t tester or a meteri g system that complies with America Natio al Sta dards I stitute
(ANSI) C101.1 "Leakage Curre t for Applia ces" a d U derwriters Laboratories (UL) 6500 / IEC
60056 paragraph 9.1.1. With the u it AC switch first i the ON positio a d the i OFF positio ,
measure from a k ow earth grou d (metal waterpipe, co duit, etc.) to all exposed metal parts
of the u it (a te as, ha dle bracket, metal cabi et, screwheads, metallic overlays, co trol
shafts, etc.), especially a y exposed metal parts that offer a electrical retur path to the chas-
sis. A y curre t measured must ot exceed 0.5 milliamp. Reverse the u it power cord plug i the
outlet a d repeat test. ANY MEASUREMENTS NOT WITHIN THE LIMITS SPECIFIED HEREIN
INDICATE A POTENTIAL SHOCK HAZARD THAT MUST BE ELIMINATED BEFORE RE-
TURNING THE UNIT TO THE CUSTOMER.
B. Insula ion Resis ance Tes Cold Check-(1) U plug the power supply a d co ect a jumper
wire betwee the two pro gs of the plug. (2) Tur o the power switch of the u it. (3) Measure the
resista ce with a ohmmeter betwee the jumpered AC plug a d each exposed metallic cabi et
part o the u it. Whe testi g 3 wire products, the resista ce measured to the product e closure
should be betwee 2 a d i fi ite MOhms. Also, the resista ce measured to exposed i put/output
co ectors should be betwee 4 a d i fi ite MOhms. Whe testi g 2 wire products, the resis-
ta ce measured to exposed i put/output co ectors should be betwee 4 a d i fi ite MOhms.
If it is ot withi the limits specified, there is the possibility of a shock hazard, a d the u it must
be repaired a d rechecked before it is retur ed to the customer.

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SPECIFICATIONS
Power Ou pu (all channels loaded): Bass Cha el: 140 Watts at 100 Hz i to 4 Ohms
Satellite Cha els: 35 Watts at 1 kHz i to 8 Ohms
Dis or ion: Bass Cha el: < 0.4% THD at 0.5W
Satellite Cha els: < 0.1% THD at 0.5W
Ou pu Noise: Bass Cha el: < 2 mVrms, u weighted
Satellite Cha els: < 400 uVrms, A weighted
Signal o Noise Ra io: 96 dB
DC Offse : < 50 mVdc, all cha els
Sa elli e Balance: + 1.5 dB for volume setti gs 0 to -79 dB
Sa elli e Separa ion: > 40 dB at 1 kHz, > 30 dB at 10 kHz, stereo mode
S andby Line Power: < 5 W at rated li e voltage (plugged i , music ce ter off)
Idle Line Power: < 15 W at rated li e voltage (plugged i , music ce ter
o a d muted)
Analog Inpu Impedance: 5.0k Ohms + 10% at 1 kHz
S/PDIF Inpu Impedance: 75 Ohms + 10% at 100 kHz
Analog Inpu Sensi ivi y: 0.5 Vrms i put at 100 Hz/1 kHz for rated power i
bass/satellite cha els
Analog Inpu CMRR: > 40 dB at 60 Hz, withi + 12V commo mode
Compressor: > 20 dB compressio from 200-10 kHz with distortio
throughout the compressio ra ge < 3% at 1 kHz a d
< 4% at 50 Hz
Turn On Delay: 1.5 Seco ds maximum
Turn Off Delay: < 200 mS
Volume Con rol A enua ion Range: 0 dB to -80 dB
Cen er Volume Con rol Range: -6 dB to 0 dB i 1 dB steps, 0 dB to 9 dB i 1.5 dB steps
Surround Volume Con rol Range: -6 dB to 0 dB i 1 dB steps, 0 dB to 9 dB i 1.5 dB steps
Audio Inpu s: Audio a d audio for video
Con rol Inpu s: IR, Serial (RS-232), Speaker Data (Music Ce ter), a d
TV Se se (logic level)
Indica ors: Power, Sta dby/Comma d, Setup/A alog I put, Fault/
Digital I put
Power Supply: 110-120 Vac, 60 Hz, 400W, 3.63 Amps
Dimensions: 15.75"H x 10.75"W x 3.38"D (40cm x 27.3cm x 8.6cm)
Uni Weigh : 16 lbs (7.25 kg)

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CS-2 Sa elli e Speaker EQ Curve Jewel Cube® Sa elli e Speaker EQ Curve
Acous imass® Series II Bass Module
EQ Curve
Residen ial 1.2 Ohm Speakers
EQ Curve
Residen ial 131® Sa elli e Speaker EQ Curve
VCS-10® Cen er Channel Speaker EQ Curve
SPEAKER EQ CURVES

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THEORY OF OPERATION
General Overview
The Bose® Digital BUILT-INvisible® amplifier is a six-cha el system with DSP-based Dolby®
Digital 5.1 decodi g a d Videostage® II sig al processi g. It is i te ded for built i i stallatio s i
Bose reside tial sou d systems. Its six cha els will ormally be prese ti g sou d for home
theater, i 5.1 format.
The Digital BUILT-I visible amplifier has a total of six audio i puts:
- stereo a alog audio for a music source
- stereo a alog audio for a video source
- four digital audio for stereo or multi-cha el Dolby Digital 5.1 audio (SPDIF coax)
Furthermore, the Digital BUILT-I visible amplifier has a umber of co trol ports:
- Lifestyle® music ce ter compatible i put
- RS-232C serial bi-directio al port
- TV Se sor i put
- Remote IR se sor i put
- IR diode
The amplifier respo ds to the various SmartSpeaker comma ds issued from the various Bose
Lifestyle® head-e d u its, such as the CD-5, CD-20 a d the PMC/MRI used with the Lifestyle®
40 a d 50 systems. The amplifier ca also be co trolled via a exter al master remote co trol
(Philips) used i co ju ctio with either the CI-1 Co trol I tegrator or the SE-1 Expa der.
The Digital BUILT-I visible amplifier is packaged i a metal e closure, co sisti g of a steel base
a d a alumi um extrusio cover. I ter ally, the electro ics co sist of:
- I put/Output (I/O) PCB
- Power Amplifier PCB
- DSP (Digital Sig al Processor) PCB
- Toroidal power tra sformer
Inpu /Ou pu (I/O) PCB
No e: U less otherwise oted, refer to the schematic diagram for the I put/Output board for the
followi g i formatio . The refere ces i brackets [ ] are the grid coordi ates for the compo e t.
Analog audio inpu s
The audio sig als are applied at J6 [A4] a d J21 [A3]. J6 is used for Music Audio I puts a d J21
is used for Video Audio I puts. U1, 2, 7, & 8 [A2-4], dual op amps, comprise the four differe tial
amplifiers for these i puts. Each differe tial amplifier uses two op amp sectio s. The o -i vert-
i g (+) i put passes through two i verti g sectio s, while the i verti g (–) i put passes through
o ly the seco d i verti g sectio . I this way, the amplifier respo ds to the differe ce betwee
the o -i verti g (+) i put a d the i verti g (–) i put. Exter al sig als appeari g i commo o
the two i put pi s (capacitively or i ductively coupled oise) are subtracted a d are largely
elimi ated. To improve commo mode rejectio , the critical resista ces are packaged i a preci-
sio thi film etwork RN1 [A4] with a high degree of matchi g. To protect the differe tial amplifier
agai st ESD a d the prese ce of higher tha ormal audio sig als with or without power
prese t, series resistors R105 a d R106 [A4] a d D25 a d D26 [A4] provide clamps. Further
ESD protectio comes from the spark gap PCB patter s. C3 a d C5 [A4] provide low pass
filteri g to remove RF that could be picked up by i put wiri g.

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THEORY OF OPERATION
Inpu /Ou pu (I/O) PCB (con inued)
S1 [A3] sectio 1, a user accessible switch, is used to co ect the left a d right i verti g (–)
pi s of the Music I puts together. S1-sectio 2 is used to co ect the left a d right – pi s of the
Video I puts together. This is sometimes desirable for certai i stallatio wiri g situatio s, such
as where the source wiri g prese ted to the TA-1 amplifier is left o -i verti g (+), right +, a d a
commo grou d (u bala ced). O e might choose to close S1 a d co ect left + to left +, right +
to right +, a d commo grou d to left – (S1 will tie left – to right – i this case).
Analog audio inpu selec or
The two stereo i puts, Music Audio a d Video Audio, after passi g through their differe tial
amplifiers, are prese ted to U3 [B4], a a alog multiplexer at pi s 4, 5, 12 a d 13. Whe the
Set_Audio (U3 pi 1) i put is high, the Video Audio i put is selected a d passes through. Whe
the Set_Audio li e is low, the Music Audio i put is selected. From U3’s outputs at pi s 8 a d 9,
the a alog audio sig als pass to J4-12 a d 14, which carries them o to the DSP PCB, where
they e ter the codec U100, [DSP schematic sheet 1, C4] a d are co verted to digital audio
sig als.
Digi al audio inpu s
The four S/PDIF digital audio sig als are delivered via J7 [C3], each i differe tial form. A typical
S/PDIF source, Source 1, is prese ted o J7-4 a d J7-5 a d passes through a DC blocki g
capacitor (to keep the small tra sformer free of a DC bias) a d i to T1 [D3]. At the seco dary,
the tra sformer is termi ated i 75 Ohms to match the source impeda ce for best pulse fidelity.
Also at the seco dary, the sig al is refere ced to grou d a d clamped to about +/-0.65 volts by
diode D8. The clamp is o ly active for higher tha ormal S/PDIF sources, but also protect the
i puts of U9 [D3], especially if sig als are prese t while the power is off.
Digi al audio inpu selec or
The four si gle-e ded digital sources are prese ted to U9 [D3], a a alog multiplexer. Sig als
DIG_SEL_A a d DIG_SEL_B from the microco troller U5 [C4] select o e of the four i puts for
passage through U9. Sig al DIG_EN ca be used to disable the output regardless of the source
selectio . From U9’s output, the selected SPDIF sig al passes to J4-8 [E4], which carries it o to
the DSP PCB, where it e ters a codec U100, [DSP schematic sheet 1, C4] a d is u packed to
yield the embedded digital audio sig als.
Power amplifier ou pu s
The power amplifier output devices U700, U701, U703, U704, U705 a d U707 (a d associated
power tra sistors) [amplifier PCB schematic sheet 1] are located o the power amplifier PCB
which is attached to the extruded top cover. The amplifier output sig als a d their grou d retur s
are carried via a wire har ess from J701 [power amp schematic sheet 2, A-C7] o the amplifier
PCB to J22 [D2] o the I/O PCB. The six amplifier outputs are directly wired to the appropriate
loudspeaker co ectors alo g the right ha d edge of the PCB. The RC etworks [E2] co tribute
to amplifier stability a d reduce EMC a d ESD eve ts.
Power supplies, +8V and +5V
The I/O PCB receives the AC mai s power via J5 [C2] a d S9, a d through fuses F3 a d F4.
The +8V a d +5V supplies provide keep-alive voltages to the I/O PCB co trol circuitry that
e able the amplifier to remai i sta dby mode, but also allow it to wake up a d go i to operate
mode whe it receives comma ds to do so. Whe mai power switch S9 is o , the +8V a d +5V
supplies are e ergized. At first, the amplifier will be i sta dby mode, characterized by the
prese ce of +8V a d +5V, but with the triac Q6 [C1] off.

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THEORY OF OPERATION
Inpu /Ou pu (I/O) PCB (con inued)
Power supplies, +8V and +5V (con inued)
U til Q6 is tur ed o , the rest of the amplifier (the Power Amplifier a d DSP PCBs) is off.
The AC mai s is applied to T5 [C1], rectified by D22 (full wave bridge), a d filtered by C31.
The +5V supply is created by U12 [C1] i a sta dard 3 termi al regulator applicatio ; so too is
+8V, created by U14. These supplies o ly deliver very low power outputs, capable of o more
tha two to three watts total.
Power supply, main ransformer con rol
The amplifier’s mai power supply is created from the seco daries of a large toroidal tra sformer
that is tur ed o a d off by the triac Q6. This is the tra sformer mou ted i the ce ter of the I/O
PCB. The seco dary leads of this tra sformer co ect via J702 to the Power Amplifier PCB,
where various power supply voltages are created, i cludi g the +/-12V supplies retur ed to the
I/O PCB to power the op amps a d sig al selectors. The +/-12V leave the amplifier PCB at J701
pi s 13 a d 15 a d e ter the I/O PCB at J22 pi s 13 a d 15.
A logic sig al (AMP_POWER) from the microco troller U5 [C4] at pi 11, goes high to tur o
the mai power supply. AMP_POWER high causes base curre t i Q7 [C1], which i tur
causes the LED i Q5 to tur o . The opto-coupled LED tur s o the i ter al triac i Q5 which,
fi ally, tur s o the gate of triac Q6 a d e ergizes the tra sformer.
Pulse Wid h Modula ed one con rol low pass fil ers, U15
The I/O PCB i terprets user comma ds to cha ge the bass a d/or treble levels by deliveri g a
a alog voltage betwee 0V (cut), +2.5V (flat), a d +5V (boost) to the DSP PCB. The micro-
co troller U5 develops this a alog voltage by co trolli g two of its output pi s i pulse width
modulatio mode. The i here t switchi g activity i PWM outputs requires a low pass filter, i
this case a 2 d order filter co sisti g of passive compo e ts a d the dual op amp U15 [C2].
Clamp diodes D36 a d D38 o the op amp outputs keep the filter output withi bou ds for its
desti atio , the DSP microco troller U202 o the DSP PCB. The sig als TREBLE a d BASS
are passed to the DSP microco troller U202 via J4-1 a d J4-2 [E4].
TV Sensor inpu
J11 [A1], a three pi co ector, provides grou d a d +8V (via resetable fuse F2 [A1]) for use by
a small TV se sor that must be attached to the TV mo itor i the home theater. The TV se sor
circuitry retur s a DC sig al via J11-1 which, whe high, i dicates that the TV set is o . This will
cause the amplifier to tur o (if it is ot already o ). The TV se sor i put is mo itored by
microco troller U5 [C4] at pi 8.
IR inpu
J10 [A1] acts as the gateway for i comi g demodulated IR sig als used by remote co trols.
These sig als are ultimately mo itored by the microco troller U5 [C4] a d are se t to the DSP
PCB at J4 [E4]. O e form of IR delivery is the electrical sig al (logic level) from a exter ally
mou ted IR receiver chip. This would typically be located i the home theater room, where it
would pick up IR radiatio from a user remote co trol, decode it, a d se d it by wire to J10-3.
This sig al is clamped a d se t to AND gate U16 [B1], which acts as a OR selector for low
levels comi g from this IR i put a d from the i ter al IR se sor. The seco d form of IR delivery
is via a electrical sig al se t to J10-1 a d –2. Whe this sig al is asserted, the i ter al IR
emitter D3 [A1] is tur ed o a d emits IR withi the amplifier. This optically couples to IR se sor
U11 [A1] which toggles low a d high, decodi g the IR sig al. This sig al passes to U16’s seco d
i put, where it is OR’d with the IR source discussed above. Fi ally, the IR sig al is se t to the
microco troller U5 [C4] as the sig al IR_IN o U5 pi 7.

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THEORY OF OPERATION
Inpu /Ou pu (I/O) PCB (con inued)
Music Cen er inpu
J8 [A1], a four pi co ector, provides a co ectio from a Bose® Lifestyle® music ce ter to the
amplifier. This co ector serve two fu ctio s. It ca be used for co ectio to a Bose Lifestyle®
music ce ter or alter ately for remote termi al access by mea s of a IBM compatible PC.
A table will help explai this.
I the Remote Termi al Access mode, a system i staller ca set up a otebook PC i the home
theater room a d ru I stallerTM software to custom equalize a d bala ce the amplifier system
for the customer’s particular home theater room. The i staller would co ect the PC’s RS-232C
serial output to the Lifestyle® co ector o the Bose wall pa el, temporarily disco ecti g the
Lifestyle® music ce ter. Switchi g betwee the two modes is accomplished via the DPDT relay
K1 [A1]. K1, show i the dee ergized state (Normal Lifestyle® mode), is co trolled by the logic
level sig al provided to pi 3 whe the remote termi al is prese t a d has activated DTR.
RS-232C inpu /ou pu
The amplifier i some i stallatio s may work e tirely u der RS-232C co trol. Such i stallatio s
may have Crestro or AMX remote co trol devices. J9 [A2] provides for RX, TX, a d grou d
co ectio s to such a termi al. Si ce RS-232 sources ca prese t electrical waveforms swi g-
i g betwee up to +/-12V, the RX sig al is passed through a special RS-232C to TTL tra slator,
part of IC U10. I the same fashio , to permit the amplifier to tra smit a bipolar TX sig al, the TX
source is buffered o the way out through the output sectio of U10.
S4, Speaker EQ swi ch, and J1, Header o Tes Accessory
The four sig als co trolled by S4 [B3] are read by the microco troller U5 [C4] duri g i itial
power-up of the amplifier. Refer to the Appe dix of this ma ual for the EQ setti gs of S4.
J1 co ects the I/O PCB with the test accessory. This co ector is ot used o productio
amplifiers.
J8 Func ions
J8
pin Mode: Normal Lifes yle
connec ion
Mode: Remo e erminal access
1Tur _o sig al from Lifestyle to
the amplifier
RS-232 RX li e, data se t from RS-232C
termi al or PC to the amplifier
2Speaker data se t from Lifestyle
to the amplifier
RS-232C TX li e, data se t from the
amplifier to RS-232C termi al or PC
3 A te a sig al DTR: RS-232C termi al or PC sets this
high to tell the amplifier to operate i the
Remote Termi al Access mode
4 grou d refere ce grou d refere ce

9
THEORY OF OPERATION
Inpu /Ou pu (I/O) PCB (con inued)
Power supply failure moni or level ransla or
There are four power supplies o the power amplifier PCB, derived as two pairs of symmetrical
bipolar supplies. By tyi g each of these supplies i to a ode by appropriate resistor values, we
have a ode that sits at zero volts whe all supplies are ormal. If o e or more supplies deviates
sufficie tly, we wa t to detect this as a error. The ode PROTECT is brought out of the amplifier
PCB at J701 pi 11 [amplifier sheet 2, A7] a d o to the I/O PCB at J22 pi 11 [D2] a d co ects
to Q1 a d Q2 [D2]. Q2 tur s o whe PROTECT exceeds about 0.5V, while Q1 tur s o whe
PROTECT exceeds about –0.5V. This dual tra sistor’s output (Q1 collector) is ormally high,
reflecti g the state where all six power supplies o the power amplifier PCB are withi ormal
limits. Whe either tra sistor tur s o , the output sig al BUF_PROTECT_N out of Q1 goes low,
i dicati g a failure. The PROTECT sig al also becomes active whe there is a DC offset failure
i the bass speaker amplifier.
Whe the PROTECT sig al becomes active, the microco troller (U5) [C4] o the I/O PCB
respo ds by placi g the u it i to the Sta dby state, where the mai power tra sformer is de-
e ergized. The Fault LED D29 [D4] flashes o a d off whe this occurs. The ext time a user
comma d is issued, it attempts to tur o , a d will stay o if the fault has bee cleared; other-
wise, it will agai switch to the Sta dby state.
Microcon roller U5 and rela ed circui s
The I/O PCB requires its ow microco troller to mo itor the serial i terfaces, the i staller DIP
switches, the TV se sor, etc. It is respo sible for passi g alo g co trol comma ds to the
microco troller U202 [DSP schematic sheet 2, C5] o the DSP PCB. The I/O PCB’s micro-
co troller U5 is clocked i ter ally by a oscillator usi g the crystal Y1 [C3]. The microco troller
ca write a d read to the optio al ( ot i stalled) EEPROM U6 [C3]. A reset ge erator U4 [C4]
e sures that the microco troller wakes up a d executes its reset routi e whe power is tur ed
o or mome tarily i terrupted. The microco troller ha dles the 3 LEDs [D4] Comma d (D28),
Fault (D29), a d Setup (D30). It also reads the co figuratio DIP switches co tai ed i S7 [D4],
as well as the speaker EQ switches S4 [B3]. Other fu ctio s (bass a d treble PWM outputs,
etc.) have bee me tio ed elsewhere i this prese tatio .
Digi al Signal Processor (DSP) PCB
Signal Processing
No e: U less otherwise oted, refer to the schematic diagrams for the DSP board for the follow-
i g i formatio . The refere ces i brackets [ ] are the schematic sheet a d grid coordi ates for
the compo e t.
The Digital BUILT-INvisible® amplifier has the ability to receive a digital S/PDIF bitstream, either
PCM (digitized 2-cha el audio) or the AC-3 output from up to four separate digital sources.
AC-3, also k ow as Dolby® Digital, is a perceptual codi g a d data compressio tech ique that
allows 5 wideba d cha els a d o e low freque cy bass cha el (5.1) to be compressed i to
less ba dwidth tha would be required for 2-cha el PCM.
The Videostage® 5 processi g used i the amplifier expa ds a L, R i put pair i to L, C, R, S
a d bass, but adds a few ew features over previous versio s of Videostage, such as stereo
surrou d cha els a d a mo o to 5 cha el mode. The mo o to 5 cha el mode is a way of
processi g a mo o sou dtrack such that all 5 speakers receive parts of the sig al. The amplifier
will also accept two a alog i puts directly at the i put jacks.

10
THEORY OF OPERATION
Digi al Signal Processor (DSP) PCB (con inued)
Power Supplies
There are several sets of i ter al power supply voltage rails. These voltages origi ate with the
mai power tra sformer located i the ce ter of the I put/Output (I/O) PCB. There is also a small
keep-alive tra sformer T5 [I/O PCB schematic, C1] located o the I/O board itself that allows the
amplifier to be tur ed o by SmartSpeaker comma ds.
The power amplifiers are supplied with both +40 a d +20 VDC u regulated rails, as determi ed
by the Class G circuitry. These rails are developed from the tra sformer seco daries diode
bridges B700 a d B701 [amplifier schematic sheet 2, A/B 3/4] a d their associated capacitor
ba ks.
The digital circuitry o the DSP PCB requires two differe t regulated voltages, +5V a d +3.3V.
The +5V regulator U1 [sheet 1, A5] is a sta dard 3 termi al li ear regulator i a surface mou t
package a d is located o the DSP PCB. It’s powered from the +20V rail via fusi g resistor
R704 [amplifier schematic sheet 2, C6] o the amplifier PCB, a d supplies about 120mA to the
DSP PCB, most of which is co sumed by the microco troller a d codec.
The +3.3V regulator U500 [sheet 4, D4] is a switch-mode regulator a d must be located u der
the shield to avoid EMI problems (harmo ics of the 100 kHz switchi g freque cy will stray i to
the AM broadcast ba d if left u shielded). This regulator is also powered from the +20V rail a d
supplies about 350mA to the DSPs.
Operatio of the 5V li ear regulator is very simple. Curre t is supplied to the regulator via sur-
face-mou t power resistors R10 a d R11 [sheet1 A5], which drop the voltage supplied to the
regulator to avoid excessive power dissipatio . The regulator eeds a mi imum of about 7V at its
i put termi al to stay i regulatio a d it should be able to do this eve as the +20V rail sags to
+10V or so.
Operatio of the +3.3V switch-mode regulator is more complicated. I its simplest terms, the
u regulated i put is “chopped” at about 100 kHz, a d the resulti g pulse trai is low-pass filtered
to extract the DC. This DC output is compared to a +3.3V refere ce, a d the duty cycle of the
switchi g waveform is adjusted accordi gly. The high-side switch (the switch that co ects
+20V to the output filter) is i tegrated i to the co troller, while the low-side switch (the switch that
co ects grou d to the output filter) is a exter al diode D500. Whe the co troller is ru i g,
you should be able to observe the switchi g waveform at L500.
Microcon roller
The microco troller U202 o the DSP PCB is used for the followi g housekeepi g a d
co trol fu ctio s:
to i terpret SmartSpeaker comma ds from the head-e d.
to i terpret special test mode comma ds from the fu ctio al tester.
to store a d retrieve data from o volatile memory (U201).
to boot a d reprogram the codec (U100) as required by the operati g mode of the system.
- to mo itor for bass a d treble PWM voltage level from U15 o the I/O board.
- DC offset o the amplifier outputs.
- PCB over-temperature.
- prese ce/abse ce of a digital S/PDIF sig al.

11
THEORY OF OPERATION
Digi al Signal Processor (DSP) PCB (con inued)
Microcon roller (con inued)
to seque ce the amplifier a d codec mute li es as required.
to boot a d mo itor the performa ce of the DSPs.
a d relay i formatio to/from DSPs.
In de ail:
1. SmartSpeaker comma ds are i terpreted by watchi g for digital activity o the serial data
i put li e (J5, pi 12 [sheet 1, C8]). This serial i put ca be either the “sta dard” SmartSpeaker
protocol, compatible with the outputs of CD-5, CD-20, etc., or it ca be 4800 baud RS232 with
5V logic levels. The microco troller decides which protocol to use based o the voltage level
prese t o the serial data i put at boot time. If the li e is low, it assumes RS232; if the li e is
high, it assumes SmartSpeaker. It checks o ly o ce, at boot time, so switchi g from o e proto-
col to the other requires a power cycle to reboot the system.
2. Test mode comma ds are special comma ds to facilitate testi g, or to retrieve stored i forma-
tio from the o volatile memory. Test mode comma ds are RS232 o ly, e.g., the revisio of the
firmware ca be queried by se di g the comma d “tv”, the a swer “2200/2000” might come
back o the serial data output li e. This would i dicate versio 22.00 for the microco troller a d
versio 20.00 for the DSPs.
3. The o volatile memory is used to store the followi g i formatio :
choice of equalizatio curve.
system, ce ter, a d surrou d volume setti gs at power-dow .
US or Euro bass to e co trol prefere ce.
system usage statistics.
umber of times system was powered off.
mi utes spe t powered o .
4. The codec U100 [sheet 1, C4] has a fair umber of i ter al registers, all of which must be set
up properly for correct operatio , e.g., to switch betwee the ADC i puts a d the S/PDIF i put
(both fu ctio s are i tegrated i to the codec), the codec must be reprogrammed. I additio ,
there are a umber of error status bits which are periodically sampled by the microco troller, the
codec ca be rebooted if problems are discovered.
5. The to e co trol pote tiometers are ot used o the Digital BUILT-INvisible® amplifier. The
bass a d treble are adjusted by mea s of pulse width modulatio as acheived with the I/O board
microco troller a d support circuitry. See the I/O board theory of operatio for a complete
descriptio . The DSP microco troller has several ADC i puts, two of which are used to detect
the voltage used to adjust the bass a d treble. Everytime this voltage cha ges it is prese ted to
the DSPs, which adjust their to e co trol filter coefficie ts accordi gly.

12
THEORY OF OPERATION
Digi al Signal Processor (DSP) PCB (con inued)
Microcon roller (con inued)
6. Other ADC ports are used for the followi g fu ctio s:
• To mo itor the gross DC offset o the five satellite speaker cha els. Excessive DC offset is
assumed to be a i dicatio of a serious problem a d the microco troller will respo d to this
by shutti g off the power to the amplifier.
• To detect the prese ce or abse ce of a digital S/PDIF sig al. The codec ca ot be set up for
a a alog i put a d a digital S/PDIF i put simulta eously a d it ca ot be reprogrammed
from a alog to digital (or vice versa) without i terrupti g the audio sig al.
• To seque ce the mute li e. As with the Series I, there are three so-called “speaker modes”,
2-cha el (bass, left, right); 3-cha el (bass, left, right a d ce ter) a d 5-cha el (bass, plus
all 5 satellites). U used output cha els are muted, ot o ly at the DSP but also at the power
amplifier. The mute i puts to the power amplifiers are 5V logic-level outputs from the
microco troller.
• The microco troller is i charge of booti g the DSPs at power-up i the followi g
seque ce:
- Boots the codec a d establishes the correct output sig als from the codec (bit_clock,
frame_clock, a d data).
- E ables the 3.3V power supply, a d verifies the correct voltage from it.
- Releases the DSP reset li e a d waits for the DSPs to boot a d ack owledge.
The microco troller is always e gaged i dialogue with both DSPs. If the DSPs should fail to
respo d withi a certai time-out, it is assumed that the DSPs have “crashed” a d the DSPs are
rebooted. The microco troller must pass some of the o volatile i formatio i the EEPROM
over to the DSPs at boot time, e.g.: speaker eq, system volume (all volume co trol i is do e i
the DSPs), ce ter a d surrou d volume a d bass a d treble pot positio . The microco troller
itself ca be reset i two ways, by a hardware reset sig al, which is ge erated by U200 whe
the 5V supply drops below 4.75V a d by the microco toller itself, o ce it has already booted
successfully (it ca pull its ow reset li e if the 8 MHz clock is ru i g).
Codec
The codec U100 [sheet 1, C4] is a highly i tegrated device which i cludes the followi g
fu ctio s:
•A I
2 C i terface for co trol a d status i formatio .
• Three cha els of 20-bit ACD; o ly two are used, o e for the left a alog i put a d o e for
the right. The ADCs will i put sig al levels i excess of 1 Vrms.
• Six cha els of output DAC; all six are used. Maximum output sig al level is 1 Vrms.
• A crystal oscillator which establishes the ADC/DAC sampli g rate, i this case, it is
11.2896 MHz / 256 = 44.1 kHz.
• A S/PDIF receiver. “S/PDIF” sta ds for So y/Philips Digital I terface Format. Esse tially, for
every pair of 20-bit audio samples, a other 24 bits of status, parity-checki g a d ge eral
housekeepi g bits are se t alo g for the ride. The data is e coded i such a way that:
a) there is o et DC co te t to the bit steam, allowi g tra sformer or AC coupli g a d
b) the bit clock ca be recovered from the bit steam.

13
THEORY OF OPERATION
Digi al Signal Processor (DSP) PCB (con inued)
Codec (con inued)
The codec ge erates three output sig als, either from the 11.2896 MHz crystal, or from the i put
S/PDIF bitstream;
• a serial bit stream co tai i g the 20-bit audio data.
• a bit_clock, which i dicates whe to sample the serial bit stream.
• a d a frame_clock, which i dicates the start of a audio sample.
I additio , there is a serial data i put (6 20-bit audio samples) to the codec, with timi g that
correspo ds exactly to the timi g of the serial data output. These four sig als (data out, data i ,
bit_clock, a d frame_clock) are used by the serial ports o the DSPs. The timi g of the data flow
i to a d out of the DSP subsystem is drive e tirely by the codec; the serial ports o the DSP
ru asy chro ously to the 40 MHz clock which drives the DSPs.
DSPs
The DSPs [DSP1, sheet 3 C/D7; DSP2, A/B7] are A alog Devices 21061L ge eral purpose
floati g poi t digital sig al processors, each capable of about 40 MIPs of performa ce.
Two are required to provide e ough MIPs for:
• AC-3 decodi g.
• Videostage®.
• bass ma ageme t.
• six cha els of speaker equalizatio .
• to e co trols.
The DSPs have o i ter al ROM; at boot time they load themselves from the exter al PROM
U401 [sheet 3, C2]. This boot process is more or less automatic; i.e., o i terve tio from the
microco troller is required (although the microco troller has co trol of the DSP reset li e).
The 21061L processors are desig ed to be bussed together, which accou ts for the relatively
large umber of pi s fou d o each DSP (240).
For i sta ce, the sig als required to co ect the DSPs to each other a d to the boot PROM
i clude:
• a exter al data address buss (32 bits, of which 24 are used).
• a exter al data buss (48 bits, of which 16 are used).
• buss co trol sig als (buss priority, address a d r/w strobes, etc).
Also, there are 30 power a d 30 grou d pi s o each DSP, a d a 40 MHz clock oscillator (U400,
crystal CR400, a d associated compo e ts) which drives both processors.

14
THEORY OF OPERATION
Digi al Signal Processor (DSP) PCB (con inued)
Signal Pa h
The sig al path through the system takes the followi g route(s):
For a alog sig als, the L/R stereo pair is i troduced from the source via the i put cable from the
I put/Output board a d the 14-pi co ector J9 [schematic sheet 1, A-D8]. Each sig al is
received pseudo-differe tially by op-amp U105 [B/C6] a d associated compo e ts a d -6 dB of
gai is applied to match with the maximum i /out sig al level of the codec (1Vrms).
Digital S/PDIF i put sig als e ter the DSP board at J9 pi 10 [B8] (which come directly from a
S/PDIF sig al source selected from o e of four possible i puts o the I/O board), the sig al is
routed directly to the codec U100 [C4] via a etwork of compo e ts (D1 [B5] a d surrou di g)
desig ed to clamp a d filter ESD tra sie ts.
The codec takes i either the pair of a alog i puts, or the si gle S/PDIF digital i put, a d outputs
three digital sig als (data, bit_clock, a d frame_clock, as described earlier). Si ce the codec
ru s o 5V a d the DSPs ru o 3.3V, a y sig als passi g betwee them must be level-shifted
via the buffers U101 [D5] a d U102 [D3].
Without goi g i to a lot of detail, DSP1 ha dles (mostly) Dolby® Digital (AC-3) decodi g a d
Videostage® 5 processi g a d DSP2 ha dles (mostly) equalizatio . With the sig al processi g
complete, DSP2 formats the six output cha els i to a si gle serial bitstream a d se ds this
back to the output side of the codec U100. The a alog buffers followi g the codec (U103, U104
a d associated compo e ts) do three thi gs:
• Remove the 2.3VDC refere ce voltage from the codec’s outputs. The codec is a
si gle supply (+5V) device a d refere ces a y of its i ter al a alog sig als to a
refere ce voltage at approximately 2.3V, about o e-half the +5V supply voltage.
• Refere ce the sig al to the amplifier grou d, ot the local grou d. The power amps are si gle
e ded a d are refere ced to their ow local grou d o the amp PCB, which is ot the same
as the local grou d at the codec o the DSP PCB. Amplifyi g the differe ces betwee the
two grou ds will produce audible hum i the output speakers.
• Provide e ough gai to i crease the output sig al for output to the amplifier board.
The sig als leave the codec itself at about 1Vrms full-scale, this is amplified up to about
6Vrms full-scale by the output buffers.
Power-Up Sequence
At power-up, all of the microco troller ports are i a high impeda ce state, which mea s that:
• The amplifier mute li es are held low, muti g the power amps.
• The 3.3V regulated supply is disabled, reduci g the dema d o the +20V supply u til
thi gs have stabilized.
• The DSP reset li e is held low, holdi g the DSPs i reset.

15
THEORY OF OPERATION
Digi al Signal Processor (DSP) PCB (con inued)
Power-Up Sequence (con inued)
The microco troller proceeds to:
• Set up its I/O ports.
• Pri t out a “reset” message o the TTY output.
• Program the codec a d verify that it respo ds.
• Retrieve system variables from o volatile memory a d pri t out the “power_cycle” a d
“eq” variables.
• Boot the DSPs, a d wait for them to respo d.
• Pass over system variables to the DSPs.
• Pri t out a y appropriate error messages.
• U mutes the power amplifiers, the u mutes the DSPs.
At this poi t, ormal sig al processi g comme ces. It should take o more tha 1.5 seco ds
from the time power is applied u til the time audio appears at the speaker outputs.
Power-Down Sequence
Upo receivi g the “off” comma d from the head-e d, the microco troller;
• Mutes the DSPs.
• Mutes the power amplifiers.
• Powers dow the codec a d the DSPs.
• Stores system variables i EEPROM.
A d the mo itors the voltage level at the tur -o i put. Whe it sees a low to high tra sitio , it
resets itself as if the power had just come o .
De ailed Theory of Opera ion (see schema ic diagram SD256431)
Digi al Signal Processor (DSP) Board, Shee 1 of 4
Sheet 1 of 4 shows the a alog i put buffers, codec’s power supply, a alog output buffers a d
some “glue logic” arou d the codec. The a alog i put buffers co sist of op-amp U105 [B/C6] a d
associated compo e ts. The ratio of R102 (a d R107) to R100 sets the gai ; -6 dB from J9 to
the i put of the codec. The dual-diodes D100 [D7], D102 [C7], a d D104 [B7] are there to clamp
ESD discharges i to J9. The filter capacitors C100 [D7], C105 [C7], etc., are prese t to filter off
RF picked up by the i put cable.
The output sig al from the buffer is grou d refere ced, but the codec’s a alog i puts are biased
at about 2.3V. C104 [C6] is required to AC-couple the sig al from the buffer i to the codec. R103
a d D103 are prese t to preve t tra sie ts from the op-amp (±12V rails) from overdrivi g a d
perhaps damagi g the codec (5V rail). R104 a d C102 [C6] are a EMI filter to preve t a y RF
leaki g from the codec from getti g outside the metal EMI shield. The codec is located u der the
shield, while the i put buffer is ot.

16
THEORY OF OPERATION
De ailed Theory of Opera ion (see schema ic diagram SD256431)
Digi al Signal Processor (DSP) Board, Shee 1 of 4 (con inued)
The S/PDIF i put e ters the DSP board at J9 pi 10 [B8] a d is routed to the codec by mea s of
C151, R1, R2, D1, C1, C7 a d R5 [B5]. C151 AC couples the digital S/PDIF sig al, a d R1
termi ates the i put with 75 Ohms. R2 a d D1 clamp the i put (a typical S/PDIF i put is about
500 mVpp i to a 75 Ohm load). C1 AC couples the sig al at D1 (which is grou d refere ced) to
the codec i put (which will be biased at about 2.3V whe the S/PDIF receiver is worki g). R5
a d C7 are a EMI filter desig ed to preve t RF from leaki g outside the shield.
The codec’s power supply co sists of U1 [A5] a d associated compo e ts. R10 a d R11 are
power resistors desig ed to drop the voltage at the voltage regulator’s i put, for reduci g the
power dissipatio of the voltage regulator itself.
D2, D3, a d R4 [A5/6] are used to draw a little curre t from the +12V regulated supply whe the
power supplies start to sag severely, as they will at low AC li e a d heavy amplifier load. The
+12V regulator is fed from the +40V u regulated supply a d has co siderably more headroom
tha the +5V regulator fed from the +20V supply. Also fed from the +20V supply is the 3.3V
switchi g regulator, which te ds to draw more curre t as its i put voltage drops (it delivers a
fixed amou t of power, at a fixed co versio efficie cy). So, as the +20V supply starts to sag,
the curre t load o it actually starts to i crease, which te ds to make it sag more.
The +5 volts supplied by the regulator is se t to two differe t compo e ts; the codec U100 [C4]
a d the microco troller U202 [sheet 2, C5] a d associated compo e ts. Si ce the regulator is
located outside the EMI shield a d the +5V supply li e might be carryi g EMI (Electro Mag etic
I terfere ce), ferrite beads L1 a d L2 [A4] were placed i series with each of the supply li es.
L1 a d R3 [A4] serve to isolate the two differe t power supply pi s o the codec (the “a alog”
+5VA from the “digital” +5VD). C5 a d C6 are bypass capacitors placed directly u der the
codec.
Codec glue logic
U101 [D5] is a 74LCX244, a 3.3V IC that ca tolerate 5 volts o its i puts. It’s used to co vert
5V to 3.3V logic sig als.
U102 [D3] is a 74ACT244, a 5V part that u dersta ds the logic levels used by the 3.3V IC. It’s
used to co vert the 3.3V logic sig als to 5V logic sig als.
U106 [A7] is a flip-flop, used to co vert a falli g edge (from the codec) to a arrow pulse (to the
DSP). This removes a pote tial timi g ambiguity.
R192 [D6] (a d others) is a 75 Ohm series resistor used to series-termi ate some of the high
speed logic sig als, to preserve edge fidelity at the receivi g e d.
R6 a d R7 [C3] comprise a low performa ce 5V to 3.3V shifter. Usi g such large series resis-
ta ces i the prese ce of eve moderate amou ts of stray a d i put gate capacita ce slows
dow the sig al’s edge, but this particular sig al is very low ba dwidth.

17
THEORY OF OPERATION
De ailed Theory of Opera ion (see schema ic diagram SD256431)
Digi al Signal Processor (DSP) Board, Shee 1 of 4 (con inued)
A alog output buffers co sists of U103, U104 [B-D2], a d associated compo e ts. Gai is set
by the ratio of R132 to R131 [D2]; to about 6x. Note that the ratio of R189 to R188 [D2] must
match. Gai of the output buffers = (codec_out - codec_refere ce) - amp_grou d_se se).
Shee 2 of 4 (microcon roller and associa ed componen s)
The bass a d treble co trol sig al e ters the DSP board at J9 pi s 1 a d 2 [D8]. This sig al is
ge erated o the I put/Output board a d co ected to a pair of microco troller ADC i puts at
U202 [C5] pi s 19 a d 20. All of these co ectio s are EMI filtered.
Thermistor R207 [C8] is mou ted o the topside of the DSP PCB. Whe the DSP PCB tempera-
ture rises to about 70 degrees C, the microco troller starts tur i g dow the output volume by
programmi g the codec, effectively co trolli g the maximum temperature i side the amplifier
e closure a d preve ti g damage.
R211 [D7] co ects the sig al “CMOUT” to o e of the microco troller’s ADC ports. CMOUT is
the codec’s 2.3V refere ce voltage. This voltage is mo itored as o e of the codec’s “vital sig s”,
if out-of-bou ds, the microco troller reboots the codec.
R208 [C8] co ects the 3.3V power supply to o e of the microco troller’s ADC ports. The
microco troller has the ability to tur the 3.3V regulator o a d off, thus havi g the ability to
check that the 3.3V supply is withi limits. The microco troller eeds to be able to tur the 3.3V
off at power dow to avoid drai i g the +20V supply faster tha the -20V supply. If the upper rails
sag faster tha the lower rails, the bass amp will u mute causi g a “thump” to be heard (about 5
seco ds after power dow ).
R44 throught R48 [I/O schematic sheet, E2] sum together all the satellite outputs a d feeds them
out through J4-5 [I/O sheet, E4] to DSP J9-5 [A7] to o e of the microco troller’s ADC ports at
U202 pi 25. The microco troller watches for grossly excessive DC offset at a y of the speaker
outputs. If DC is detected the microco troller will shut dow the AC power.
U201 [B6] is the o -volatile memory. Read/write access is via the 2-wire serial I2C buss.
U200 [D6] ge erates a 250msec reset pulse for the microco troller whe ever the +5V supply
drops below 4.75V.
D200 [A5] forms a simple level tra slator. The CLIP sig al is ge erated o the amp PCB whe -
ever o e of the satellite power amplifiers starts to clip. It’s a ope -collector output that pulls
dow to -12V. D200 level shifts this sig al from -12V through +12V, to 0V through 5V. This level-
shifted sig al goes to both the microco troller a d DSP2 (via a 5V to 3.3V buffer). As it tur s out,
the microco troller ig ores this sig al, but DSP2 tur s dow the system volume u til the CLIP
sig al disappears, the lets the volume drift back up to the origi al setpoi t.
Q204 a d Q201 [B3] form a simple S/PDIF detector. Q204 sets the bias for Q201 such that it is
just barely off. A S/PDIF sig al arrivi g at Q201 will cause C216 to be discharged, causi g the
voltage at C216 to drop from 5V to somethi g closer to grou d. This voltage is co ected to o e
of the microco troller’s ADC ports a d is sampled periodically by the microco troller.

18
De ailed Theory of Opera ion (see schema ic diagram SD256431)
Digi al Signal Processor (DSP) Board, Shee 2 of 4 (con inued)
Q200 [C2] allows the microco troller to pull dow o the DSP’s reset li e. Whe the
microco troller first boots, all of its output ports are set to a high impeda ce state. Q200 remai s
tur ed o by R252, which holds the DSPs i reset, u til the microco troller is ready to boot the
DSPs.
R246, R248, [C/D2] etc. co ect several of the microco troller output ports to the MUTE i puts
o the power amplifiers. The mute sig als are orga ized i to three groups; (bass, left, right),
(ce ter) a d (left_surrou d, right_surrou d), correspo di g to the three speaker modes the
product supports. Each li e is EMI filtered. Pulldow resistors R813, R814 a d R815 [amplifier
schematic sheet 2, [D5] guara tee that the sig als will assume a LOW state i.e., muted) at
power-up.
Shee 3 of 4 (DSPs)
There are o ly two DSPs, but si ce they each have 240 pi s, they’ve bee broke i to several
differe t schematic symbols so as ot to clutter the page:
- address a d data busses.
- buss co trol, a d miscella eous.
- li k ports (sheet 4).
- power a d grou d (sheet 4).
Without goi g i to a y detail, the DSPs are co ected to each other a d to the boot PROM
U401 [C2], as follows:
- address buss co ected to address buss.
- data buss co ected to data buss.
- buss co trol sig als co ected to buss co trol sig als.
- power pi s co ected to 3.3V power pla e.
- grou d pi s co ected to grou d pla e.
The large umber of i terco ects a d the fact that each sig al has extremely fast rise times
(2 sec), required the use of a four layer PCB. O e of the i er layers is a (more or less) solid
grou d pla e; the other is used for a power pla e, plus additio al sig al i terco ect where
required.
U400 [B2] a d associated compo e ts form a third-overto e 40 MHz oscillator. There are two
buffered outputs; o e drives both DSPs a d o e is co ected to the test co ector J401 [B1],
which was used to help debug the prototype PCBs but is o lo ger loaded.
Shee 4 of 4
U500 [C/D4] a d associated compo e ts form a 3.3V regulated supply. C500 a d L500 [C5] are
the regulator’s output filter. R500 a d C501 [D4] set the regulator’s switchi g freque cy (about
100 kHz). C503 [C4] is the “bootstrap” capacitor required for establishi g a i ter al bias voltage
higher tha the supply voltage (for tur i g o the i ter al N-cha el MOSFET switch). C515,
L501, a d C505 [C4] preve t switchi g harmo ics from leaki g back out o to the raw DC i put
voltage. R501, C507, C508 [C3], etc., are feedback a d compe satio compo e ts.
THEORY OF OPERATION

19
De ailed Theory of Opera ion (see schema ic diagram SD256431)
Digi al Signal Processor (DSP) Board, Shee 4 of 4 (con inued)
C506 [D3] is the “soft-start” capacitor, which forces the regulator to start up slowly whe power
is first applied, thus limiti g the i rush curre t. R510 a d Q500 [D3] allow the “soft-start” pi to be
pulled low, shutti g off the regulator. The 3.3V supply is tur ed off as part of the ormal power
dow seque ce.
De ailed Theory of Opera ion (see schema ic diagram SD256421)
Power Amplifier Board
No e: U less otherwise oted, refer to the schematic diagrams for the power amplifier board for
the followi g i formatio . The refere ces i brackets [ ] are the schematic sheet a d grid coordi-
ates for the compo e t.
Shee 1 of 2
The satellite cha el power amplifiers are a discrete high efficie cy Class-G desig . Maximum
power is 35 W per cha el i to 4 Ohms at less tha 0.1% THD. I Class-G operatio the amplifi-
ers are powered by two differe t power supplies depe di g o the amplitude of the sig al i put.
Whe the audio amplitude is low, the amplifiers ru off of the lower supply rails, but duri g musi-
cal peaks they switch to the higher supply rails. Efficie cy is typically i creased from 20% to
40% a d power dissipatio is reduced by a factor of 2.5.
Bass Channel Power Amplifier
Audio i put is applied to the amplifier PCB at pi 12 of co ector J700 [amplifier schematic sheet
2, D7] a d is AC coupled through C727 [D8]. The amplifier is co trolled by egative feedback to
op-amp U707 [C6], which is co figured as a i verti g amplifier with a voltage gai of 12 (21.6
dB). With o sig al applied to the i put, all output power devices are biased off. For a egative
i put sig al, pi 1 goes high a d co ducts driver tra sistor Q713 [D6]. Collector curre t is pulled
through R707 a d R774 [D6] u til the voltage drop across R774 reaches about 1 Volt, at which
time the high gai darli gto tra sistor Q718 [D6] begi s to co duct emitter curre t through
power diode D711 [D5/6], which co ects to the +20VDC supply.
Collector curre t from Q718 [D6] flows through the speaker load a d the voltage at this ode is
regulated by feedback to the op-amp via resistor R789 [D7].
Whe the audio output voltage approaches the 20VDC power supply rail, output tra sistor Q718
begi s to saturate a d co ducts much more base curre t tha the ormal maximum of 5mA. At
approximately 8mA the voltage drop across 75 Ohm resistor R707 [D6] exceeds 0.6V a d small
sig al tra sistor Q714 [D6] begi s to co duct. This i tur co ducts Class-G Darli gto tra sis-
tor Q715 [D6], which tur s o the 40VDC power supply a d reverse biases power diode D711
[D6], effectively tur i g off the 20VDC supply. Duri g this period, the waveform at the collector of
Q715 resembles the audio output sig al plus the saturatio drop of Q718 a d Q715 is operated
i the active regio ( ot as a switch), thus shari g the power dissipatio .
Crossover distortio a d switchi g tra sie ts are ot a issue due to the relatively low ba d-
width of the amplifier (less tha 250 Hz) a d the ability of the bass module to roll off high fre-
que cy distortio products. Crossover distortio is less tha 0.5% at 200 Hz, 1 Watt.
THEORY OF OPERATION

20
De ailed Theory of Opera ion (see schema ic diagram SD256421)
Power Amplifier Board, Bass Channel Power Amplifier (con inued)
Short circuit protectio is provided through curre t se se resistor R822. At greater tha 16A,
Q726 co ducts a d triggers the o e-shot op-amp circuit U707, pi s 5, 6 a d 7, a d mutes the
amp for several seco ds. The amp will cycle i a d out of mute u til the short circuit is removed.
Sa elli e Power Amplifiers
Each of the five satellite amplifiers are operated i Class-G co figuratio a d co sist of a 50W,
Class AB mo olithic i tegrated circuit (i a multiwatt-15 package, TDA7294). The amplifier is
short circuit a d thermally protected. Exter al to this IC is a pair of TO-220 Darli gto tra sistors
(the same as used i the discrete bass amplifier) to perform the Class-G power supply switch-
i g. The followi g detailed operatio is described for the left surrou d cha el, however the other
four cha els would be the same.
The surrou d sig al e ters the amplifier board at J700 pi 11 [sheet 2, D7] a d is applied to
capacitor C717 [C5] a d couples to the o -i verti g i put of the TDA7294 amplifier IC. It is
co figured as a o -i verti g amplifier with a voltage gai of 4 (12 dB). The output stage co -
sists of a pair of MOSFET tra sistors a d the positive FET must develop gate drive well above
the supply voltage a d he ce there is a bootstrap cap, C716 [C3], betwee pi 6 a d 14.
With low amplitude sig al, the amplifier ru s off of the 20VDC rails through power diodes D704
[D3] a d D710 [C3]. The power supply voltage at pi 13 is subtracted by 5.6V ze er diode D703
[D3] a d divided dow by the ratio of 1 + R731/R732 [D3/4]. This bias voltage sets the threshold
at which tra sistor Q703 [D4] tur s o . Whe the audio or the i put to the amplifier exceeds the
voltage at the emitter of Q703 by two diode drops, D716 [C4] a d Q703 co duct. I tur this
co ducts small sig al tra sistor Q704 [D4] which i tur co ducts output tra sistor Q705 [D3].
A egative feedback loop is established that preve ts Q705 from tur i g completely o a d the
voltage at the collector of Q705 resembles the audio output wave form plus several volts of
saturatio headroom. Q705 operati g i the active regio (i stead of as a o /off switch), results
i shared power dissipatio betwee the tra sistor a d the power amplifier IC. The phase lag
created by the i put etwork R753 a d C745 [C4] allows the power circuit to switch o slightly
ahead of the power amplifier at high freque cies (above 8 kHz) to mi imize tur -o glitch.
Power Amplifier Board, Shee 2 of 2
Power Supplies and Connec ors
AC power is se t to the amplifier board at J702 [A/B5] from the seco dary of the power tra s-
former [I/O schematic sheet, D1] located i the ce ter cutout of the I put/Output board. The raw
AC is recitified by bridge rectifiers B700 a d B701 [A/B4]. The filtered DC from B701 is passed
through fusible resistors R713 a d R714 [B3] a d output as +40V fused. These 40V rails are
used as the higher rail voltage for the Class G amplifier output devices as show o amplifier
schematic sheet 1. The +40Vdc fused outputs are also are regulated dow to +12Vdc by regula-
tors U708 a d U709 [B/C2]. This +12Vdc is fed to both the DSP board through J700 pi s 2 a d 6
a d to the I put/Output board at J701 pi s 13 a d 15 [A7]. The filtered DC from B700 provides
+20Vdc a d is used as the lower rail voltage for the amplifier Class G output devices.
THEORY OF OPERATION