Casio CTK-731 User manual

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BACK LIGHT LCD
INTRO
RECORD SONG PATTERN
DSP
CONTRAST
FREE SESSION
ONE TOUCH PRESET
TONE
RHYTHM
LAYER/AUTO HARMONIZE
SPLIT
MIN
MAX
FULL RANGE
CHORD
000-009
010-019
020-029
030-039
040-049
050-059
060-069
070-079
080-089
090-099
100-109
8 BEAT
0 REVERB 1 LAYER
AUTO
HARMONIZE
TOUCH
RESPONSE
SPLIT
GM
1 REVERB 2
2 REVERB 3
3 CHORUS
4 TREMOLO
5 PHASE SHIFTER
6 ORGAN SPEAKER
7 ENHANCER
8 FLANGER
9 EQ LOUDNESS
000-007 PIANO
008-015 CHROMATICPERC
016-023 ORGAN
024-031 GUITAR
032-039 BASS
040-047 STR/ORCHESTRA
048-055 ENSEMBLE
056-063 BRASS
064-071 REED
072-079 PIPE
080-087 SYNTH-LEAD
088-095 SYNTH-PAD
096-103 SYNTH-SFX
104-111 ETHNIC
112-119 PERCUSSIVE
120-127 SOUND EFFECTS
128-191 VARIATION TONE
192-199 DRUM SET
200-231 USER TONE
16 BEAT
ROCK
POPS I
POPS II
JAZZ
EUROPEAN
LATINI
LATINII/VARIOUS I
VARIOUS II
USER RHYTHM
FINGERED
CASIO CHORD
FILL-IN
NORMAL/
FILL-IN
VARIATION/ ENDING SYNCHRO/
MUSICAL INFOMATION SYSTEM
10 DSP
2HD/DD FLOPPY DISK DRIVE
2HD/2DD FLOPPY DISK DRIVE
BASS REFLEX SPEAKER SYSTEM
789
456
123
0
SYNTH
DELETE
/NO
TRANSPOSE/TUNE/MIDI
TOUCH RESPONSE
DISK
/YES
GENERAL
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EXTERNAL
INTERNAL
GM SOUND KEYBOARD
CTK-731
JULY.1999
CTK-731
Ver.3: Dec. 2007
INDEX

CONTENTS
Specifications ---------------------------------------------------------------------------------------------- 2
Block Diagram --------------------------------------------------------------------------------------------- 4
Circuit Description --------------------------------------------------------------------------------------- 5
Diagnostic Program------------------------------------------------------------------------------------ 20
Major Waveforms --------------------------------------------------------------------------------------- 26
Printed Circuit Board ---------------------------------------------------------------------------------- 27
Exploded View ------------------------------------------------------------------------------------------- 31
Parts List--------------------------------------------------------------------------------------------------- 32
Schematic Diagrams----------------------------------------------------------------------------------- 35

— 2 —
SPECIFICATIONS
GENERAL
Keyboard: 61 standard-size keys, 5 octaves (with touch response on/off; ExLight/
Light/Normal/Heavy touch)
Tones: 232 (128 General MIDI, 64 variation, 8 drum, 32 user); with layer and
split
Rhythm instrument tones: 53
Polyphony: 32 notes maximum (16 for certain tones)
Digital effects: 10 (REVERB 1, 2, 3; CHORUS; TREMOLO; PHASE SHIFTER; OR-
GAN SPEAKER; ENHANCER; FLANGER; EQ LOUDNESS)
Auto accompaniment
Rhythm patterns: 110 (100 + 10 user rhythms)
Tempo: Variable (226 steps, = 30 to 255)
Chords: 3 fingering methods (CASIO CHORD, FINGERED, FULL RANGE
CHORD)
Rhythm controller: Start/Stop, Intro, Normal/Normal Fill-In, Variation/Variation Fill-In,
Synchro/Ending
Accomp volume: 0 to 127 (128 steps)
One touch presets: Recalls settings for tone, tempo, layer, and Auto Harmonize in accor-
dance with rhythm.
Auto harmonize: Automatic addition of notes that harmonize with melody note in ac-
cordance with specified Auto Accompaniment chords.
Free session
Number of patterns: 100 (Auto Accompaniment function based on preset chord progres-
sions.)
Song sequencer
Songs: 2
Recording tracks: 6 (2 through 6 are melody tracks)
Recording method: Real-time
Memory capacity
(total for two songs): Approximately 4,900 notes
Punch in: Supported
Pattern sequencer
Number of patterns: 10 (Rhythm numbers 100 to 109)
Memory capacity: Approximately 7,000 notes
Elements: Intro, Normal, Variation, Normal Fill-In, Variation Fill-In, Ending
Parts: Chord 1, 2, 3; Bass; Rhythm
Recording method: Real-time
Registration memory
Number of setups: 20 (5 setups ×4 banks)
Memory contents: Tone, Rhythm, Tempo, Split on/off, Split point, Layer on/off,Auto Har-
monize on/off, Mixer settings, Keyboard channel on/off, DSP (digital
effect) on/off, DSP (digital effect) settings, Accompaniment mode,
Touch Response settings, Assignable jack setting, Transpose, Tun-
ing, Pitch Bend range, Sound range shift on/off
Demo tunes: 2
Synthesizer
Parameters: PCM set, amp envelope set, attack rate, release rate, pitch envelope
set, pitch, level, touch sensitivity, pan, filter sensitivity, filter level, trans-
pose
Mixer Channels: 16
Modes: Internal, External, External/Solo, External/Play
Parameters: Program change number, volume, expression, pan, coarse tuning,
fine tuning, Effect Send
MIDI: 16-channel multi-timbre receive, General MIDI Level 1

— 3 —
Other functions
Pitch bend range: Adjustable (12 semitones upwards and downwards)
Modulation: Equipped
Transpose: 25 steps (–12 semitones to +12 semitones)
Tuning: Adjustable (A4 = approximately 440Hz ±50 cents)
Terminals
MIDI terminal: IN, OUT
Sustain/Assignable jack: Standard jack (sustain, sostenuto, soft, rhythm start/stop)
Headphones/Output: Stereo standard jack
Output Impedance: 250 Ω
Output Voltage: 6 V (RMS) MAX
12 V DC
Floppy disk drive
Type: 3.5" FDD
Formats: 2DD (720KB MS-DOS format)
2HD (1.44MB MS-DOS format)
Functions: Save and load of user tones, user rhythms, sequencer, and registration
data; playback of SMF; disk formatting; file delete; accompaniment pat-
tern style conversion
Power supply: Dual power supply system
Batteries Six D-size batteries
Battery life Approximately 3 hours continuous operation on alkaline batteries
AC adapter: AD-12
Auto power off: Turns power off approximately six minutes after last key operation. En-
abled under battery power only, can be disabled manually.
Speaker output: 5 W + 5 W
Power consumption: 12 V 18 W
Dimensions: 96.0 ×37.5 ×14.8 cm (37 13/16 ×14 3/4 ×5 7/8 inch)
Weight (without batteries): Approximately 7.0 kg (15.5 lbs)
Standard accessories: Music Stand; Pattern Conversion Disk; Data Disk; Disk User’s Guide;
Keyboard User’s Guide, Rhythm Tone Plate
ELECTRICAL
Current drain with 12 V DC:
No sound output 400 mA ±20 %
Maximum volume 2330 mA ±20 %
with 10 keys from C1 to E2 pressed in whistle tone
Volume: MAX., Velocity: MAX.
DSP0: Reverb1, FDD: Replay
Phone output level (Vrms with 8 Ωload each channel):
with tone Synth-Bass 4 tone L-ch (Key C4) 77 mV ±20 %
Volume: MAX., Velocity: MAX. R-ch (Key F3) 75 mV ±20 %
DSP0: Reverb1
Speaker output level (Vrms with 8 Ωload each channel):
with tone Synth-Bass 4 tone L-ch (Key C2) 5.7 mV ±20 %
Volume: MAX., Velocity: MAX. R-ch (Key E1) 5.6 mV ±20 %
DSP0: Reverb1
Output level (Vrms with 47 kΩload each channel):
with tone Synth-Bass 4 tone L-ch (Key D3) 2400 mV ±20 %
Volume: MAX., Velocity: MAX. R-ch (Key F3) 2150 mV ±20 %
DSP0: Reverb1

— 4 —
BLOCK DIAGRAM
Back Light Driver
T501
Q501, Q502
ROM2
MX23C3210MC-12CA89
LSI3 (32Mbit)
ROM1
MX23C8100MC-12CA99
LSI2 (8Mbit)
RAM2
TC551001BFL-70L
LSI8 (1Mbit)
VBR VBR
VBR
AVDDDVDDFVDDCVDDVCCVDDVC
VDD
APO
NMI
SWCK
LSDT
S1
IC1
LWR, RD S1 HWR, RD HWR
RD
RD, HWR, LWR
RD, HWR, LWR
1RD, 1HWR, 1LWR
TEND, DREQ, CS2, CS3, B1-5
A0 ~ A15
KI0 ~ KI7
KC0 ~ KC8
SEG1 ~ SEG40
OUT
MIDI
IN
COM1 ~ COM16
LEDA ~ LEDF
LEDCK, LEDCL
D0 ~ D15
D0
D7
~
D8
D15
~
D8
D15
~
Chip Selector
TC74VHCO8F
IC4
S-Register
TC74HC164
IC302
S-Register
TC74HC164
IC301
LCD
FDD Controller
HD63266F
LSI6
3.5" FDD Unit
DF354H064A
Back up
Power
CR2032
Power Supply Circuit
IC204, Q203
Q204, Q208, Q210
Q205,
Q206
CPU
HD6433042SB51F
LSI9
Working
RAM
TC55257
DFL-70L
LSI5
(256Kbit)
LPF
(L) LPF (R)
D8 ~ D15 RESET
RESET
RD,
HWR
ECEB, EOEB
EWEB
RESB
RESB
PBO
LCD Driver
SED1278F2A
LSI501
DB4
~DB7
CONT,
LRS,
LR/W
LE
Keyboard
SI0 ~
SI7
FI0 ~
FI7
KC0
~
KC7
WOK1
SOLP
BOK RAM1
TC551001BFL-70L
LSI7 (1Mbit)
Key Controller
TC190C020AF-001
LSI10
Reset IC
RN5VD40AA
IC3
Out put
(L) (R)
Speakers
LEDs
VDD
Buttons
A1 ~ A4
D0 ~ D15
RA0 ~ RA20
ED0 ~ ED8
EA0 ~ EA14
RD0 ~ RD15
Main
Volume
D/A Converter
µPD6376GS
LSI1
Power Amp.
LA4620
IC201
DSP
HG51B155FD
LSI4
A0 ~ A3
Back Light

— 5 —
KC0 KC1 KC2 KC3 KC4 KC5 KC6 KC7
FI0 C2 1C#2 1D2 1D#2 1E2 1F2 1F#2 1G2 1
SI0 C2 2C#2 2D2 2D#2 2E2 2F2 2F#2 2G2 2
FI1 G#2 1A2 1A#2 1B2 1C3 1C#3 1D3 1D#3 1
SI1 G#2 2A2 2A#2 2B2 2C3 2C#3 2D3 2D#3 2
FI2 E3 1F3 1F#3 1G3 1G#3 1A3 1A#3 1B3 1
SI2 E3 2F3 2F#3 2G3 2G#3 2A3 2A#3 2B3 2
FI3 C4 1C#4 1D4 1D#4 1E4 1F4 1F#4 1G4 1
SI3 C4 2C#4 2D4 2D#4 2E4 2F4 2F#4 2G4 2
FI4 G#4 1A4 1A#4 1B4 1C5 1C#5 1D5 1D#5 1
SI4 G#4 2A4 2A#4 2B4 2C5 2C#5 2D5 2D#5 2
FI5 E5 1F5 1F#5 1G5 1G#5 1A5 1A#5 1B5 1
SI5 E5 2F5 2F#5 2G5 2G#5 2A5 2A#5 2B5 2
FI6 C6 1C#6 1D6 1D#6 1E6 1F6 1F#6 1G6 1
SI6 C6 2C#6 2D6 2D#6 2E6 2F6 2F#6 2G6 2
FI7 G#6 1A6 1A#6 1B6 1C7 1
SI7 G#6 2A6 2A#6 2B6 2C7 2
CIRCUIT DESCRIPTION
KEY MATRIX
Note: Each key has two contacts, the first conatct 1and second contact 2.
Key
Second contact 2 First contact 1 FI
KC
SI
NOMENCLATURE OF KEYS
F#3 G#3 A#3 C#4 D#4 F#4 G#4 A#4 C#5 D#5 F#5 G#5 A#5
F3 G3 A3 B3 C4 D4 E4 F4 G4 A4 B4 C5 D5 E5 F5 G5 A5 B5 C6
D#3
C2 D2 E2 F2 G2 A2 B2 C3 D3 E3 B6A6G6F6E6D6 C7
C#3A#2G#2
F#2D#2
C#2 A#6 G#6F#6D#6
C#6

— 6 —
KI0 KI1 KI2 KI3 KI4 KI5 KI6 KI7
KC0 MODE INTRO A SPLIT
KC1 RECORD B ▲2
KC2 SONG C RHYTHM 5
KC3 PATTERN D ENTER TONE 8
KC4 DSP E DISK 0
KC5 STORE 1 3
KC6 46
KC7 BANK ▼SYNTH 7 9
BUTTON MATRIX
LED-B
FINGERD
LED-A
FULL RANGE
CHORD
LED MATRIX
LED-C
CASIO CHORD
LED-E
DEMO
LED-D
FREE
SESSION
LED-F
DISK
CON-
TRAST
FREE
SESSION
ONE TOUCH
PRESET
NORMAL/
FILL-IN
VARIATION/
FILL-IN
SYNCHRO/
ENDING
START/
STOP
TEMPO
▼
TEMPO
▲
TR6
CH16
TOUCH
RESPONSE
TRANS-
POSE
LAYER/
AUTO HARMO
▼/NO
—
▲/YES
+
DMSW DEMO
▲
▲
MIXER
SELECT
UPPER1
CH1
LOWER1
CH3
UPPER2
CH2
LOWER2
CH4
ACC VOL.
CH5
CHORD1
CH6
CHORD2
CH7
CHORD3
CH8
BASS
CH9
TR1
CH11
RHYTHM
CH10
TR2
CH12
TR3
CH13
TR4
CH14
TR5
CH15

— 7 —
MEMORY DEVICES
Each memory device has the following data.
1RAM1 :
S-RAM for operation program, Register, Pattern, Song
and SMF data from FDD. (Lower part of data bus)
2RAM2 :
S-RAM for operation program, Register, Pattern, Song
and SMF data from FDD. (Upper part of data bus)
3Internal ROM of CPU :
Main program data for system operation
4Internal RAM of CPU :
Work area for system operation
5ROM1 :
Demo,Accompaniment data, Song, Pattern, Synth, Disk
mode
6ROM2 :
Sound Waveforms/Tone data Digital sound effect
7Working RAM :
Work area for DSP
CPU
RAM1
1
1 Mbit
LSI7
ROM
RAM
3
4
512 kbit
16 kbit
DSP
LSI9
LSI4
Working RAM
7
256 kbit
LSI5
Internal Memory
ROM1
5
8 Mbit
LSI2
RAM2
2
1 Mbit
LSI8
ROM2
6
32 Mbit
LSI3
VDD Battery set
RESET
CPU
HD6433042SB51F
LSI9
FDD Controller
HD63266F
LSI6
RESET
Power Supply
Circuit
DSP
HG51B155FD
LSI4
RESB
RESB
Key Controller
TC190C020AF-001
LSI10
DVDD
DVDD
DVDD
VDD
DVDD
RESET
APO
PWSW
From power switch
RES
NMI
PB0
PA7
RESET
PW/SW ON
APO
DVDD
(5V)
Initial reset
When batteries are set or an AC adapter is connected, the reset IC provides a low pulse to the CPU.
When the power switch is pressed, the CPU receives a low pulse of POWER signal. The CPU first raises
APO signal to +5 V to generate DVDD voltage, then raises RESET signal to +5 V. During this period the
DSP, the key controller and FDD controller LSIs initialize their internal circuits.
RESET CIRCUIT

— 8 —
POWER SUPPLY CIRCUIT
The power supply circuit provides various voltages as shown below.
The voltage VDD (+5 V) is provided as long as batteries or AC adaptor is set.
Other voltages are controlled by APO (Auto Power Off) signal from CPU.
The regulator IC BA9700A generates square waveform from pin 5 as PWM (Pulse Wide Modulation).
The LC filter makes stable output voltage (+5 V) for each circuit as shown above.
LC Filter
Switching
Transistors
Regulator IC
From
Batteries or
AC Adaptor (To back light)
(To LCD)
(To FDD)
(To digital)
(To analog)
+9V ~ +12 V
LC Filter
CPU
HD6433042SB51F
LSI9
PA7
NMI
PW/SW
APO
NMI
PW/ON
APO

— 9 —
DSP and DAC CIRCUIT
The DSP (Digital Signal Processor) and DAC (Digital Analog Converter) consists of the following circuits.
RA22
Working RAM (256K-bit)
TC55257DFL-70L
LSI5
ROM2
MX23C3210MC-12CA89
LSI3 (32Mbit)
ROM1
MX23C8100MC-12CA99-465
LSI2 (8Mbit)
SOLP
BOK
WOK1
EA0 ~
EA14
D0 ~
D15
ED0 ~
ED15
KC0 ~
KC7
SI0 ~ SI7
FI0 ~ FI7
RA0 ~
RA18
RA0 ~ RA20
CS
RA23
CE A0 ~ A18 Q0 ~ Q15 CE A0 ~ A20 Q0 ~ Q15
WE
OE
D0 ~ D15 A0 ~ A14
PG
24.576 MHz
DAC
UPD6376GS
LOUT
ROUT
SOLP: Sound data
BOK: Bit clock
WOK1: Word clock
SI
CLK
LRCK
DSP
HG51B155FD
LSI4
CPU
HD6433042SB51F
LSI9
Key Controller
TC190C020AF-001
LSI10
RD0 ~ RD15
RA0 ~
RA20
D8 ~
D15 Control
data
key
data
key
data
Key-
board

— 10 —
FDD UNIT (DF354H064A)
FDD Specifications:
1Memory Capacity (under un-format) : 1.6 MByte
2Density of track : 5.33 track/mm (135 TPI)
3Number of track : 77 track/side
4Number of head : 2
5Rate of data transfer : 500 kbps
6Access time (between two tracks) : 3 m seconds
7Compensation of writing data : 125 n second (all tracks)
8Rotation speed : 360 Min-1 (rpm) ±1.5 %
FDD Interface:
Host system Drive
CN2 connector
Index8 Density Select4
Drive Select 1 12
Motor ON 16
Direction 18
Step 20
Write Data 22
Write Gate 24 Track 0026 Write Protect28 Read Data30
Side 1 Select 32 Disk Change34
+5 V
DC.GND
System Frame GND.
Drive Frame GND.
0 Ω
1+5 V Return2+5 V Return3
N.C 4
CN1 connector
Signal GND
GND Pin Numbers of CN2:
1, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31, 33
Non connected Pin Numbers of CN2:
2, 6, 10, 14 (Pin #3 is removed to prevent erroneous insertion)

— 11 —
LCD BACKLIGHT
When voltage CVDD is supplied, transistors Q501 and Q502 start oscillation.
From the oscillation voltage, transformer T501 generates about 600 V which is necessary for lighting the
backlight.
10 1
11
C502
(Bottom View)
NT-07
T501
CFL1
L501
LHL08TB101K
1
1
12
DG
CVDD
C104FA
C104M
2SD965R 2SD965R
C501
R501
4.7K
Q501
CP14
Q502
C516
1
12
23 32
2
HMBV26BG1W63N/AZG
DE0405-979SL180J2K
2
12
2
3
4
5
8
9
7
5

— 12 —
Pin No. Terminal In/Out Function
1 VCC In VCC (5 V) source.
2 ~ 5 PB0 ~ PB3 Out Data bus for LCD driver.
6 PB4 Out Chip enable signal for LCD driver.
7 PB5 Out Read/write signal for LCD driver.
8 DREQ0 — DMA(Direct Memory Access) request.
9 PB7 Out Register selection signal for LCD driver.
10 RES0 In Not used.
11 VSS In Ground terminal (0 V).
12 TXD0 Out MIDI signal output.
13, 15 ~ 17 P91, P93~P95 In Key input signal from buttons.
14 RXD0 In MIDI signal input.
18 ~ 21 D0 ~ D15 In/Out Data bus.
23 ~ 34
22 VSS In Ground terminal (0 V).
35 VCC In Vcc (5 V) source.
36 ~ 43, A0 ~ A19 Out Address bus.
45 ~ 56
44, 57 VSS In Ground terminal (0 V).
55, 59, 60 P52, P61, P62 In Key input signal from buttons.
58 WAIT — Not used.
61 CLKOUT Out Clock signal (16 MHz).
62 STBY — Not used.
63 RES In Reset signal at VDD (5 V) supplied.
64 NMI In Power ON signal input.
65 VSS In Ground terminal (0 V).
66, 67 EXTAL, XTAL In Clock (16 MHz) input.
68 VCC In Vcc (5 V) source.
69 AS — Not used.
70 RD Out Read signal.
71 HWR Out Write signal for upper data bus.
72 LWR Out Write signal for lower data bus.
73 ~ 75 MD0 ~ MD2 In Mode selection terminals.
76, 77 AVCC, VREF In Power source and reference voltage for internal A/D, D/A.
78 AN0 In Battery voltage detection (Not used).
79 AN1 In Pitch bender voltage detection.
CPU (LSI9: HD6433042SB51F)
The 16 bit CPU contains a 512K-bit ROM, a 16K-bit RAM, eleven 8-bit I/O ports, anA/D converter and serial
interfaces. The CPU accesses to the RAM1, RAM2, DSP, Key controller, FDD controller and LCD driver
LSI. The CPU also controls buttons, LEDs, bender input and MIDI input/output.

— 13 —
Pin No. Terminal In/Out Function
80 P72 In AC adaptor detection terminal.
81 P73 In Modulation signal input.
82 P74 In Pedal signal input.
83 P75 In FD sheet type (2HD, 2DD) signal input.
84 P76 In Key input signal from buttons.
85 DA1 Out LCD contrast control voltage output.
86 AVSS In Ground terminal (0 V).
87 PB0 Out Reset signal for DSP, Key controller, FDD controller.
88 CS3 Out Chip select signal for FDD.
89 CS2 Out Acknowledge signal FDD DMA function.
90 CS1 Out Chip select signal for Key controller.
91 CS0 Out Chip select signal for DSP.
92 VSS In Ground terminal (0 V).
93 TEND0 Out End signal for data transfer of FDD.
94 PA1 Out Change signal for data transfer speed of FDD.
95 PA2 Out Key input signal for DEMO button.
96 PA3 Out Clock signal for shift register of KC signal.
97 PA4 Out Clear signal for shift register of LED.
98 PA5 Out Control signal for KC signal and LED.
99 PA6 Out Clock signal for shift register of LED.
100 PA7 Out APO (Auto Power Off) signal.

— 14 —
DIGITAL SIGNAL PROCESSOR (LSI4:HG51B155FD)
Upon receipt of note numbers and their velocities, the DSP (Digital Signal Processor) reads sound and
velocity data from the sound source ROM in accordance with the selected tone; the DSP can read rhythm
data simultaneously when a rythm pattern is selected. Then it provides 16-bit serial signals containing data
of the melody, chord, bass, and percussion to the DAC. The DSP also adds the selected effect to the sound
data using a 256k-bit RAM.
The following table shows the pin functions of the DSP.
Pin No. Terminal In/Out Function
1 ~ 8 CD0 ~ CD7 In/Out Data bus
9, 10 Not used.
11 GND7 In Ground (0 V) source
12 CK16 Out 24.576 MHz clock output
13 VCC6 In +5 V source
14 CK0 In Clock input. Connected to terminal CK16.
15 TCKB Not used.
16 VCC1 In +5 V source
17 GND1 In Ground (0 V) source
18, 19 XT0, XT1 In/Out 24.576 MHz clock input/output. Connected to a crystal oscillator.
20 SGL In System control terminal. Single chip system: Open
21 CCSB In Chip select signal input
22 ~ 25 CA0 ~ CA3 In Address bus
26 CE0 In Not used. Connected to ground.
27 CWRB In Write enable signal
28 CRDB In Read enable signal
29 ~ 32 Not used.
33 RESB In Reset signal input
34 TESB In Not used. Connected to +5 V
35 ~ 39 Not used.
40 ~ 49 RD0 ~ RD15 In Data bus for the ROM1 and ROM2
52 ~ 57
58 RA23 Out Chip select signal for the ROM1
59 RA22 Out Chip select signal for the ROM2
60 RA21 Out Not used.
61 ~ 73 RA0 ~ RA20 Out Address bus for the ROM1 and ROM2
75 ~ 82
74 GND5 In Ground (0 V) source
83 WOK2 Out Word clock output. Not used.
84 VCC3 In +5 V source
85 GND3 In Ground (0 V) source
86 WOK1 Out Word clock for the DAC
87 SOLM Out Serial data output. Not used.
88 SOLP Out Serial data output for the DAC
89 BOK Out Bit clock output for the DAC

— 15 —
FDD CONTROLLER (LSI6:HD63266F)
The FDD (Floppy Disk Drive) controller can control the FDD unit.
The controller contains not only analog VFO (Variable Frequency Oscillator) circuit but also driver/receiver,
input/output port and oscillation circuit internally.
Pin No. Terminal In/Out Function
1 8/ - 5 In Change of data transfer speed.
2 XTALSEL — Not used. Connected to ground (0 V).
3 RESET In Reset signal input.
4 E, -RD In Read signal.
5 R/-W, -WR In Write signal.
6 CS In Chip select signal.
7 DACK In Acknowledge signal of DMA (Direct Memory Access).
8, 9 RS0, RS1 In Register selection for read/write.
10, 11 VSS1, VSS2 In Ground terminal (0 V).
12 ~ 19 D0 ~ D7 In/Out Data bus.
20 DREQ In Request signalof DMA.
21 IRQ — Not used.
22 DEND In End signal for data transfer.
23 VSS3 In Ground terminal (0 V).
24 1/2 EX1 — Not used.
25 VCC1 In DVDD (5 V) source.
26, 27, 28 NUM1, NUM2 —Not used. Connected to ground (0 V).
IFS
29 SFORM In Selection signal for formatting.
Pin No. Terminal In/Out Function
90 ~ 92 Not used.
93 VCC5 In +5 V source
94, 95
97 ~ 105 EA0 ~ EA14 Out Address bus for the working RAM
107, 109
110, 112
96 EWEB Out Write enable signal output for the working RAM
106 EOEB Out Read enable signal output for the working RAM
108 VCC7 In +5 V source
111 ECEB Out Chip select signal output for the working RAM
113 ~ 117 Not used.
118 VCC4 In +5 V source
119 GND4 In Ground (0 V) source
120 ~ 122 Not used.
123 ~ 130 ED0 ~ ED7 In/Out Data bus for the working RAM
131 GND6 In Ground (0 V) source
132 ~ 134 Not used. Connected to ground.
135, 136 Not used.

— 16 —
Pin No. Terminal In/Out Function
30 INP In Disk detection signal.
31 READY In Ready signal from FDD. (Connected to ground (0V).)
32 WPRT In Write protect signal from FDD.
33 TRKO In Track0 signal from FDD.
34 INDEX In Index signal from FDD.
35 RDATA In Read data signal from FDD.
36, 37, 38 XTAL2, EXTAL2
—Not used.
39 NC, XTAL1
40 EXTAL1 In Clock signal input from CPU (16 MHz).
41, 42 VSS4, VSS5 In Ground terminal (0 V).
43 NC — Not used.
44 ~ 46 VCC2, VCC3, In DVDD (5 V) source.
VCC4
47 WGATE Out Write gate signal to FDD.
48 WDATA Out Write data signal to FDD.
49 VSS6 In Ground terminal (0 V).
50 STEP Out Step signal for FDD head.
51 HDIR Out Head direction signal for FDD.
52 HLOAD Out Not used.
53 HSEL Out Head selection signal for FDD.
54 VSS7 In Ground terminal (0 V).
55 DS0 Out Drive selection signal.
56, 57, 58 DS1, DS2, DS3 — Not used.
59 VSS8 In Ground terminal (0 V).
60 MON0 Out Motor ON signal for FDD.
61, 62, 63
MON1, MON2,
—Not used.
MON3
64 VSS9 In Ground terminal (0 V).

— 17 —
KEY TOUCH LSI (LSI10: TC190C020AF-001)
By counting the time between first-key input signal FI and second-key SI from the keyboard unit, the key
touch LSI detects key velocity of 256-step. Then the LSI sends the CPU the note number and its velocity
data.
Pin No. Terminal In/Out Function
1 WRB In Write signal from CPU.
2 ~ 11, 13, D0 ~ D15 In/Out Data bus.
14, 16 ~ 19
12 VSS In Ground terminal (0 V).
15 VDD In VDD (5 V) source.
20 ~ 23 CA0 ~ CA3 In Address bus.
24 VSS In Ground terminal (0 V).
25 ~ 32, FI0 ~ FI4, In Key input signal.
34, 35 SI0 ~ SI4
33 VDD In VDD (5 V) source.
36 ~ 38, KC0 ~ KC7 Out Key scan signal.
40 ~ 44
39 VSS In Ground terminal (0 V).
45 VDD In VDD (5 V) source.
46 ~ 51 FI5 ~ FI7 In Key input signal.
SI5 ~ SI7
52 VSS In Ground terminal (0 V).
53 ~ 58, FI8 ~ FI10
60 ~ 62 SI8 ~ SI10 In Key input signal (Not used).
KI0 ~ KI2
59 VDD In VDD (5 V) source.
63, 64 MODE0, MODE1 — Not used.
65 VSS In Ground terminal (0 V).
66 KCKI In Clock signal for key common/input.
67 ~ 72, — Not used.
74 ~ 77
73 VDD In VDD (5 V) source.
78 RESB In Reset signal from CPU.
79 CSB In Chip selection signal.
80 RDB In Read signal from CPU.

— 18 —
LCD DRIVER (LSI501: SED1278F2A)
The LCD driver can drive a dot matrix LCD having 40 segment and 16 common lines. The LSI contains 240
graphic symbols in the built-in character generator ROM, and stores 80 characters in the built-in display
data RAM. In accordance with command from the CPU, the LSI is capable of displaying up to 16 characters
simultaneously. The following table shows the pin functions of LSI 501.
Pin No. Terminal In/Out Function
1 ~ 22,
SEG1 ~ SEG40 Out Segment signal output
63 ~ 80
23 VSS — GND (0 V) source
24, 25 OSC1, OSC2 In/Out Terminals for the built-in clock pulse generator. The external re-
sistor connected determines the oscillation frequency.
LCD drive voltage input.
26 ~ 30 V1 ~ V5 In Those voltages are used for generating the stepped pulse of the
LCD drive signals.
31, 32 LP, XSCL — Not used
33 VDD In LVDD (+5 V) source
34, 35 FR, DO — Not used
36 RS In Data/command determination terminal.High: data, Low: command
37 R/W In Read/write terminal. High: read, Low: write
Chip enable signal.
38 E In High: enable, the writing is done at fall edge.
Low: disenable
39 ~ 42 DB0 ~ DB3 — Not used. Connected to GND (0 V)
43 ~ 46 DB4 ~ DB7 In/Out Data bus
47 ~ 62 COM1 ~ COM16 Out Common signal/output
REGULATOR IC (IC204: BA9700A)
The regulator IC controls the output voltage by PWM (Pulse Wide Modulation) with outer switching transis-
tors and LC filters (integration circuit).
14
1
13
2
12
3
11
4
10
5
9
6
8
NON
INVERT
INP 1/2Vret INVERT
INP Vret POWER SW NC VCC
7
D-TIME
CONT
Error
Amp
Vret
30k
RT CT FEED
BACK OUT NC GND
Triangle
Oscillator
PWM
Comparator
Voltage
Regulator
+–
30k

— 19 —
DAC (LSI1: UPD6376GS)
UPD6376GS is a two-channel 16-bit Digital to Analog Convertor consisting of resistor string, output ampli-
fier and zero offset circuit.
The DAC receives 16-bit serial data output from the DSP. The data contains digital sound data of the
melody, chord, bass, and percussion for the right and left channels. The DAC converts the data into analog
waveforms by each channel and output them separately.
POWER AMPLIFIER (IC301: LA4620)
The power amplifier is a two-channel amplifier with standby switch.
6
16 2 10 11 13
12
Pre-drive
Amp.
Input
Amp. Power Amp.
+
–
Pre-drive
Amp.
Input
Amp. Power Amp.
+
–
9
7
3
5
+
–Input
Amp. Pre-drive Amp. Power Amp.
+
–Input
Amp. Pre-drive Amp. Power Amp.
4
19
20
21
22
23
1
18
17
15
14
8
RL Short
Protector
RL Short
Protector
Terminal
Protection
Circuit
Pop Noise
Prevention
Circuit
Ripple
Filter
IN11+
IN11–
IN12–
IN21+
IN21–
IN22–
NC DC MUTE ADJ
Boot11
OUT11
PoGND1
OUT12
Boot12
VCC1
Boot21
OUT21
PoGND2
OUT22
Boot22
VCC2
PriGND
Pin No. Terminal In/Out Function
1 SEL In Mode selection terminal. Connected to ground.
2 D.GND In Ground (0 V) source for internal digital circuit
3 NC Not used.
4 DVDD In +5 V source for internal digital circuit
5 A.GND In Ground (0 V) source for internal analog circuit
6 R.OUT Out Sound waveform output
7 A.VDD In +5 V source for internal analog circuit
8 A.VDD In +5 V source for internal analog circuit
9 R.REF In Reference voltage terminal. Connected to a capacitor.
10 L.REF In Reference voltage terminal. Connected to a capacitor.
11 L.OUT Out Left channel sound waveform output
12 A.GND In Ground (0 V) source for internal analog circuit
13 LRCK In Word clock (L/R separation signal) input.
14 LRSEL In Not used. Connected to ground.
15 SI In Sound data input
16 CLK In Bit clock input