Cirrus Logic CobraNet EV-2 User manual

Copyright 2004 Cirrus Logic, Inc. August 2004
EV-2MAN20
http://www.cirrus.com
Preliminary Product Information This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
CobraNetTM EV-2
Digital Audio Networking Processor
CobraNet
EV-2 Development System Manual
TM

Page 1
CobraNetTM EV-2
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Required Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Included: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Not Supplied: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Setup Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Switch and Connector Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
J300 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
J401 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
J700 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
P450 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
P501 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
P504 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SW200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SW201-SW204 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SW500 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Detailed Description of EV-2 Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
The Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Microcontroller Memory Space: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Microcontroller Port Connections: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Interfacing the Microcontroller to the CM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Programming the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Interfacing Serial Audio to the CM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Configuring the FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Functional Discussion of FPGA Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Hex Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
EV-2 Schematics, Page-by-Page Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Microcontroller and Hex Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
D/A Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Connectors and Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Optional VCXO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
AES/EBU Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Power Supply Conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Appendix A: Definition of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Appendix B: EV-2 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Appendix C: Other Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Appendix D: EV-2 Schematic Drawings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Appendix E: EV-2 Command Line Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Appendix F: CD-ROM Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Page 2 Rev. 2.0
CobraNetTM EV-2
Introduction
The EV-2 provides a means of evaluating the CM-1 or CM-2 CobraNettm Modules and the Cirrus Logic
CS181xx family of CobraNet chips. In addition to evaluating the CM-1 or CM-2 ( hereafter collectivelly
referred to as the CM except where differences between the CM-1 and CM-2 exist ), the user may also use
the EV-2 as a development platform and as an example interface for CMs, the CS181xx, and other
CobraNet related projects. The EV-2 connects to the CM via the module's host interface. An 8051 type
microcontroller interfaces to the CM's host port, and a simple audio router on the EV-2 allows multiple
audio inputs and outputs to connect to the CM's serial audio interface. The included software provides a
simple interface for audio routing on the EV-2, as well as development support.
Features:
• Analog audio I/O: Two channels of analog audio input converted to high quality, 24-bit, 48 kHz
digital audio. Two channels of 24-bit, 48 kHz digital audio converted to high quality, analog audio
output. Refer to Appendix B for audio I/O specifications.
• Digital audio I/O: One stream of AES/EBU input and one stream of AES/EBU output. An
AES/EBU stream is two channels of digital audio. The AES/EBU input stream is sample rate con-
verted.
• 8051-type microcontroller: 64kB on-chip Flash Program Memory, 1kB internal SRAM, 32kB
external SRAM and in-system programmability.
• Field programmability: The supplied EV-2 software provides a means to reprogram EV-2 micro-
controller firmware for field upgrades or user development.
• RS232 Interfaces: Two RS232 interfaces, one direct to the CM and another to the microcontroller.
• Routing flexibility: Route from any audio source to any audio sink using the supplied EV-2 soft-
ware. Route to and from the CM as well as within the EV-2.
Figure 1. EV-2 Block Diagram
A
nalog
Input
A
nalog
Output
C
M
M
O
D
U
L
E
I
N
T
E
R
F
A
C
E
VCXO
A
DC
DAC
A
ES
LEDs
SRAM
Hex
Switches
RS232
Interfaces
FPGA
8051
Output
Input

CobraNetTM EV-2
Page 3
• Sine wave generation: A sine wave test tone may be used as an alternate audio source. Minimal
frequency and gain control is provided.
• Hex switches: Four hex formatted switches may be used for network identification of the Cobra-
Net module and/or user development.
• Command line interface: The 8051, via its RS232 serial interface, can be used to configure the CM
using a command line interface.Cobranet MI variables can be viewed and modified using this
interface. Refer to Appendix E for a description of the Command line interface.
• LED display: Three LED indicators are provided and may be used for user development.
• Power supply: Uses standard computer ATX power supply (not included).

Page 4 Rev. 2.0
CobraNetTM EV-2
Getting Started
Required Materials
Included:
The CobraNet EV-2 Development Package ships with the following materials:
• EV-2 module w/ CM CobraNet PCB Qty. (2)
• 3’ CAT5 crossover cable Qty. (1)
• 6 - Pin Phoenix-style audio connectors Qty. (6)
• CD-ROM containing documentation, CobraNet Discovery utility and other support software
(see Appendex F for details)
Qty. (1)
Not Supplied:
• Two (2) ATX computer power supplies with cables are required, one for each EV-2 module. These
devices are commonly available at computer retail stores.
• Audio cables.
• RS232 cables. (Not required to pass audio)
Figure 2. EV-2 Module w/CM PCB
Evaluation Board EV-2
Module CM

CobraNetTM EV-2
Page 5
Setup Procedure
• Using the supplied Phoenix connectors, build audio input and output cables and two AES/EBU
cables (if desired). These will be used to connect your audio input and output devices to the EV-2
modules. For analog audio pin assignments, see Figure 3 or Figure 5 below. For AES/EBU pin
assignments, see Figure 6 below.
• Connect a power supply to the ATX Power Connector at P450 on each EV-2 module.
• Connect the CAT5 crossover cable between the Ethernet jacks at J5 on each CM board.
• Connect a stereo audio source to the analog inputs at J300.
• Connect a stereo audio monitor to the analog outputs at J401.
• Apply power to both EV-2 modules.
• Verify that you have established a proper connection. See Table 1 on page 6 for Ethernet connector
LED status .
• On the EV-2, the LED CR710, if on, indicates that the AES/EBU receiver does not detect a valid
AES/EBU data input stream. If AES/EBU I/O is not being used, this can be disregarded. Other-
wise, connect a proper AES/EBU signal to J700. Note that there must be a valid AES/EBU input
for the AES/EBU output to work.
The units are now ready to pass audio. The audio input at J300 on one board should now appear at J401 on
the other board and vice versa.
Figure 3. Connector, Switch and Jack Locations
J401
Audio Outputs
J300
Audio Inputs
P450
ATX Power Connector P504
Serial Bridging
Connector
(+-gnd) (+-gnd)
J5 J6
Ethernet Jacks
Serial MCU
Connector
P501
System Reset Switch
SW508
SW200
Programming
Switch
J700
AES I/O
gnd - + gnd - +
Input Output
CR710
AES LED
Hex Switches
SW201-4
Power Status
(+-gnd) (+-gnd)

Page 6 Rev. 2.0
CobraNetTM EV-2
Switch and Connector Functionality
J300
Audio Input Connector: Phoenix-style connector for two-channel balanced audio input, +14.4 dBu
maximum (0 dBFS). Refer to Figure 5 for the signal connection.
J401
Audio Output Connector: Phoenix-style connector for two-channel balanced audio output, +15.8 dBu
maximum (0 dBFS). Refer to Figure 5 for the signal connection.
J700
AES/EBU I/O Connector: Phoenix-style connector for an AES/EBU stream. Refer to Figure 6 for the
signal connection. For the AES/EBU tranceiver to operate properly a vailid AES/EBU signal must be
provided at the AES/EBU input.
P450
ATX power supply connector: ATX power supply is not included with this kit.
Module
CM-1 CM-2
Condition Left LED Right LED Left LED Right LED
Conductor Flashing Green Solid Orange Flashing Orange Flashing Green
Performer Flashing Green Solid Green Solid Orange Flashing Green
Fault Flashing Red Flashing Red Flashing Orange Flashing Orange
Table 1: Ethernet jack indicator legend.
+ - gnd + - gnd
Right
Left
Figure 5. Analog Audio Input and Output Phoenix-style Connectors
+ - gnd
Output
+ - gnd
Input
Figure 6. AES/EBU I/O Phoenix-style Connector

CobraNetTM EV-2
Page 7
P501
9-Pin, D-Type Connector: RS232 connection for communicating with the EV-2 microcontroller using
the supplied routing software or a command line interface ( see Appendix E ). Data format is 19200, e,
8, 1.
P504
9-Pin, D-Type Connector: RS232 connection to the CM for serial bridging. The default data format is
19200 baud, 9-bit format for the CM-1. 9-bit format supports any 8 bit format with parity such as
19200, e, 8, 1. The default data format for the CM-2 is 19200 baud, 8-bit format.
SW200
Programming switch: The EV-2 microcontroller can be programmed via its serial port, connector
P501. The supplied software can be used to perform field updates to the board's code and firmware.
This programming capability is initially disabled, but can be enabled by setting the hex switches to
FFF8H and then clicking on the "Hex Switches" display (see Figure 8 ). For more information about
the programming mode, please refer to the Programming the Microcontroller section.
SW201-SW204
Hex switches: SW201-SW204 may be used to uniquely identify the unit on a network. Valid settings
fall within the range 0000-FFEF (values FFF0-FFFF are reserved). Changing these values updates the
value of the CobraNet module's SNMP variable, sysName, to the current hex switch value. Through
SNMP, the user may query this variable. The SNMP response is of the form
"PEAK_AUDIO_EVAL-SWwxyz", where the wxyz represents the hex values of the switches in
ASCII format.
SW500
System reset switch: This momentary switch resets the EV-2 and attached CM, and initiates calibration
operations for the analog-to-digital converter (ADC) and digital-to-analog converter (DAC).
Software
The EV-2 is supplied with the CNEval.exe application, which may be used to setup audio routes on the
EV-2 (this should not be confused with routing audio over the CobraNet network). The EV-2 has eight
sources of audio input, with each source consisting of a stereo pair of audio channels. The sources are:
• Four Synchronous Serial Interface (SSI) audio streams from the CM
• An AES/EBU audio input stream.
• Two audio streams from the ADC
• A sine wave generator
The ADC produces two sets of stereo audio streams, one high-quality and one low-latency. Please refer to
the Cirrus Logic CS5396-KS documentation for more information on the ADC. The sine wave generator
produces a stream of two identical 24-bit resolution sine waves. Using CNEval.exe, the user can route any
of these eight source streams to any of the six output streams. The available output streams are the four SSI
audio streams going to the CM, one going to the DAC and one to the AES/EBU transmitter.

Page 8 Rev. 2.0
CobraNetTM EV-2
CNEval.exe communicates with the EV-2 via an RS-232 serial connection. CNEval.exe can communicate
using either COM1 or COM2 of the PC on which it is running. The connection from computer to EV-2
must be made as follows:
• Connect a straight-through, male-to-female, 9-pin RS232 cable to EV-2 connector P501.
• Select the appropriate PC serial port. The software will attempt to make contact with the EV-2.
• Once communication is established, the routing can then be configured. (See Figure 7 below for
an example of a routing scheme.)
The default on power up state of the EV-2 is for the ADC and DAC to be the source and sink respectively,
using the CM’s SSI #0 I/O stream. The audio is then transmitted/received via a CobraNet Bundle to/from
the other CM. This allows evaluation of the CobraNet module in the analog domain without any
configuration.
Clicking on any of the product or company logos will pull up the corresponding website using the
computer's default browser (an Internet connection is required).
The EV-2 software also has a programming mode that may be used to perform field updates of the EV-2
microcontroller code. For more information about the programming mode, please refer to the section
Programming the Microcontroller below.
Figure 7. Screen Shot of EV-2 Software

CobraNetTM EV-2
Page 9
Detailed Description of EV-2 Components
The Microcontroller
The microcontroller on the EV-2 is a Philips Semiconductor P89C51RD2. This microcontroller has 64
kByte of internal Flash Program Memory and 1 kByte of Static RAM. The microcontroller is field
programmable using the provided CNEval.exe software. The microcontroller's clock rate is 33Mhz.
Philips P89C51RD2 preliminary specification for programming information and part usage may be found
on the Philips Semiconductor website: http://www-us.semiconductors.philips.com/.
Microcontroller Memory Space:
Besides the internal program and data memory space the microcontroller also has an external 64k data
memory space. The microcontroller is hard-wired to execute from internal Flash Program Memory
only. The Flash Program Memory has been segmented to store both Program and FPGA configuration
data. The Program Memory map is shown in Table 2 on page 9 and the data memory map is shown in
Table 3 on page 9:
*After reset, the FPGA is the only device in the upper 32k of the data memory space. The
microcontroller is then able to configure the FPGA and once configured the FPGA performs more
sophisticated address decoding of the upper data memory space. Refer to the FPGA section of this
document for a detailed description of the configuration process and a listing of the current EV-2
FPGA firmware memory map.
Memory Location Description
0x0000-0xBFFF Program Memory
0xC000-0xFFFF FPGA Configuration Data
Table 2: Flash Program Memory Map
Memory Location Description
0x0000- 0x02FF Internal Static RAM
0x0300-0x7FFF External Static RAM
0x8000-0x87FF Unused
0x8800 FPGA express mode configu-
ration*
0x8801-0xFFFF Unused
Table 3: Microcontroller Data Memory Map After Reset but Before FPGA Configuration

Page 10 Rev. 2.0
CobraNetTM EV-2
Microcontroller Port Connections:
Port 0: used for the address/data (AD) bus. Once configured, the FPGA latches the lower address byte
from the AD lines.
Port 1: used for several purposes as shown in Table 4 on page 10.
Port 2: upper address bus. Port 2 is output only.
Bit # Name of Signal I/O Description
0 INIT_IO# I Used when configuring the FPGA.
Refer to Xilinx Spartan datasheet for
more detail.
1 PROGRAM# O Used to initiate the FPGA configura-
tion. Refer to Xilinx Spartan datasheet
for more detail.
2 MUTE# I Mute signal from the CM module
3 HEX_DATA_IN O Not used. May be used to concatenate
settings from other hex switches.
4 HEX_CLOCK O Used to latch the hex switch values
into a serial shift register.
5 HEX_SHIFT O Used to shift the hex switch values
from the serial shift register.
6 HEX_DATA_OUT O The hex switch value from the serial
shift register appears at this input.
7 RS232 O This is not operational and should be
ignored.
Table 4: Port 1 Signal Descriptions

CobraNetTM EV-2
Page 11
Port 3: See Table 5 on page 11.
Interfacing the Microcontroller to the CM
Please refer to the EV-2 schematic, found in Appendix D for information regarding interfacing to the
CM.
The CM has a host interface that allows a host processor (such as an 8051 microcontroller) to interface
to the DSP on the CM. From a hardware perspective the interface to the CM-1 and CM-2 is almost the
same,. The host interface signals are a data strobe signal, HDS#; a read/write line, HRW, an 8-bit
bi-directional data bus, HD0-HD7, and three address lines, HA0-HA2 on the CM-1 and four address
lines, HA0-HA3 on the CM-2. The HEN# line has been configured by the CobraNet software to be
ignored or seen as a logic low. Given this host configuration, the interface of the microcontroller to the
CM host port is straightforward. In addition to the above signals there are two more, HACK# and
HREQ# which can be used as flags to indicate a state change on the CM.
With regard to the CM-1 which uses a Motorola DSP56303, care must be taken with the timing of
HDS# and HWR. Motorola's timing specifications for the DSP56303 host port in a non-multiplexed,
single data strobe mode requires a set up time from the falling edge of HWR# to the falling edge of
HDS# of 4.7ns and the hold time from the rising edge of HDS# to the rising edge of HWR# of 3.3ns.
The pulse of the HDS# signal must be wholly within the pulse of the HWR# signal with the constraints
stated above. Please refer to Motorola's DSP56303 Technical Data sheet for complete information
regarding timing and interface issues. This is available for download from the Motorola web site at
http://www.motorola.com/SPS/DSP/.
Bit # Name of Signal I/O Description
0 RXD I RS232 serial port receive signal.
1 TXD O RS232 serial port transmit signal
2 HREQ# O Connected to the CM module host
request signal. See CobraNet Techni-
cal Datasheet for a complete descrip-
tion of this signal.
3 HACK# I Connected to the CM module host
acknowledge signal. See CobraNet
Technical Datasheet for a complete
description of this signal. May be
used as an interrupt request on the
microcontroller.
4 Watchdog I Watchdog signal from the CM
5 MCU_P35 I/O Connected to SCI_CLK via the
FPGA.
6 WR# O Microcontroller write signal.
7 RD# O Microcontroller read signal.
Table 5: Port 3 Signal Descriptions

Page 12 Rev. 2.0
CobraNetTM EV-2
In the EV-2 application, the host address lines are generated by the address latch in the FPGA (see
Table 6 on page 14) and the host data bus is connected directly to the data bus of the microcontroller.
The HREQ# and HACK# signals are connected to the two interrupt inputs of the microcontroller.
These signals may be used for data handshaking and asynchronus notification respectively.
The final host signal, HRESET#, resets the CM when asserted low. Setting a bit in the host reset
register (see Table 6 on page 14) controls this signal. See the discussion of the FPGA below for more
information about this signal.
Supplemental information regarding the CM Host interface may by found in the section titled "Host
Management Interface" in the CS181xx data sheet available on the Cirrus Logic website: www.
cirrus.com.
Programming the Microcontroller
The EV-2 is designed so that field updates of both the microcontroller firmware and the FPGA
firmware are possible. If only the efficacy and performance of the CobraNet paradigm is being
evaluated, reprogramming of the microcontroller is not required. However, use of the field program
capability may aid in the design of a CobraNet based product.
Modifying the Flash Program Memory of the microcontroller constitutes the update. To program the
flash, either the provided software or a copy of WINISP may be used. (WINISP can be downloaded
from the Philips Semiconductor website: http://www-us.semiconductors.philips.com/)
The programming instructions that follow pertain to the supplied EV-2 routing/programming software,
CNEval.exe. Programming the microcontroller is a multi-stage process:
1. Install the EV-2 CNEval.exe software on your Windows-based computer.
2. Install an RS232 cable from port 1 or 2 on your PC to P501, the 9-pin D-type connector closest
to the center of the board.
3. Run CNEval.exe
4. Change the hex switches (SW201-SW204) to FFF8 (as viewed when looking at the hex
switches). You may, as an alternative, press the key combination Control+Shift+F9 to enable
the Utility-Program menu item.
5. Select "Program" from the Utility menu in CNEval.exe.
6. From the drop-down list box located in the main programming window, select a serial connec-
tion, either port COM1 or COM2 based on which is connected.
7. Located near the two serial RS232 connectors is a switch, SW200. This switch must be set to
the program mode position. The program position is indicated by silk screen on the EV-2
board.
8. Push switch SW508, the momentary reset switch. SW508 is located just behind the hex
switches.
9. Select which firmware to update, either the FPGA or the 8051.
10. Wait for programming to complete. Do not interrupt the programming process!
11. Once programming has completed for the microcontroller or the FPGA firmware, return the
programming switch, SW200, to the normal operation position and press the reset switch,
SW508.

CobraNetTM EV-2
Page 13
12. Click OK to return to the routing window in CNEval.exe.
Note: When using Philip Semiconductor's WINISP application, instructions 2, 7, 8, 10 and 11 are
applicable.
Interfacing Serial Audio to the CM
In general, interfacing to most off-the-shelf A/D and D/A converters is straightforward and the CM is no
exception. Most signals for a direct connection to these as well as other audio ICs such as the CS8420
AES/EBU transceiver, are available on the CM module interface connector. Most converters provide for a
choice of bit clock and sample (frame) clock polarity, as well as audio data formats such as SPI or I2S.
The A/D converter, a Cirrus Logic CS5396 introduces one wrinkle. The CS5396 needs a master clock of
256FS (one that is 256 times the sample rate frequency). This is not directly supplied on the CM interface
connector. Additional circuitry is required to derive a 256FS clock from the 512FS clock supplied by the
CM. The CS5396 is configured for slave operation, which means that it requires a bit clock and a sample
(frame) clock input. The bit and sample clocks are direct connections from SCK and FS1 respectively, as is
the data stream which comes from one of the SSI ports. The CM can be configured to clock data from
either edge of the bit clock, as well as allowing for specifying the polarity of the sample clock. (See the
CobraNet Technology Datasheet for more information.) This is important since the CS5396 works with
sample pairs which need to be phase aligned. The polarity of the sample clock specifies this alignment. For
the EV-2 application, the SSI ports of the CM have been programmed to send two channels per port. This
allows a straightforward connection without any demultiplexing.
The connection to the CS4396 D/A converter is straightforward, as it is able to use the 512FS clock
directly from the CM for its master clock. Like the SCS5396, it uses the bit clock and sample clock directly
from the CM. Data to the DAC and from the ADC are also direct except that they pass through a selector
circuit in the FPGA. If a particular design does not include multiple sources of audio, then the connection
can be direct to the CM interface connector.
FPGA
The Field Programmable Logic Array is a Xilinx Spartan XCS10XLVQ100-4. It is mapped into the
microcontroller's memory space. The microcontroller must configure the FPGA after power on or reset.
Express mode configuration is used for this part. Refer to the Xilinx Spartan XL family data sheet for more
information on the Express mode configuration operation. This data sheet can be found at the Xilinx web
site, http://www.xilinx.com/. The address for configuration is 0x8800. Once configured, the FPGA's two
main functions are to decode the microcontroller's address signals and to route audio from a user selected
source to a user selected destination. Secondary functions are to generate a sine wave signal and implement
registers whose function are mostly of a control nature. A discussion of the memory decoding, routing,
sine wave generation and other functions follow.
The memory map of the upper 32k of the microcontroller space after configuration, is shown in Table 6 on
page 14. All bit-defined locations use the least significant microcontroller data bus signal AD0 as the

Page 14 Rev. 2.0
CobraNetTM EV-2
controlling bit. Other data bits are ignored on these registers. Power on and reset default for all registers is
0 unless specified otherwise.
Memory
Location R/W Description
0x8000 W Bit register for green LED, CR903. 0=LED on, 1=LED off. Refer
to Table 10 on page 17 for this and other LED registers.
0x8001 W Bit register for red LED, CR904. 0=LED on, 1=LED off.
0x8002 W Bit register for yellow LED, CR905. 0=LED on, 1=LED off.
0x8004 W Bit register for green LED blink control. 0=blink off, 1=blink on.
0x8005 W Bit register for green LED blink control. 0=blink off, 1=blink on.
0x8006 W Bit register for green LED blink control. 0=blink off, 1=blink on.
0x8008 W DAC audio routing address (see Table 7 on page 16).
0x8009 W Bit register for DAC mute signal. 0=mute on, 1=mute off.
0x800A W Bit register for DAC sample rate mode. 0=48k, 1=96k.
0x800B W Bit register for DAC reset signal. 0=reset on, 1=reset off.
0x8010 R ADC Calibration Status. 1=Calibrating, 0=Ready. See the Cali-
brating the ADC section for details.
0x8010 W Manual ADC Calibration. 0=Normal, 1=Calibrate. See the Cali-
brating the ADC section for details.
0x8011 W Bit register for ADC slave/master control. 0=Slave, 1=Master.
0x8018 W AES/EBU audio routing address (see Table 7 on page 16).
0x8019 W Bit register for AES/EBU mute signal. 0=AES output muted,
1=Unmuted.
0x8020 W SSI 0 audio routing address (see Table 7 on page 16).
0x8021 W Bit register for SSI 0 mute signal. 0=Muted, 1=Unmuted.
0x8028 W SSI 1 audio routing address (see Table 7 on page 16).
0x8029 W Bit register for SSI 1 mute signal. 0=Muted, 1=Unmuted.
0x8030 W SSI 2 audio routing address (Table 7 on page 16).
0x8031 W Bit register for SSI 2 mute signal. 0=Muted, 1=Unmuted.
0x8038 W SSI 3 audio routing address (Table 7 on page 16).
0x8039 W Bit register for SSI 3 mute signal. 0=Muted, 1=Unmuted.
0x8040 Note 1 CM-1 Host Port ICR register. CM-2 Message-A register.
Table 6: Microcontroller Memory Map of Upper 32k After FPGA Configuration

CobraNetTM EV-2
Page 15
Note 1: The FPGA only decodes this address. The actual register located is on the CM. See the Motorola
DSP56303 users manual for a discussion of each of these host port registers.
Configuring the FPGA
The FPGA is configured from data that is stored in the upper 16kbytes (0xC000-0xFFFF) of the
microcontroller’s Flash Program Memory. The microncontroller code for configuring the FPGA uses
express mode which writes byte-wide data to the FPGA. Refer to the Xilinx Spartan XL family data
sheet for more information on the express mode configuration operation. The address used for writing
configuration data is 0x8800.
Functional Discussion of FPGA Operation
Routing of Audio Data
The routing of audio data is achieved by a simple 8 to 1 multiplexing operation; for each audio
destination three data bits in an a register in the FPGA select the source. For example, the three
data bits in the D/A audio routing register determine which audio source is selected to appear at the
analog outputs (J401). Table 7 on page 16 shows the definition of the data bits and the respective
0x8041 Note 1 CM-1 Host Port CVR register. CM-2 Message-B register.
0x8042 Note 1 CM-1 Host Port ISR register. CM-2 Message-C register.
0x8043 Note 1 CM-1 Host Port IVR register. CM-2 Message-D register.
0x8044 Note 1 CM-1: Unused. CM-2 Data-A register.
0x8045 Note 1 CM-1 Host Port Data register high. CM-2 Data-B register.
0x8046 Note 1 CM-1 Host Port Data register middle. CM-2 Data-C register.
0x8047 Note 1 CM-1 Host Port Data register low. CM-2 Data-D register.
0x8048 R/W CM-2 Host Control Register.
0x8049 R/W CM-2 Host Status Register.
0x8051 W Bit register for Host reset signal. 0=Asserted, 1=Deasserted.
0x8058 R/W Auxiliary lines. Not used, for test purposes only.
0x8060 R FPGA configuration major version.
0x8061 R FPGA configuration minor version.
0x8062 R FPGA configuration revision number.
0x8070 R/W Sinewave Gain register. See Table 9 on page 17.
0x8078 R/W Sinewave Frequency register. See Table 8 on page 16.
Memory
Location R/W Description
Table 6: Microcontroller Memory Map of Upper 32k After FPGA Configuration (Cont’d)

Page 16 Rev. 2.0
CobraNetTM EV-2
audio source.
Sine Wave Generator
The FPGA contains a 32-sample, 24-bit, sine table. The table is stepped through at the sample
clock rate so the resulting fundamental frequency is 48kHz / 32 samples = 1500Hz and 3000Hz at
96kHz. Limited control over frequency and gain is provided. Listed below are the values to write
to the frequency and gain registers in the FPGA.
microcontroller data
bit
AD2 AD1 AD0
Audio Source
000CMSSI0
001CMSSI1
010CMSSI2
011CMSSI3
1 0 0 ADC Low-latency
1 0 1 ADC High-quality
1 1 0 AES/EBU Input
1 1 1 Sine wave
Table 7: Definition of Audio Routing Register Bits
Frequency register data bits
AD3 AD2 AD1 AD0
Frequency
48kHz sample rate
(96kHz sample rate)
00011.5kHz(3.0kHz)
00103.0kHz(6.0kHz)
00114.5kHz(9.0kHz)
0 1 0 0 6.0 kHz (12.0 kHz)
0 1 0 1 7.5 kHz (15.0 kHz)
0 1 1 0 9.0 kHz (18.0 kHz)
0 1 1 1 10.5 kHz (21.0 kHz)
1 0 0 0 12.0 kHz (24.0 kHz)
Table 8: Sine Wave Frequency Register Bit Definitions

CobraNetTM EV-2
Page 17
LED Control
There are two bit registers to control the state of each of three LEDs. The mapping of control bits
to LED behavior is described in Table 10 on page 17. The data bit is always AD0.
Calibrating the ADC
The CS5396 ADC requires approximately ten seconds to achieve proper operating temperature
after which, for optimal performance, it is necessary to initiate a calibration cycle. After power is
applied and after reset the EV-2 uses an internal timer to count off approximately 10 seconds
before beginning the calibration cycle. Prior to and during the calibration, the ADC calibration
status register will read 1. Once calibration has been completed, the status register will read 0.
Calibration can also be initiated manually by the microcontroller by writing a 1 to the Manual
ADC Calibration register and then immediately returning the register to the 0 state. The FPGA
initiates this one-time power up/reset calibration.
Version Control
The FPGA contains three hardwired eight-bit registers that contain an ASCII version/revision
number of the FPGA configuration file. The microcontroller can read these registers for version
control and reporting purposes.
Gain register
data bits
AD1 AD0
Gain
00 0dB
01 -6dB
10-12dB
11-18dB
Table 9: Sine Wave Gain Register Bit Definitions
Enable Blink Status
00off
10on
01off
1 1 blink
Table 10: LED Status

Page 18 Rev. 2.0
CobraNetTM EV-2
Mute Control
Muting comes from three different sources 1) the microcontroller can mute or unmute audio by
writing to a bit control register. There is one mute bit control register for each output audio path, 2)
the CM asserts its mute signal, and 3) all audio is unconditionally muted during a power on/reset
calibration cycle. If the microcontroller initiates a calibration cycle using the Manual ADC
Calibration register, the ADC automatically mutes itself (i.e., gates off its digital output stream
until calibration has completed).
Hex Switches
Four pins on the 8051 allow the hex switches to be read. The EV-2 circuitry associated with the hex
switches serves as a good example implementing this common CobraNet feature (see Recommended User
Interface Practices section in the CobraNet Programmer’s Manual for a discussion of use of this scheme).
Requirements include a physical (hardware) mapping of the hex switches to a code (software) within the
CM. The methodology to achieve this is listed below:
1. When viewing the hex switches from the front, the rightmost switch should be the first nibble
of the serial data stream, and subsequent nibbles should follow working from the second right-
most switch to the leftmost switch.
2. Two of the four signals will be control signals: a Shift/Load# signal where Shift is high and
Load is Low. The Load allows for parallel, asynchronous loading of the hex switch data into a
shift register and the Shift allows for serial shifting of data out of that register. A clock signal
to perform the shifting operation where data changes on the rising end of the clock. The
74HC165 IC is an example of a part that supports this protocol.
3. The other two signals are the shifted data output and an input that will be shifted serially into
the shift register concatenating it with the hex data. The intent of this latter signal is to allow
for the possibility of concatenating other data, additonal hex switches or otherwise, for appli-
cation specific enhancements.
4. The software will convert the serial hex data stream to a four-byte ASCII value that represents
the switch settings.
As shown in Figure 8, viewing hex switches from the front, the given switch positions would read as
"CA30" in a software query of the hex switch setting. On the EV-2, the microcontoller is responsibile for
reading the switches through the hardware serial interface and converting those readings to an ASCII
representation. This representation is then written to the CM through the host port. Speciafically, the EV-2
microncontroller updates the CM's MI variable, sysName. Using SNMP, the user may query this variable.
The SNMP response is of the form "PEAK_AUDIO_EVAL-SWwxyz", where the wxyz represents the hex
values of the switches in ASCII format. In the example shown in Figure 8, a query of sysName would
return "PEAK_AUDIO_EVAL_SWCA30".
Figure 8. Example Switch Setting

CobraNetTM EV-2
Page 19
EV-2 Schematics, Page-by-Page Description
The following sections provide detailed descriptions of the EV-2 schematic drawings contained in
Appendix D.
Block Diagram
This page is a hierarchical block diagram showing an overview of all schematic pages and
interconnects between pages.
Microcontroller and Hex Switches
This page shows an 8051-type microcontroller, its connections, and peripherals. Peripherals include
32kbytes of SRAM, hex switch interface, clock oscillator and programming switch. The programming
switch circuitry has additional settings via jumpers R204 and R207 to program the Flash with either +5
volts or 12 volts. Voltage selected depends on the particular model of 8051-type microcontroller
installed. Either R204 or R207 should be installed, but not both.
A/D Converter
This circuit is based on the Cirrus Logic CS5396 reference design. See the Cirrus Logic website,
http://www.cirrus.com/, for a detailed description of the CS5396 and its reference design, the
CDB5396. There is also a white paper at the Cirrus website titled Techniques to Measure and
Maximize the Performance of a 120 dB, 24-bit, 96 kHz A/D Converter Integrated Circuit that provides
an in-depth analysis of the analog input conditioning circuit. One notable deviation in the EV-2 circuit
with respect to the Cirrus reference design is that the EV-2 circuit only runs at 48 kHz (64x
oversampling mode) and only in stand-alone mode.
D/A Converter
This circuit uses the Cirrus Logic CS4396 D/A Converter. See the Cirrus Logic website,
http://www.cirrus.com/, for a detailed description of the CS4396. On the EV-2 the mute transistors on
the analog outputs are omitted. The CS4396 in the EV-2 design runs in single sample rate and
stand-alone mode.
Connectors and Interfaces
This page shows the CM interface connectors, P510 and P511, as well as the RS232 interface. Also
included on this page are:
• The master audio clock (FS512) divide-by-two circuit (U506) that provides a clock for the A/D
converter.
• Buffering and serial termination (U510) for the bit clocks and sample (frame) clocks that go to the
A/D, D/A converters and the AES/EBU transceiver. Buffereing and termination reduces over and
under shoot. Over and under shoot may adversely affect audio performance and increase RF emis-
sions. This conditioning is recommended but not necessary in all applications.
• The reset switch circuit, SW508 and associated components.
Optional VCXO
Although the CM produces a high quailty master clock, in some applications, the master clock my be
compromised by long or noisy signal paths (i.e. ribbon cable connection). An optional VCXO circuit
was included as an example of re-clocking the master clock (FS512). This circuit is designed to