Texas Instruments TPS7A87 User manual

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TPS7A87 Evaluation Module
User's Guide
SBVU038–November 2016
TPS7A87 Evaluation Module
This user’s guide describes the operational use of the TPS7A8701EVM-852 evaluation module (EVM) as
a reference design for engineering demonstration and evaluation of the TPS7A8701RTJ, dual low-noise,
low-dropout voltage regulator (LDO). Included in this user’s guide are setup and operating instructions,
thermal and layout guidelines, a printed circuit board (PCB) layout, a schematic diagram, and a bill of
materials (BOM).
Throughout this document, the terms demonstration kit, evaluation board, evaluation module are
synonymous with the TPS7A8701EVM-852.
The following related documents are available through the Texas Instruments web site at
http://www.ti.com.
Related Documentation
Device Literature Number
TPS7A87 SBVS281

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Contents
1 Introduction ................................................................................................................... 3
1.1 Before You Begin................................................................................................... 3
2 EVM Setup.................................................................................................................... 4
2.1 Input/Output Connectors and Jumper Descriptions............................................................ 4
2.2 Soldering Guidelines ............................................................................................... 7
2.3 Equipment Connection............................................................................................. 7
3 Operation ..................................................................................................................... 7
4 PCB Layout................................................................................................................... 8
5 Schematic ................................................................................................................... 11
6 Bill of Materials ............................................................................................................. 12
List of Figures
1 Assembly Layer.............................................................................................................. 8
2 Top Layer Routing........................................................................................................... 8
3 Layer 2 Routing.............................................................................................................. 9
4 Layer 3 Routing.............................................................................................................. 9
5 Bottom Layer Routing ..................................................................................................... 10
6 Schematic ................................................................................................................... 11
List of Tables
1 Bill of Materials ............................................................................................................. 12
Trademarks
All trademarks are the property of their respective owners.

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1 Introduction
The Texas Instruments TPS7A8701EVM-852 EVM helps design engineers evaluate the operation and
performance of the TPS7A87 linear regulator for possible use in their own circuit application. This
particular EVM configuration contains a dual low-noise, high-PSRR linear regulator, ideal for high-
performance signal chain. The regulator is capable of delivering up to 0.5 A per channel to each load with
low dropout (VIN – VOUT) voltage for high-efficiency operation. For stability, each channel requires a 10-
µF input capacitor and 10-µF output capacitor for the TPS7A87.
1.1 Before You Begin
The following warnings and cautions are noted for the safety of anyone using or working close to the
TPS7A8701EVM-852. Observe all safety precautions.
WARNING
Hot surface. Contact may cause burns. Do not touch.
CAUTION
The circuit module may be damaged by overtemperature. To avoid damage,
monitor the temperature during evaluation and provide cooling, as needed, for
your system environment.
CAUTION
Some power supplies can be damaged by application of external voltages. If
using more than one power supply, check your equipment requirements and
use blocking diodes or other isolation techniques, as needed, to prevent
damage to your equipment.
CAUTION
The circuit module is not a finished product or electrical appliance. The module
does not contain current or voltage thresholds for circuit protection. It must be
used by qualified personnel with additional equipment for evaluation only.

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2 EVM Setup
This section describes how to properly connect and setup the TPS7A8701EVM-852, including the jumpers
and connectors on the EVM board.
2.1 Input/Output Connectors and Jumper Descriptions
2.1.1 J1 – VIN1
Channel-1, input power-supply voltage connector. Twist together the positive input lead and ground return
lead from the input power supply; keep the leads as short as possible to minimize input wire inductance.
Add additional bulk capacitance between J1 and J4 (use the C1 footprint) if the supply leads are longer
than six inches. For example, an additional 47-µF electrolytic capacitor connected from J1 to ground
improves the transient response of the TPS7A87, while eliminating unwanted ringing on the input because
of long wire connections.
2.1.2 J2 – VOUT1
Channel-1, regulated, output voltage connector.
2.1.3 J3 – VPU1
Channel-1, pullup-voltage selector for PG1. This EVM is designed so that PG1 can be pulled up to either
VOUT1 by shorting J3, or pulled up to another voltage by applying an external voltage to the RPU1 post.
2.1.4 J4 – GND
Return connector for the channel-1, input power supply.
2.1.5 J5 – GND
Channel-1, output, ground return connector.
2.1.6 J6 – VIN2
Channel-2, input, power-supply voltage connector. Twist together the positive input lead and ground return
lead from the input power supply; keep the leads as short as possible to minimize input wire inductance.
Add additional bulk capacitance between J6 and J8 (use the C9 footprint) if the supply leads are longer
than six inches. For example, an additional 47-µF electrolytic capacitor connected from J6 to ground
improves the transient response of the TPS7A87, while eliminating unwanted ringing on the input because
of long wire connections.
2.1.7 J7 – VOUT2
Channel-2, regulated, output voltage connector.
2.1.8 J8 – GND
Return connector for the channel-2, input power supply.
2.1.9 J9 – GND
Channel-2, output, ground return connector.
2.1.10 J10 – ANYOUT2
The channel-2 output voltage of the TPS7A87 is selectable in accordance with the names given to the
output voltage setting pins: 50 mV, 100 mV, 200 mV, 400 mV, 800 mV, 1.6 V, and 1.6 V. For each pin
connected to the ground, the output voltage setting increases by the value associated with that pin name,
starting from the value of the reference voltage of 0.8 V; floating the pins has no effect on the output
voltage.

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2.1.11 J11 – ANYOUT1
The channel-1 output voltage of the TPS7A87 is selectable in accordance with the names given to the
output voltage setting pins: 50 mV, 100 mV, 200 mV, 400 mV, 800 mV, 1.6 V, and 1.6 V. For each pin
connected to the ground, the output voltage setting increases by the value associated with that pin name,
starting from the value of the reference voltage of 0.8 V; floating the pins has no effect on the output
voltage.
2.1.12 J12 – VPU2
Channel-2 pullup voltage selector for PG2. This EVM is designed so that PG2 can be pulled up to either
VOUT1 by shorting J12, or pulled up to another voltage by applying an external voltage to the RPU2 post.
2.1.13 J13 – EN1
Channel-1 output enable. To enable the output for channel 1, connect a jumper to short VIN1 to EN1. To
disable the output, connect a jumper to short EN1 to GND.
2.1.14 J14 – EN2
Channel-2 output enable. To enable the output for channel 2, connect a jumper to short VIN2 to EN2. To
disable the output, connect a jumper to short EN2 to GND.
2.1.15 J15 – CTRL1
Channel-1, soft-start control. Connect a jumper to short VIN1 to CTRL1 for a fast charge time. Connect a
jumper to short CTRL1 to GND for a slower startup.
2.1.16 J16 – CTRL2
Channel-2, soft-start control. Connect a jumper to short VIN2 to CTRL2 for a fast charge time. Connect a
jumper to short CTRL2 to GND for a slower startup.
2.1.17 TP1 – VIN1
Channel-1, input, sense test point.
2.1.18 TP2 – VOUT1
Channel-1, output, sense test point.
2.1.19 TP3 – VOUT2
Channel-2, output, sense test point.
2.1.20 TP4 – VIN2
Channel-2, input, sense test point.
2.1.21 TP5 – EN1
Channel-1, enable, sense test point.
2.1.22 TP6 – EN2
Channel-2, enable, sense test point.
2.1.23 TP7 – GND
Ground.

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2.1.24 TP8 – GND
Ground.
2.1.25 TP9 – GND
Ground.
2.1.26 TP10 – GND
Ground.
2.1.27 TP11 – GND
Ground.
2.1.28 TP12 – GND
Ground.
2.1.29 TP13 – GND
Ground.
2.1.30 TP14 – GND
Ground.

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2.2 Soldering Guidelines
To avoid damaging the integrated circuit (IC), use a hot-air system for any solder rework to modify the
EVM for the purpose of repair or other application reasons.
2.3 Equipment Connection
1. Set the input power supplies for each channel to 6.5 V (max), and turn the power supplies off.
2. Connect the positive voltage lead from input power supply 1 to VIN1, at the J1 connector of the EVM.
3. Connect the ground lead from input power supply 1 to GND at the J4 connector of the EVM.
4. Connect the positive voltage lead from input power supply 2 to VIN2, at the J6 connector of the EVM.
5. Connect the ground lead from input power supply 2 to GND at the J7 connector of the EVM.
6. Connect a 0-A to 0.5-A load between OUT1 and GND.
7. Connect a 0-A to 0.5-A load between OUT2 and GND.
8. Disable the output for channel 1 by shorting EN1 to GND on J13.
9. Disable the output for channel 2 by shorting EN2 to GND on J14.
3 Operation
1. Turn on the power supplies.
2. Enable the channel 1 output by shorting the EN1 pin to VIN1 on J13.
3. Enable the channel 2 output by shorting the EN2 pin to VIN2 on J14.
4. Vary the respective load and input voltage, as necessary, for test purposes.

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4 PCB Layout
Figure 1 to Figure 5 illustrate the PCB layout for this EVM.
Figure 1. Assembly Layer
Figure 2. Top Layer Routing

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Figure 3. Layer 2 Routing
Figure 4. Layer 3 Routing

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Figure 5. Bottom Layer Routing