A590 SERVICE MANUAL
Theory of Operation
The Host Power supply provided + 5 volts to this Assembly through an 86-pin connector where it enables the A590 external
power supply.
The Assembly as described herein shall consist of three independent Subsystems:
[1] MEMORY
[2] DMA/SCSI CONTROLLER
[3] A TO-CONFIG
A TO-CONFIG for all on-board devices (RAM, ROM, DMA Controller) shall be executed by the DMA Controller Chip.
The DMA chip provides “
_
RAMSEL” and “
__
ROMCS” Signals to indicate an access to the on board RAM and ROM,
respectively. Düring auto-config time the DMA chip must indicate how much RAM is on board. It determines this by reading
its “RAMSZ” line. The following chart shows the relationship between the Signal on RAMSZ and the amount of RAM that
should be present:
Signal Amount of RAM
Ground None
Inverse of CDAC 512K
CDAC IM
Vcc 2M
The Signal applied to “RAMSZ” is determined by JP1. The DMA Controller chip also generates the Signal “
_
SLAVE” whenever
something within the auto config address space is being accessed. This is tied directly to “
_
OVR” to allow for generation
of “
_
DTACK” on our board.
The auto-boot ROMS simply connect to the bus with the data Outputs being enabled by “
_
ROMCS”. “
_
DTACK” is generated
automatically by the DMA chip when the ROM is accessed.
The RAM section is controlled by 5. (See Timing Diagram.) 3 generates RAS and CAS for the RAMs as well as DTACK.
The RAM is set up in 4 separate banks, each with its own CAS, but a common RAS. The CAS on the bank that is being
accessed has a special access waveform, while the other three CAS lines will just perform a refresh. After the access, a hidden
refresh is performed. If the RAM is not being accessed, all of the RAM is just continually refreshed. On writes, the byte(s)
(upper, lower or both) to write shall be determined by gating and write Signal to the RAMs with DS and LDS. Byte control
of reads is gated by applying LDS or DS to the output enable inputs of the RAMs. The multiplexed address that DRAMS
need is generated by 8 and 9, which is controlled by the mux signal from 5. There are two possible relationships between
processor timing and the CI and C3 clocks. 5 only understands one of these (Agnus normally synchronizes the processor
to this relationship, but this relationship can be upset by DMA operations, for instance). If 5 sees the other relationship,
it will insert a single wait state to realign the 68000 to what it considers correct timing. This special cycle is shown on the
timing diagram in addition to normal cycles.
The DMA Controller ( l) attaches to the bus and to the WD33C93 SCSI Controller chip ( 4). 4 attaches to an internal 50
pin SCSI connector and goes out to a DB25 connector on the back of the board which allows attachment of SCSI peripherals.
The DMA Controller also provides a special XT interface for IBM PC XT bus type drives (this is NOT ST-506). This connects
to the internal drive. The 7-MHz clock required by the DMA Controller is generated by 6. The special SCSI bus reset signal
is generated whenever the Amiga is reset.
2-1
