Computer Automation ALPHA 16 User manual

COMPUTER
AUTOMATION
ALPHA 16 & NAKED MINITM 16
COMPUTER REFERENCE MANUAL

INDEX
1. GENERAL DESCRIPTION
2. ALPHA 16 AND NAKED MINI 16
INSTRUCTIONS
3. INPUT/OUTPUT
4. PROCESSOR OPTIONS
Appendix A: HEXIDECIMAL ARITHMETIC
Appendix
B: INSTRUCTION SET BY CLASS
{
Appendix C: LOGICAL FUNCTION DESCRIPTION
1.1 Introduction
1.2 Characteristics
1.3 Processor Configuration
2.1 Introduction
2.2 Arithmetic Overflow
2.3 Memory Reference Instructions: Word Mode
2.4 Memory Reference Instructions: Byte Mode
2.5 Immediate Instructions
2.6 Conditional Jump Instructions
2.7 Shift Instructions
2.8 Register Change Instructions
2.9 Control Instructions
3.1 Introduction
3.2 Priority Interrupt System
3.3 General Input/Output Instructions
3.4 Block Transfer Instructions
3.5 Automatic Input/Output Instructions
4.1 Introduction
4.2 TTY Interface
4.3 Power Fail/Restart
4.4 Real-Time Clock
4.5 Autoload
4.6 Memory Protect
Appendix D: INSTRUCTION SET, ALPHABETICAL ORDER
Appendix E: INSTRUCTION SET, NUMERICAL ORDER
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ALPHA 16 and NAKED MINI™16
COMPUTER
REFERENCE MANUAL
JANUARY 1972
(REVISED EDITION)
COMPUTER AUTOMATION,INC. 895 W. 16th ST.,NEWPORT BEACH,CALIF. 92660
COPVRIGHT,1971 COMPUTER AUTOMATlON,INC.
$20.00
00-9701900-AO

TABLE OF CONTENTS
Section
Page
1.
GENERAL DESCRIPTION
1-1
1.1 Introduction
1-1
1.1.1 General
1-1
1.1.2 The NAKED MINI Concept 1-1
1.1.3 The ALPHA 16 1-4
1.1.4 Applications 1-4
1.2 Characteristics 1-4
1.2.1 General 1-4
1.2.2 Processor 1-4
1.2.3 Instruction Set
1-5
1.2.4 Memory Addressing
1-5
1.2.5 I/O Structure
1-7
1.2.6 Processor Mounted Options
1-7
1.2.7 Processor Plug-In Options
1-8
1.2.8 Peripheral Equipment
1-8
1.2.9 Standard Software
1-8
1.2.10 Optional Software
1-11
1.2.11 Processor Physical Characteristics 1-12
1.3 Processor Configuration 1-12
1.3.1 General 1-12
1.3.2 Adder 1-14
1.3.3 Hardware Registers 1-14
1.3.4 Processor Data Paths 1-14
1.3.5 Shift Control 1-15
1.3.6 I/O Control and Data Paths 1-15
1.3.7 Instruction Execution Sequences 1-18
1.3.8 Data Word Format
1-21
1.3.9 Data Byte Format 1-23
1.3.10 Memory Address Formats 1-25
1.3.11 Control Console 1-28
1.3.12 Console Operation
1-31
2.
ALPHA 16 AND NAKED MINI 16 INSTRUCTIONS
2-1
2.1 Introduction
2-1
2.1.1 General
2-1
2.1.2 Symbolic Notation
2-1
iii

Section
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
iv
TABLE OF CONTENTS (Continued)
Arithmetic Overflow
2.2.1 General
2.2.2 Overflow Conditions
-Memory Reference Instructions: Word Mode
2.3.1 General
2.3.2 Memory Addressing: Word Mode
2.3.3 Instruction Description Format
2.3.4 Memory Reference Instruction Descriptions
Memory Reference Instructions: Byte Mode
2.4.1 General
2.4.2 Byte Addressing
2.4.3 Instruction Descriptions
Immediate Instructions
2.5.1 General
2.5.2 Immediate Instruction Format
2.5.3 Immediate Instruction Functions
2.5.4 Instruction Descriptions
Conditional Jump Instructions
2.6.1 General
2.6.2 Testable Conditions
2.6.3 Instruction Descriptions
Shift Instructions
2.7.1 General
2.7.2 Single Register Shifts
2.7.3 Double Register Shifts
2.7.4 Shift Instruction Formats
2
.. 7.5 Shift Timing
2.7.6 Instruction Descriptions
Register Change Instructions
2.8.1 General
2.8.2 Instruction Format
2.8.3 Instruction Descriptions
Control Instructions
2.9.1 General
2.9.2 Format
2.9.3 Instruction Descriptions
Page
2-2
2-2
2-2
2-4
2-4
2-4
2-9
2-10
2-19
2-19
2-20
2-24
2-30
2-30
2-30
2·30
2-30
2·33
2-33
2-34
2·36
2-40
2-40
2-40
2-43
2·43
2A3
2-44
2·58
2·58
2·58
2·58
2·66
2·66
2·66
2-67

TABLE OF CONTENTS (Continued)
Section
Page
3.
INPUT /OUTPUT
3-1
3.1
Introduction
3-1
3.1.1 General
3-1
3.1.2 Control Requirements
3-1
3.1.3 Organization 3-2
3.1.4 . Reserved Device Addresses 3-4
3.2 Priority Interrupt System 3-5
3.2.1 General 3-5
3.2.2 Basic Concepts 3-6
3.2.3 Interrupt Processing 3-7
3.2.4 Interrupt Latency 3-12
3.2.5 Interrupt Priorities 3-14
3.2.6 Reserved Interrupt Locations in Memory 3-14
3.3 General
Input/Output Instructions 3-15
3.3.1 General 3-15
3.3.2 Sense Instructions 3-17
3.3.3 Select Instructions 3-18
3.3.4
Input to Register Instructions 3-18
3.3.5
Output from Register Instructions 3-22
3.4 Block Transfer Instructions 3-23
3.4.1 General 3-23
3.4.2 Block Transfer Operation 3-23
3.5 Automatic
Input/Output Instructions 3-26
3.5.1 General 3-26
3.5.2 Format 3-26
3.5.3 Operation 3-27
3.5.4 Direct Memory Channels 3-27
3.5.5 In-Line Programming 3-29
3.5.6 Instruction Descriptions 3-30
4. PROCESSOR OPTIONS
4-1
4.1 Introduction
4-1
4.1.1 General
4-1
4.1.2 Standard Configurations
4-1
4.2 TTY Interface
4-1
4.2.1 General
4-1
4.2.2 Operation
4-1
4.2.3 Data Transfer Rates 4-2
v

Section
4.3
4.4
4.5
4.6
TABLE OF CONTENTS (Continued)
4.2.4 Programming
4.2.5 Reserved Memory Locations
Power Fail/Restart
4.3.1 General
4.3.2 Operation
4.3.3 Interrupt Control
4.3.4 Programming Examples
4.3.5 Reserved Memory Locations
Real-Time Clock
4.4.1 General
4.4.2 Clock Sources
4.4.3 Operation
4.4.4 Control Instructions
4.4.5 Interrupt Locations
Autoload
4.5.1 General
4.5.2 Operating Procedures
4.5.3 Operation
4.5.4 Reserved Memory Locations
~emory Protect
4.6.1 General
4.6.2 Operation
4.6.3 Control Instructions
4.6.4 Reserved Memory Locations
Appendix A HEXIDECIMAL ARITHMETIC
Appendix B: INSTRUCTION SET BY CLASS
Appendix C: LOGICAL FUNCTION DESCRIPTION
Appendix D: INSTRUCTION SET, ALPHABETICAL ORDER
Appendix E: INSTRUCTION SET, NUMERICAL
ORDER
vi
Page
4-2
4-5
4-6
4-6
4-6
4-7
4-7
4-8
4-8
4-8
4-8
4-9
4-9
4-10
4-10
4-10
4-10
4-11
4-11
4-11
4-11
4-11
4-12
4-12
A-I
B-1
C-I
lD-1
E-I

LIST OF ILLUSTRATIONS
Figure
Page
1-1. Evolution
of Compatible 16-Bit Computers
1-2
1-2. Conventional Mini Computer Application
1-3
1-3. NAKED MINI 16 Application
1-3
1-4. ALPHA 16 and NAKED MINI 16 Block Diagram 1-13
1-5. I/O Control and Data Paths 1-17
1-6. Data Word Bit Identification
1-21
1-7. Byte Storage, Two Bytes Per Word 1-24
1-8. Data in Memory, One Byte Per Word 1-26
1-9. Data in Memory, Two Bytes Per Word 1-26
1-10. Basic Word Address Format 1-27
1-11. Byte Address Format 1-27
1-12. Indirect Address Pointer Format 1-28
1-13. ALPHA 16 Control Panel 1-29
2-1. Memory Reference Instruction Format: Word Mode
2-6
2-2. Direct Memory Addressing: Word Mode
2-7
2-3. Indirect Addressing: Word Mode
2-8
2-4. Memory Reference Instruction Format: Byte Mode
2-21
2-5. Direct Memory Addressing: Byte Mode 2-22
2-6. Indirect Addressing: Byte Mode 2-23
2-7. Immediate Instruction Format
2-31
2-8. Conditional Jump Format 2-35
2-9. Logical Right Shift
2-41
2-10. Logical Left Shift
2-41
2-11. Rotate Right 2-41
2-12. Rotate Left 2-41
2-13. Arithmetic Left Shift 2-42
2-14. Arithmetic Right Shift 2-43
2-15. Long Right Shift 2-43
2-16. Long Left Shift 2-43
2-17. Long Rotate Right 2-43
2-18. Long Rotate Left 2-44
2-19. Single Register Shift Format 2-44
2-20. Long Shift Format 2-44
3-1. Computer/Interface/Device Relationships 3-3
3-2. Party Line 110 Structure
3-5
3-3. Single Instruction Interrupt Processing 3-10
3-4. Interrupt Subroutine Processing
3-11
vii

LIST OF ILLUSTRATIONS (Continued)
Figure
3-5. General Input/Output Instruction Format
3-6. Word Movement Sequence
3-7. Byte Movement Sequence
viii
Page
3-17
3-28
3-28