Computer Automation ALPHA 16 User manual

COMPUTER
AUTOMATION
ALPHA 16 & NAKED MINITM 16
COMPUTER REFERENCE MANUAL

INDEX
1. GENERAL DESCRIPTION
2. ALPHA 16 AND NAKED MINI 16
INSTRUCTIONS
3. INPUT/OUTPUT
4. PROCESSOR OPTIONS
Appendix A: HEXIDECIMAL ARITHMETIC
Appendix
B: INSTRUCTION SET BY CLASS
{
Appendix C: LOGICAL FUNCTION DESCRIPTION
1.1 Introduction
1.2 Characteristics
1.3 Processor Configuration
2.1 Introduction
2.2 Arithmetic Overflow
2.3 Memory Reference Instructions: Word Mode
2.4 Memory Reference Instructions: Byte Mode
2.5 Immediate Instructions
2.6 Conditional Jump Instructions
2.7 Shift Instructions
2.8 Register Change Instructions
2.9 Control Instructions
3.1 Introduction
3.2 Priority Interrupt System
3.3 General Input/Output Instructions
3.4 Block Transfer Instructions
3.5 Automatic Input/Output Instructions
4.1 Introduction
4.2 TTY Interface
4.3 Power Fail/Restart
4.4 Real-Time Clock
4.5 Autoload
4.6 Memory Protect
Appendix D: INSTRUCTION SET, ALPHABETICAL ORDER
Appendix E: INSTRUCTION SET, NUMERICAL ORDER
II
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ALPHA 16 and NAKED MINI™16
COMPUTER
REFERENCE MANUAL
JANUARY 1972
(REVISED EDITION)
COMPUTER AUTOMATION,INC. 895 W. 16th ST.,NEWPORT BEACH,CALIF. 92660
COPVRIGHT,1971 COMPUTER AUTOMATlON,INC.
$20.00
00-9701900-AO

TABLE OF CONTENTS
Section
Page
1.
GENERAL DESCRIPTION
1-1
1.1 Introduction
1-1
1.1.1 General
1-1
1.1.2 The NAKED MINI Concept 1-1
1.1.3 The ALPHA 16 1-4
1.1.4 Applications 1-4
1.2 Characteristics 1-4
1.2.1 General 1-4
1.2.2 Processor 1-4
1.2.3 Instruction Set
1-5
1.2.4 Memory Addressing
1-5
1.2.5 I/O Structure
1-7
1.2.6 Processor Mounted Options
1-7
1.2.7 Processor Plug-In Options
1-8
1.2.8 Peripheral Equipment
1-8
1.2.9 Standard Software
1-8
1.2.10 Optional Software
1-11
1.2.11 Processor Physical Characteristics 1-12
1.3 Processor Configuration 1-12
1.3.1 General 1-12
1.3.2 Adder 1-14
1.3.3 Hardware Registers 1-14
1.3.4 Processor Data Paths 1-14
1.3.5 Shift Control 1-15
1.3.6 I/O Control and Data Paths 1-15
1.3.7 Instruction Execution Sequences 1-18
1.3.8 Data Word Format
1-21
1.3.9 Data Byte Format 1-23
1.3.10 Memory Address Formats 1-25
1.3.11 Control Console 1-28
1.3.12 Console Operation
1-31
2.
ALPHA 16 AND NAKED MINI 16 INSTRUCTIONS
2-1
2.1 Introduction
2-1
2.1.1 General
2-1
2.1.2 Symbolic Notation
2-1
iii

Section
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
iv
TABLE OF CONTENTS (Continued)
Arithmetic Overflow
2.2.1 General
2.2.2 Overflow Conditions
-Memory Reference Instructions: Word Mode
2.3.1 General
2.3.2 Memory Addressing: Word Mode
2.3.3 Instruction Description Format
2.3.4 Memory Reference Instruction Descriptions
Memory Reference Instructions: Byte Mode
2.4.1 General
2.4.2 Byte Addressing
2.4.3 Instruction Descriptions
Immediate Instructions
2.5.1 General
2.5.2 Immediate Instruction Format
2.5.3 Immediate Instruction Functions
2.5.4 Instruction Descriptions
Conditional Jump Instructions
2.6.1 General
2.6.2 Testable Conditions
2.6.3 Instruction Descriptions
Shift Instructions
2.7.1 General
2.7.2 Single Register Shifts
2.7.3 Double Register Shifts
2.7.4 Shift Instruction Formats
2
.. 7.5 Shift Timing
2.7.6 Instruction Descriptions
Register Change Instructions
2.8.1 General
2.8.2 Instruction Format
2.8.3 Instruction Descriptions
Control Instructions
2.9.1 General
2.9.2 Format
2.9.3 Instruction Descriptions
Page
2-2
2-2
2-2
2-4
2-4
2-4
2-9
2-10
2-19
2-19
2-20
2-24
2-30
2-30
2-30
2·30
2-30
2·33
2-33
2-34
2·36
2-40
2-40
2-40
2-43
2·43
2A3
2-44
2·58
2·58
2·58
2·58
2·66
2·66
2·66
2-67

TABLE OF CONTENTS (Continued)
Section
Page
3.
INPUT /OUTPUT
3-1
3.1
Introduction
3-1
3.1.1 General
3-1
3.1.2 Control Requirements
3-1
3.1.3 Organization 3-2
3.1.4 . Reserved Device Addresses 3-4
3.2 Priority Interrupt System 3-5
3.2.1 General 3-5
3.2.2 Basic Concepts 3-6
3.2.3 Interrupt Processing 3-7
3.2.4 Interrupt Latency 3-12
3.2.5 Interrupt Priorities 3-14
3.2.6 Reserved Interrupt Locations in Memory 3-14
3.3 General
Input/Output Instructions 3-15
3.3.1 General 3-15
3.3.2 Sense Instructions 3-17
3.3.3 Select Instructions 3-18
3.3.4
Input to Register Instructions 3-18
3.3.5
Output from Register Instructions 3-22
3.4 Block Transfer Instructions 3-23
3.4.1 General 3-23
3.4.2 Block Transfer Operation 3-23
3.5 Automatic
Input/Output Instructions 3-26
3.5.1 General 3-26
3.5.2 Format 3-26
3.5.3 Operation 3-27
3.5.4 Direct Memory Channels 3-27
3.5.5 In-Line Programming 3-29
3.5.6 Instruction Descriptions 3-30
4. PROCESSOR OPTIONS
4-1
4.1 Introduction
4-1
4.1.1 General
4-1
4.1.2 Standard Configurations
4-1
4.2 TTY Interface
4-1
4.2.1 General
4-1
4.2.2 Operation
4-1
4.2.3 Data Transfer Rates 4-2
v

Section
4.3
4.4
4.5
4.6
TABLE OF CONTENTS (Continued)
4.2.4 Programming
4.2.5 Reserved Memory Locations
Power Fail/Restart
4.3.1 General
4.3.2 Operation
4.3.3 Interrupt Control
4.3.4 Programming Examples
4.3.5 Reserved Memory Locations
Real-Time Clock
4.4.1 General
4.4.2 Clock Sources
4.4.3 Operation
4.4.4 Control Instructions
4.4.5 Interrupt Locations
Autoload
4.5.1 General
4.5.2 Operating Procedures
4.5.3 Operation
4.5.4 Reserved Memory Locations
~emory Protect
4.6.1 General
4.6.2 Operation
4.6.3 Control Instructions
4.6.4 Reserved Memory Locations
Appendix A HEXIDECIMAL ARITHMETIC
Appendix B: INSTRUCTION SET BY CLASS
Appendix C: LOGICAL FUNCTION DESCRIPTION
Appendix D: INSTRUCTION SET, ALPHABETICAL ORDER
Appendix E: INSTRUCTION SET, NUMERICAL
ORDER
vi
Page
4-2
4-5
4-6
4-6
4-6
4-7
4-7
4-8
4-8
4-8
4-8
4-9
4-9
4-10
4-10
4-10
4-10
4-11
4-11
4-11
4-11
4-11
4-12
4-12
A-I
B-1
C-I
lD-1
E-I

LIST OF ILLUSTRATIONS
Figure
Page
1-1. Evolution
of Compatible 16-Bit Computers
1-2
1-2. Conventional Mini Computer Application
1-3
1-3. NAKED MINI 16 Application
1-3
1-4. ALPHA 16 and NAKED MINI 16 Block Diagram 1-13
1-5. I/O Control and Data Paths 1-17
1-6. Data Word Bit Identification
1-21
1-7. Byte Storage, Two Bytes Per Word 1-24
1-8. Data in Memory, One Byte Per Word 1-26
1-9. Data in Memory, Two Bytes Per Word 1-26
1-10. Basic Word Address Format 1-27
1-11. Byte Address Format 1-27
1-12. Indirect Address Pointer Format 1-28
1-13. ALPHA 16 Control Panel 1-29
2-1. Memory Reference Instruction Format: Word Mode
2-6
2-2. Direct Memory Addressing: Word Mode
2-7
2-3. Indirect Addressing: Word Mode
2-8
2-4. Memory Reference Instruction Format: Byte Mode
2-21
2-5. Direct Memory Addressing: Byte Mode 2-22
2-6. Indirect Addressing: Byte Mode 2-23
2-7. Immediate Instruction Format
2-31
2-8. Conditional Jump Format 2-35
2-9. Logical Right Shift
2-41
2-10. Logical Left Shift
2-41
2-11. Rotate Right 2-41
2-12. Rotate Left 2-41
2-13. Arithmetic Left Shift 2-42
2-14. Arithmetic Right Shift 2-43
2-15. Long Right Shift 2-43
2-16. Long Left Shift 2-43
2-17. Long Rotate Right 2-43
2-18. Long Rotate Left 2-44
2-19. Single Register Shift Format 2-44
2-20. Long Shift Format 2-44
3-1. Computer/Interface/Device Relationships 3-3
3-2. Party Line 110 Structure
3-5
3-3. Single Instruction Interrupt Processing 3-10
3-4. Interrupt Subroutine Processing
3-11
vii

LIST OF ILLUSTRATIONS (Continued)
Figure
3-5. General Input/Output Instruction Format
3-6. Word Movement Sequence
3-7. Byte Movement Sequence
viii
Page
3-17
3-28
3-28

SECTION 1
GENERAL DESCRIPTION
1.1 INTRODUCTION
1.1.1 General
.The ALPHA 16 and NAKED MINI 16 are general purpose,
stored program digital computers. They are extensions
of
the successful and proven 16-bit computer family from
Computer Automation, and are effectively repackaged and
improved versions
of the Model 116 computer.
1.1.1.1 Upward Compatibility. Both the ALPHA 16 and
NAKED MINI
16 are upward software and I/O compatible
with earlier 16-bit computers from Computer Automation.
Figure
1-1 illustrates the evolution of these computers.
Upward software compatibility means that programs
written for the earlier 16-bit computers will run without
change
on the ALPHA 16 or NAKED MINI 16. However,
due
to the expanded and improved instruction set of the
ALPHA
16 and NAKED MINI 16, programs written for
these computers may not run
on the earlier computers.
1.1.1.2 General Features. All
of the 16-bit computers
from Computer Automation feature a 16-bit word format
and' a very powerful and efficient instruction set
of over
145 basic instructions. The ALPHA 16 and NAKED
MINI 16 incorporates all
of the power and flexibility of the
earlier computers plus some new instructions and features
that make these computers a major advance in the mini
computer field. Perhaps the most significant advance
is the
incorporation
of byte processing and byte addressing as
well asfull 16-bit word processing and 16-bit word address-
ing. Since most peripheral devices are byte oriented, this
feature alone improves software efficiency and memory
efficiency tremendously. Software packing and unpacking
of bytes is virtually eliminated. Data may be packed two
bytes
to each word automatically by the computer hard-
ware even when performingblock transfers
of data between
the computer and high speed peripheral devices such
as
magnetic tape or disks.
In addition
to byte processing instructions, additional
instructions have been incorporated in the ALPHA 16 and
NAKED MINI 16
to improve I/O operations, interrupt
control, and processor control.
1.1.2 The NAKED MINI Concept
Within the 16-bit computer family from Computer Auto-
mation, the NAKED MINI 16
is the most revolutionary.
Conventional mini computers have followed the design
concepts
of larger computers in that they have been
designed to work
as stand-alone processors with some peri-
pheral devices attached. Figure
1-2 illustrates a conven-
tional mini computer in a typical application. This figure
shows that the conventional mini computer
is effectively a
separate entity from the system in which it
is used. It has
its own power supply and control panel separate from the
power supply and control panel used
by the remainder of
the system. It treats the remainder of the system as peri-
pherals to the mini computer.
1.1.2.1 System Component. The NAKED MINI 16 is
designed to be a component
of a system rather than a sepa-
rate entity that is connected to the system in which it is
used. Figure
1-3 illustrates a typical NAKED MINI 16
application. The NAKED MINI 16
is designed to be used
as a system component along with other system compo-
nents.
It depends on the system power supply for a source
of power. It depends on the system control panel for con-
trolling signals that may be needed. It is truly a modular
component
of the system in which it is used.
1.1.2.2 System Advantages. Elimination
of a separate
computer power supply and control panel reduces the cost
of the computer component in the system. Elimination of
1-1
II

NAKED - MINITM 16
ALPHA 16
Model 116
Model 216
Figure 1.1. Evolution of Compatible 16-Bit Computers
1-2

CONTROL
PANEL
MINI
COMPUTER
POWER
SUPPLY
~~
!
SYSTEM
DEVICE
All-
SYSTEM
CONTROL
PANEL
'"
SYSTEM
DEVICE
f
~r
~ r
SYSTEM
DEVICE
f
~r
~~
SYSTEM
DEVICE
f
Figure 1-2. Conventional Mini Computer Application
" !
~ ,
SYSTEM
NAKED
DEVICE
MINI16
1 f
Figure 1-3. NAKED MINI 16 Application
SYSTEM
POWER
SUPPLY
SYSTEM
CONTROL
PANEL
SYSTEM
POWER
SUPPLY
,~
~ Ir
SYSTEM
DEVICE
1
1-3

the control panel also reduces the possibility of
inexpedenced operators interfering with system operation
by misuse
of the computer control panel. Since the com-
puter control panel is incorporated in the system control
panel, the need for the computer
to be "front and center"
is eliminated, thus enhancing design and packaging flexibility
for the total system in which the NAKED MINI 16 is used.
1.1.2.3 Module Concept. The name "NAKED MINI 16"
was chosen to emphasize the concept of a computer as a
component
or module which is a fully tested operational
unit. Apply power and the NAKED MINI 16 runs without
a control panel. If external control is needed, a console
connector
is available for connecting the NAKED MINI 16
to a system control panel.
1.1.3 The ALPHA 16
The powerful instruction set and I/O structure
of the
NAKED MINI 16 can be very useful in a stand-alone proc-
essor in the conventional sense. The ALPHA 16 is a conven-
tional mini computer with all of the power of the NAKED
MINI 16.
It is effectively a "dressed" NAKED MINI 16.
It has a dedicated control panel and its own power supply.
In addition, it is mounted in an air cooled chassis.
The ALPHA 16 processor
is identical to the NAKED
MINI 16 processor. Printed circuit boards are interchange-
able between the two machines. The two machines are
identical in every respect, except for the packaging and the
inclusion
of a power supply and a control panel with the
ALPHA 16.
1.1.4 Applications
These computers are designed for commercial, industrial
control, and monitoring applications where emphasis
is on
reliability, flexibility, and economy. Extensive experience
has shown that there
is no limit to the applications of this
16-bit computer family. Some current applications
include:
1-4
• Production test and automation
• EDP source data entry
• Point-of-sale systems
• Scientific and medical instrumentation
1.2 CHARACTERISTICS
1.2.1 General
Detailed characteristics
of the ALPHA 16 and NAKED
MINI 16 are explained in subsequent sections
of this
manual. The following
is an overview of the character-
istics of these computer.
1.2.2 Processor
Some
of the significant characteristics of the computer
processor are:
• Parallel processing of full 16-bit words and 8-bit
bytes
• Seven 16-bit hardware registers
• Memory word size of 16 bits, with each word
addressable
as a full 16-bit word or as two sepa-
rate 8-bit bytes
• Memo.ry capacity is 2,048 words minimum,
expandable
to 32,768 words maximum, with
4,096 words standard
• Computer cycle time is 1.6 microseconds with
memory cycle time included within the computer
cycle time.
• Binary 2's complement arithmetic processing
• Automatic memory scan (standard)
• Hardware Multiply and Divide (standard)

1.2.3 Instruction Set
These computers have a very powerful instruction set
consisting
of 145 basic instructions divided into seven
classes. The instruction classes are:
• Memory Reference
• Immediate
• Conditional Jump
• Shift
These instructions access
memory in either full word or
byte mode and perform
logi-
cal and arithmetic operations
involving data in memory and
data in hardware registers.
These instructions are similar
to memory reference in that
they perform logical and
arithmetic operations involv-
ing memory data and data in
hardware registers. The
memory data, however,
is con-
tained within the instruction
word
so that it is immediately
available for processing with-
out requiring an operand
cycle to fetch it from
memory.
These instructions test condi-
tions within the processor and
perform conditional branches
depending on the results
of
the tests performed. Jumps
may be as much
as ±64 loca-
tions from the location
of the
conditional
jump instruction.
These instructions include
single-register logical shifts,
single-register arithmetic shifts,
single-register rotate shifts,
double-register logical shifts,
and double-register rotate
shifts. The hardware multiply
• Register Change
• Control
• Input/Output
1.2.4 Memory Addressing
and divide instructions are
part
of this class.
These instructions provide
logical manipulation
of data i.
within hardware registers.
These instructions are used to
enable and disable interrupts.
suppress status, control word
or byte mode data processing
and perform other general
control functions.
These are the instructions that
provide communications
between the computer and
external devices. They
include conventional I/O
instruction plus Block Trans-
fer and Automatic Input/
Output instructions.
An important feature of these machines is the ability to
access full 16-bit words and 8-bit bytes (half words) in core
memory. Core memory may be
as small as 2K 16-bit
words, and
as large as 32K 16-bit words. Since memory
may contain 32K words, and since each word contains two
bytes, provisions are made for addressing up
to 64K bytes.
Instructions which access memory may operate in either
word or byte mode. Memory ref,erence instructions are
sixteen bits in length (one-word instructions), with the
eight least-significant bits plus three control bits dedicated
to memory addressing. The eight least significant bits
address 256 words or bytes. The ALPHA 16 and NAKED
MINI 16 computers use the three control bits to specify
several addressing modes. These addressing modes are
dis-
cussed briefly in the following paragraphs, and are
explained in detail in Section
2. The addressing modes
1-5

used are Scratchpad, Relative Forward, Relative backward,
Indexed, and Indirect.
• Scratchpad
• Relative
• Indexed
1-6
Scratchpad addressing uses
the 8-bit address field
of the
memory reference instruction
as the effective memory
address. Scratchpad address-
ing accesses the first 256
words in memory in Word
Mode, or the first 256 bytes
in Byte Mode. The first 256
words in memory are referred
to as "Scratchpad" memory,
because these are common
words which can be addressed
directly by instructions
located anywhere in memory.
Relative addressing uses the
location
of the instruction
which
is addressing memory
as a reference point, and
address memory relative to
that instruction. In Word
Mode, relative addressing can
address an area
of memory
extending from the instruc-
tion address forward 256
words (+256) or backward
255 words (-255). In Byte
Mode, the range
is forward
5
12 bytes. Bytes cannot be
directly addressed relative
backward.
There
is a register in the proc-
essor which can be added to
the address field of memory
reference instructions to form
an effective memory address.
This register
is the Index, or
• Indirect
X, register. The Index
register
is a 16-bit register
which can be set
by software
to any desired value. The
address
of any specific word
(in Word Mode) or byte (in
Byte Mode) may be formed
by adding the address field of
the instruction to the value in
the Index register and using
the result to address memory.
Indirect addressing uses
scratchpad or relative
addressing
to access a word in
memory which contains the
address
of a memory operand.
The word that contains a
memory address rather than
an operand
is called an
Address Pointer. In Word
Mode multi-level indirect
addressing
is possible; i.e.,
one Address Pointer may con-
tain the address
of another
address pointer rather than
the address
of an operand.
In Byte Mode, only one level
of indirect addressing is
possible.
Indirect addressing may also
be used in conjunction with
indexing.
When indexed
indirect addressing
is speci-
fied, the indirect operation
is
performed first and then the
contents
of the X Register
are added to the contents
of
the Address Pointer. This
process
is called Post Indexing.

1.2.5 I/O Structure
The ALPHA 16 and NAKED MINI 16
have a parallel I/O
structure that provides
both ease of interfacing and power-
ful peripheral control. Some special features
of the I/O
Structure are:
• Vectored Interrupts These machines feature
vec-
tored hardware priority inter-
rupts. There are three
standard interrupt lines. The
third, with control lines, can
accommodate a virtually
unlimited number
of vectored
interrupts.
• Direct Memory Channels Direct memory channels
(DMC) provide data transfers
between the computer and
peripheral components with-
out affecting the operating
registers
of the computer.
DMC's are a standard feature
of these computers. The
maximum data transfer rate
using DMC's under interrupt
control
is 238,000 bytes/sec.
• Block Input/Output
• Parallel Busses
The Block I/O feature
of
these computers dedicates the
computer to I/O data transfer
at the maximum possible
transfer rate. The maximum
transfer rate using Block I/O
is 1,000,000 bytes/sec. Block
I/O
is a standard feature of
these computers.
Separate busses providing
device address selection, data
transfer, and control signals
are used for ease of inter-
facing. Busses are not time
shared for I/O functions.
This feature alone simplifies
interface design considerably.
1.2.6 Processor Mounted Options
Processor Mounted Options are those optional features
which are mounted directly on basic processor printed
circuit boards. Since these options are mounted on basic
processor boards, they do not occupy plug-in interface/
option slots within the computer chassis. The processor
mounted options are:
• Teletype Interface
• Power Fail Restart
• Real Time Clock
Interfaces a modified ASR-33
or ASR-35 Teletype to the
computer. This
is a fully-
buffered interface that
includes remote Teletype
power
on/off control.
This option includes the
hardware necessary to detect
low input power conditions,
and bring the computer
to an
orderly halt until normal
input power
is restored.
When normal power
is
restored this option will gen-
erate an orderly restart. The
Power Fail Restart option
allows completely unattended
operation
of the computer at
locations where power con-
ditions are unreliable.
The Real Time Clock option
features a crystal controlled
internal clock which may be
wired to produce clock rates
of 100 microseconds, 1 milli-
second, or 10 milliseconds.
The 10 millisecond rate
is
standard. An external clock
1-7

• ~emoryProtect
• ~ulti-Device Autoload
source, such
as AC line
frequency, may also be used.
The Real Time Clock pro-
vides time-of-day information
to the computer and may be
used
to time periodic events
that must be controlled
by
the computer.
~emory Protect provides a
means for protecting selected
sections
of core memory from
destruction
by program-
generated or I/O-generated
write commands. The segment
to be protected is selected by
jumper wiring. Protect mode
may optionally be enabled
and disabled by software.
The
~ulti-Device Autoload
option consists
of a Read-
Only ~emory (RO~) pro-
grammed with a complete
binary loader which
is
capable of loading binary pro-
grams from
anyone of several
input devices. The Autoload
hardware consists
of the RO~
and the necessary logic to
cause the computer to execute
the program in
RO~ when the
Autoload switch
is activated.
1.2.7 Processor Plug-In Options
Locations are provided within the computer chassis for the
installation
of processor options, peripheral interfaces, and
memory modules. The options are mounted on printed
cir-
cuit boards which plug into the locations within the com-
puter chassis. Some
of the available plug-in processor
options are:
1-8
• DTL I/O buffers, up to 64 bits
• Relay I/O buffers, up to 32 isolated relays
• ~odem interfaces: non-synchronous, synchronous,
parallel, and autodial; multiplexed up to
16 channels
• Direct Memory Access, allowing peripheral access
to memory on a cycle-steal basis at data transfer
rates
of 1,250,000 bytes/sec.
• Read Only ~emory (RO~)
1.2.8 Peripheral Equipment
The following
is a partial list of the various types of peri-
pheral eqUipment for which interfaces
to the ALPHA 16
and NAKED
~INI 16 have been developed. This list does
not imply that these are the only devices for which inter-
faces can be developed. The interface structure
of these
computers
is such that virtually any peripheral device can
be interfaced
to the computer.
• ASR-33 and ASR-35 Teletypewriters
• High speed paper tape readers and punches
• Line printers
• Card readers
• Open reel and cassette magnetic tape units
• Magnetic disks
• A/D and D/A converters
• CRT terminals
1.2.9 Standard Software
The following
is a brief description of the standard software
packages provided with the ALPHA 16 and NAKED
~INI
16 computers. Detailed operating procedures and descrip-
tions
of each program are provided separately.
• BETA BETA
is a symbolic
assembler for translating
free-form source

(symbolic code) tapes into one program. Source code
Object Language tapes which may be typed in, edited, and
can be loaded into the com- assembled using this one pro-
puter and executed. In addi- gram. Source tapes, source
tion to recognizing symbolic listings, Object (assembly)
instruction codes, BETA tapes, and assembly listings
recognizes a full set
of pseudo- are produced by OMEGA.
operation codes. The symbolic ROLL Relocatable Object Language
•
instruction codes recognized . Loader. BETA and OMEGA
by BETA are those codes generate Object Language
listed in the definitions
of the
ALPHA 16 and NAKED tapes. These tapes are not
MINI 16 instructions in sub- binary images
of programs as
sequent sections of this they appear in core memory
when the programs are exe-
manual. cuted. Object Language tapes
• STP Source Tape Preparation. are relocatable; i.e., they may
STP provides a means for pre- be loaded anywhere in
paring and/or editing symbolic memory by
an Object Lan-
source tapes for input
to
guage Loader. ROLL is a
BETA. STP
is used with an sophisticated loader capable
ALPHA 16, a teletype key-
of reading Object language
board, and a paper tape punch. tapes, assigning memory loca-
Source lines are entered tions, linking separate Object
through the keyboard and are language tapes together into
stored temporarily in the one program, and relocating
computer memory where programs in memory. Object
they may be edited before language program tapes pro-
being punched on paper tape. duced
by BETA or OMEGA
Source code may be edited in must be loaded into the
memory, or previously pre- ALPHA 16 or NAKED
pared source tapes may be MINI 16 by ROLL.
read into memory through a BLD/BDP Binary Load/Binary Dump.
•
paper tape reader and edited This program provides a
to produce a corrected source means for loading and dump-
tape. Source listings are also
ing programs in absolute
produced by STP. binary format. The Binary
• OMEGA OMEGA
is a conversational Dump portion of the program
assembler that includes the
is normally used to dump
features
of BETA and STP in binary images of memory in
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a format that may be loaded features assist debugging
using the Binary Load portion operations, and 16 relocation
of the program. Object Lan-
pseudo registers are included
guage programs that have been for accessing subroutines.
loaded into the computer •
MATH 1 Fixed Point Arithmetic Pack-
memory using ROLL may be
age. This package consists of
dumped onto a binary tape twelve Object language pro-
using
BDP. Binary tapes may grams which perform single-
then be loaded into the com-
puter memory in binary for- and double-precision
arithmetic functions.
mat using BLD. BLD/BDP
is
a much shorter program than •
MATH 2 Fixed Point Elementary Func-
ROLL, therefore much tions Package. This package
longer programs can be loaded
is composed of the twelve
with
BLD than with ROLL. most frequently used mathe-
Also, ROLL
is often used to matical functions, organized
link main programs on one into six convenient Object
tape with subroutines on language programs on one
another tape. The total pro- tape. The six programs are:
gram, including main program
and subroutines, may be
1. Square Root: SQRT
dumped
by BDP and subse- 2. Exponential: EXP2,
quently loaded using BLD. EXPE,EXPI
This procedure incorporates
object language programs
on
3. Logarithmic: LOG2,
several tapes into a single LOGE,LOGI
binary image tape. 4. Trignometric: SIN, COS,
• DBUG
Debug Package. DBUG is an TAN
interactive program which aids
the user in debugging his 5. Arctangent: ATAN
programs on the ALPHA 16 6. Hyperbolic Tangent:
or NAKED MINI 16. An TANH
ASR-33 or ASR-35 Teletype
is required by DBUG. DBUG
• TUP Teletype Utility Package.
functions include: transfer TUP consists
of 15 object
control, fill memory, copy programs which perform the
memory, search memory, most common teletype
breakpoint, inspect and/or input/output functions. The
change memory, and modify basic routines input or out-
memory. Register savelchange put a single character, right
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