Computer Automation NAKED MINI LSI Series User manual

10077-00AO
~~3
NAKED MINI LSI/ALPHA LSI
PROGRAMMING REFERENCE MANUAL
~
COMPUTER AUTOMATION, INC.
the NAKED MINI company
18651 Von Korman. Irvine, Calif. 926611
lel.71l1-833-8830 TWX 9JO.59S.I767
COPYRIGHT 1973. COMPUTER AUTOMATION. INC.

Section
~
1.1
1.1.1
1.1.2
1.2
1.3
1.4
1.4.1
1.4.2
1.4.3
1.4.4
1.4.5
1.4.6
1.4.7
1.5
1.5.1
1.5.1.1
1.5.1.2
1.5.1.3
1.5.1.4
1.5.1.5
1.5.2
1.5.2.1
1.5.2.2
1.5.2.3
1.5.2.4
1.5.3
1.5.3.1
1.5.3.2
1.5.3.3
COMPUTER AUTOMATION, INC. ~
TABLE OF CONTENTS
Page
Section 1. GENERAL DESCRIPTION
INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Upward Compatibility .........................•..•..• 1-1
General Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
THE NAKED MINI 16 LSI CONCEPT. ... . ..... ... ...... ...... 1-1
THE ALPHA 16 LSI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
CHARACTERISTICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Processor............................................ 1-2
Instruction Set .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1- 2
Memory Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
I/O Structure......................................... 1-5
Processor Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Plug-In Options .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Peripheral Equipment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
DATA HANDLING CHARACTERISTICS. ..... ................. 1-7
Data Word Format..................................... 1-7
Bit Identification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
Bit Values '0' • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 1-8
Signed Numbers. . . . . . . • . . . ... . . . . . . . . . . . . . . . . . . . . . 1-8
Positive Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1- 8
Negative Numbers.................... ............ 1-8
Data Byte Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1- 9
Byte Mode Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
Register Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
Arithmetic Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 .... 10
Data Packing .......................... t.. • • • • • • • • • 1-10
Memory Address Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
Word Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
Byte Addressing. . . . . . . . . . . . . . . . . . . . . . . • . . . • . . . . . . 1-12
Indirect Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
iii

~
Section
2.1
2.2
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.4
2.4.1
2.4.2
2.4.3
2.4.4
2.5
3.1
3.1.1
3.1.2
3.1.3
3.1.3.1
3.1.3.2
3.1.3.3
3.1.3.4
3.1.4
3.1.5
3.2
3.2.1
3.2.1.1
3.2.1.2
3.2.1.3
COMPUTER AUTOMATION, INC. ~
TABLE OF CONTENTS (Cont'd)
Page
Section 2. CONSOLE
INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
SWITCHES AND INDICATORS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
MACHINE MODES. . . . . . . . . . . . . . . . . . . • . . . •. . • • . . . . . . . . . . . . . . 2- 6
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . •. . . •••• •• 2-6
Step Mode. . . . . . . . . . . . . . . . . . . . . . . . •. . . . . . . . . •. • . • . •. •. 2-7
Run Enable Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . •. . . . . . . 2-7
Run Mode............................................. 2-7
CONSOLE OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
Console Preparation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
Console Data Entry Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . 2- 8
Console Display Procedure. , . . . . . . ••. . . . . . . •. . . . . . . . . . . 2- 9
Program Execution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
UNATTENDED OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
Section 3. INSTRUCTIONS AND DIRECTIVES
INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Instruction and Directive Classes. . . . . . . . . . . . . . . . . . •. . . . 3-1
Symbolic Notation ...... , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Assembler Source Statement Fields. . . . . . . . . . . . . . . . . . . . . 3-2
Label Field. . . . . . . . • •••. •. . •. •. •. . . . . . . . . . . . . . . . . . 3- 2
Op Code Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3- 2
Operand Field .......................... '. . •. . . . . . .. 3- 3
Comments Field. . . . . . . . . . . . . . . . . . . . . . . •. . . . . . . . . . . 3-4
Arithmetic Operations and Overflow. . . . . . . . . . . . . . . . . . . . 3-4
Relocatability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3- 5
MEMORY REFERENCE INSTRUCTIONS. . . . . . . . . . . . . . . . . . . . . .. 3-6
Word Mode Operations and Instruction Format. . . . . . . . . . . 3- 6
Word Mode Direct Addressing. . . . . . . . . . . . . . . . . . . . . . 3-6
Word Mode Indirect Addressing. . . . . . . . . . . . . . . . . . . . 3-7
Word Mode Direct Indexed Addressing. . . . . . . . . . . . . . 3-7
iv

Section
3.2.1.4
3.2.1.5
3.2.2
3.2.2.1
3.2.2.2
3.2.2.3
3.2.2.4
3.2.2.5
3.2.3
3.2.4
3.2.5
3.2.6
3.3
3.3.1
3.3.2
3.4
3.4.1
3.4.2
3.5
3.5.1
3.5.2
3.5.3
3.5.4
3.6
3.6.1
3.6.2
3.6.3
3.6.4
3.6.5
3.6.6
3.7
3.7.1
3.7.2
3.7.3
COMPUTER AUTOMATION,INC. ~.
TABLE OF CONTENTS (Cont'd)
Section 3. INSTRUCTIONS AND DIRECTIVES (Cont'd)
Word Mode Indirect Post-Indexed Addressing ....•...
Word Mode Summary ..........•.....•..............
Byte Mode Operations and Instruction Format ........... .
Byte Mode Direct Addressing ...•...................
Byte Mode Indirect Addressing .......•..•....•.....
Byte Mode Direct Indexed Addressing .............. .
Byte Mode Indirect Post-Indexed Addressing ....... .
Byte Mode Summary ............................... .
Arithmetic Memory Reference Instructions .............. .
Logical Memory Reference Instructions ......•...........
Data Transfer Memory Reference Instructions ........... .
Program Transfer Memory Reference Instructions ••••••.•
DOUBLE-WORD MEMORY REFERENCE INSTRUCTIONS .....••.
Format .............................................. .
Instructions .......................................... .
IMMEDIATE INSTRUCTIONS .....•.....•........•.......•...
Format ............................................... .
Instructions .......................................... .
CONDITIONAL JUMP INSTRUCTIONS ....................•...
Format ............................................... .
Microcoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Arithmetic Conditional Jump Instructions .............•..
Control Conditional Jump Instructions .................. .
SHIFT INSTRUCTIONS .................••....... ' ........... .
Operand Restrictions and Instruction Format .......•.•...
Arithmetic Shift Instructions ......•.•.........•.........
Logical Shift Instructions .........•.•••..•.•..•.•..••...
Rotate S hilt Instructions ............................... .
Double Register (Long) Rotate Shift Instructions ....•....
Double Register (Long) Shift Instructions •...............
REGISTER CHANGE INSTRUCTIONS ........... It ••••••••••••
Format ............................................... .
A Register Change Instructions ........................ .
X
Register Change Instructions ...............•.........
v
Page
3-7
3-8
3-8
3-9
3-9
3-10
3-10
3-10
3-10
3-11
3-12
3-12
3-14
3-14
3-14
3-17
3-17
3-17
3-18
3-18
3-18
3-20
3-20
3-21
3-21
3-21
3-22
3-23
3-24
3-24
3-25
3-25
3-25
3-26

Section
3.7.4
3.7.5
3.7.6
3.8
3.8.1
3.8.2
3.8.3
3.8.4
3.8.5
v3.9
3.9.1
3.9.1.1
3.9.1.2
3.9.2
3.9.2.1
3.9.2.2
3.9.3
3.9.3.1
3.9.3.2
3.9.4
L
L-
3.9.5
3.10
3.10.1
3.10.2
3.11
3.11.1
3.11.2
3.12
3.12.1
3.12.2
3.13
3.14
3.15
COMPUTER AUTOMATION,INC. ~
TABLE OF .CONTENTS, (Cont'd)
Page
OV Register Change Instructions. . . . . . . . . . . . . . . . . . . . . . . 3- 26
Multi-Register Change Instructions ....... 0 ••• 0 •• 0 • • • • • • 3-26
Console Register Instructions. . . . . . . . . . . . • . . . . • . . . . . . . . 3-28
CONTROL INSTRUCTIONS ...... 0 ••••••••••••••••••• 0 0 • • • • • • 3-28
Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3- 28
Processor Control Instructions. . . . . . . . . . • . . . . . . . . . . . . . .. 3-r29
Mode Control Instructions 0 0 0 ••• 0 •• 0 0 • 0 •••• 0 ••• 0 •••• 0 ••••. 3" 29
Status Control Instructions. . . . . . . . . . . . . . . . •. . . . . . . . . . . . 3-29
Interrupt Control Instruction ........... 0 •••••• 0 • • • • • • • • 3- 30
INPUT /OUTPUT INSTRUCTIONS ....................... 0 ... 0 3-31
Control Input/Output Instructions. 0 •••••••••••• 0 0 •••• 0 0 3- 32
Sense Instructions 0 0 ••••• 0 •••••• 0 ••••••••• 0 •• 0 •• 0 • 3- 32
Select Instructions .. 0 • 0 • 0 •• 0 ••••••••• 0 ••••• 0 • 0 • • • • 3-32
Word Input/Output Instructions ................... 0 • • • • 3-33
Unconditional Word Input/Output Instructions. 0 •• 0 • 0 3-33
Conditional Word Input/Output Instructions. . . . . . . . . 3- 34
Byte Input Instructions. 0 •••••• 0 0 0 • 0 • • • • • • • • • • • • • • • • • • • 3- 35
Unconditional Byte Input Instructions. . . . •. . . . . . . . . . 3-35
Conditional Byte Input Instructions 0 ••••••••••••• 0 • • 3-35'
Block Input/Output Instructions ........ 0 • • • • • • • • • • • • • • • 3-36
Automatic Input/Output Instructions .............. 0 • • • • • 3-38
ASSEMBLER CONTROL DIRECTIVES. . . . . . . . . . . . . . . . . . . . . . . . 3-41
Conditional Assembly Controls. . . . . . . . . . . . . . . . . . . . . . . . . 3- 41
Program Location Controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3- 42
DATA AND SYMBOL DEFINITION DIRECTIVES. . . . . . . . . . . . . . . 3-43
Formats .................................... ' . . . . . . . . . . 3- 43
Directives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43
PROGRAM LINKAGE DIRECTIVES. . . . . . . . . . . . . . . . . . . . . . . . . . . 3-44
Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-44
Directives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-45
SUBROUTINE DEFINITION DIRECTIVES. . . . . . . . . . . . . . . . . . . . . 3-45
LISTING FORMAT AND ASSEMBLER INPUT CONTROLS. . . . . . . 3-46
USER-DEFINED OPERATION CODE DIRECTIVE.... ... ... ... .. 3-47
vi

Section
4.1
4.1.1
4.1.1.1
4.1.1.2
4.1.1.3
4.1.2
4.1.2.1
4.1.2.2
4.1.2.3
4.2
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.3
4.3.1
4.3.2
4.3.3
4.4
4.4.1
4.4.2
5.1
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.2
5.2.1
5.2.2
COMPUTER AUTOMATION. INC. ~
TABLE OF CONTENTS (Cont'd)
t/ Section 4. INPUT/OUTPUT AND INTERRUPT OPERATION
INTRODUCTION
.......................................... .
Discussion of Input/Output Operations ...•.......•......
Control .......................................... .
Sense ........................................... .
Data Transmission .......•.••..••••••.••.•••••.••••
Interrupt Operations ..........•........................
Non-Input/Output ................................ .
Input/Output ..................................... .
Word and Block Interrupts .......................•.
NON-INTERRUPT INPUT /OUTPUT EXAMPLES ............... .
Control Instructions ........•...........•...........•..
Unconditional Instructions ............................ .
Conditional Instructions ...................•...........
Block Transfer Instructions ........................... .
Automatic Transfer Instructions ...•....................
Page
4-1
4-1
4-1
4-2
4-2
4-5
4-5
4-6
4-6
4-6
4-9
4-9
4-10
4-10
4-11
INTERRUPT STRUCTURE EXAMPLES. . . . . . . . . . . . . . . . . . . . . • . . 4-11
General Interrupt Handling. . . . . . . . . . . . . • . . . . . . . . . . . . . .. 4-11
Examples of Initialization and Enabling Sequences. . . . . . .. 4-12
Examples of Interrupt Instructions. . . . . . . . . . . . . . . . . . . . . . 4-13
INTERRUPT LATENCY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
Interrupt Service. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
Priority Resolution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
Section 5. PROCESSOR OPTIONS
TELETYPE. . . . . . . . . . . . . . . . . •. . . . . . . . . . . . . . . . • . . . . . . . . . . . . . 5-1
General Discussion .......... '. . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Half- Duplex Usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Table of Half-Duplex Teletype Instructions. • . . . . . . . . . . . . 5-3
Full- Duplex Usage. • . • • •• • • • • . • • • •• • • • •• • •• • • • •• • • • • •. 5- 6
Table of Full-Duplex Teletype Instructions. . . . .. . . . . . . . 5-8
REAL-TIME CLOCK. . . . . . . . . . . • . . • . . •• •. . . . . . . . • . . . . . . . . . . . 5-11
Discussion of Usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Summary Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
vii

COMPUTER AUTOMATION,INC. ~
TABLE OF CONTENTS (Cont'd)
Section
Page
5.3 AUTOLOAD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
5.4 POWER FAIL/RESTART. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
5.4.1 General.............................................. 5-14
5.4.2 Power Fail........................................... 5-14
5.4.3 Restart.............................................. 5-14
5.4.4 Interrupt Control Option. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
5. 4. 5 Programming Examples. . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . 5-15
Appendix A. HEXADECIMAL TABLES
Appendix B. RECOMMENDED DEVICE AND INTERRUPT ADDRESSES
F .1
F .2
F.3
F .3.1
F .3.2
F.3.3
F.3.4
F.3.5
F.3.S
F.3.7
F.3.8
F.3.9
F.3.10
F. 3.11
Appendix C. INSTRUCTION SET IN ALPHABETICAL ORDER
Appendix D. INSTRUCTION SET IN NUMBERICAL ORDER
Appendix E. ALPHA LSI EXECUTION TIMES
Appendix F. SOFTWARE SUMMARY
INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . .
F-l
BOOTSTRAP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . F-2
SOFTWARE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . •. . . F-2
Autoload. . . . . . . . . . . . . . . . . . •. . . . . . . . . . . . . . . . . . . . . . . . . . F- 2
Binary Load (BLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F-3
Binary Dump IV erify (BDP lVER) . . . . . . . • . . . . . . . . . . . . . . F- 3
Object Load ......................................... F-4
BETA-4Assembler... ........ ............ ............ F-4
BETA- 8 Assembler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F- 4
OMEGA Conversational Assembler. . . . . . . . . . . . . . . . . . . . . F-5
Source Tape Preparation Program. . . . . . . . . . . . . . . • . •. . . F-S
Debug (DBG). . . . . . . . . . . . . . . . . . . • . • . . . . . . . . . . . . . . . . . . . F-7
Concordance (CONe)....... . . . . . . . . . . . . . . . . . . . . . . . . . . F-8
OS Command Summary. . . . . . . . •. . . . . . . . . . . . . . . . . . . . . . . F-8
viii

Figure
1-1
1-2
1-3
1-4
1-5
1-6
1-7
2-1
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
3-17
3-18
3-19
3-20
3-21
3-22
3-23
3-24
3-25
3-26
3-27
3-28
3-29
3-30
3-31
3-32
3-33
3-34
COMPUTER AUTOMATION,INC. ~
LIST OF ILLUSTRATIONS
Data Word Bit Identification .................................. .
Byte Storage, Two Bytes Per Word ........................... .
Data in Memory, One Byte Per Word .......................... .
Data in Memory, Two Bytes Per Word ......................... .
Basic Word Address Format .................................. .
Byte Address Format ........................................ .
Indirect Address Pointer Format ............................. .
ALPHA 16
LSI Console ........................ " ............... .
Instruction and Directive Classes ............................ .
Source Statement Format .................................... .
Arithmetic Overflow ........................................ .
Word Mode Memory Reference Instruction Format ............. .
Word Mode Addressing Summary ............................ .
Byte Mode Memory Reference Instruction Format .............. .
Byte Mode Addressing Summary ............................. .
Double Word Memory Reference Format. ...................... .
Divide ..................................................... .
Multiply and Add ........................................... .
NRM Shift Path ............................................. .
Immediate Instruction Format ................................ .
JOC Jump On Condition Format .............................. .
JOC Microcode Bit Functions ................................ .
Conditional Jump Format .................................... .
Single Register Shift Format. ................................ .
Double Register (Long) Shift Format. ........................ .
Arithmetic Right Shift ....................................... .
Arithmetic Left Shift ......................................... .
Logical Right Shift .......................................... .
Logical Left Shift ............................................ .
Rotate Right ................................................ .
Rotate Left .................................................... .
Long Left Shift .............................................. .
Long Right Shift ............................................ .
Long Rotate Right ........................................... .
Long Rotate Left ............................................. .
Register Change Format ...................................... .
Control Format .............................................. .
Computer Status Word Format ................................. .
Single Word Input/Output Instruction Format ................... .
Block Input/Output Instruction Format ......................... .
Automatic Input/Output Instruction Format ..................... .
In-line Auto I/O Instruction Sequence .......................... .
ix
Page
1-9
1-9
1-11
1-12
1-13
1-13
1-13
2-3
3-1
3-2
3-5
3-6
3-8
3-9
3-11
3-14
3-15
3-16
3-16
3-17
3-18
3-19
3-19
3-21
3-21
3-21
3-21
3-22
3-22
3-23
3-23
3-24
3-24
3-24
3-24
3-25
3-28
3-29
3-31
3-37
3-38
3-39

Figure
3-35
3-36
3-37
3-38
3-39
3-40
3-41
3-42
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
5-1
5-2
5-3
5-4
C.l
C.2
C.3
C.4
C.5
C.6
C.7
C.8
D.l
D.2
D.3
D.4
D.5
D.6
D.7
D.8
D.9
D.lO
D.11
COMPUTER AUTOMATION,INC. ~
LIST OF ILLUSTRATIONS (Cont'd)
Interrupt Location Auto I/O Instruction Sequence .............. .
Begin Conditional Assembly Directives Format ................. .
End Conditional Assembly Directive Format .................... .
Location
Control Directive Format ............................. .
Data
and Symbol Definition Directive Format ................... .
Program Linkage Directive Formats ........................... .
Subroutine Definition Directive Formats ....................... .
Title Directive Format ....................................... .
Initialization and Unconditional Output to Line Printer .......... .
Unconditional Character Read from Teletype Paper Tape Reader ..
Initialization and Conditional Control of Line Printer ............ .
Conditional
Input from Teletype Keyboard with Auto-Echo ....... .
Uninterruptable Block Output to Line Printer ................... .
Automatic Byte
Input from Card Reader ........................ .
Line
Printer Interrupt Initialization Sequence .................. .
Real-Time Clock
Interrupt Initialization Sequence .............. .
Line
Printer Interrupt Instructions ............ ; ............... .
Real-Time Clock
Interrupt Instructions ........................ .
Standard Interrupt Priorities .................................. .
Program-Controlled Data Output to Half-Duplex Teletype ........ .
Program-Controlled Data Input from TTY Paper Tape Reader .... .
Program-Controlled Data Input from Full-Duplex Teletype ....... .
Automatic
Interrupt Data Input from Full-Duplex Teletype ....... .
Class 1 - Single-Word Memory Reference Instruction Format ..... .
Class 2 - Double.i:Word Memory Reference Instruction Format ..... .
Class 3 - Byte Immediate Instruction Format .................... .
Class 4 - Conditional Jump Instruction Format .................. .
Class 5 - Register Shift Instruction Format ..................... .
Class 6 - Nonvariable Instruction Format ....................... .
Class 7 - Input/Output Instruction Format ...................... .
Class 8 - JOC Jump-On-Condition Instruction Format ............ .
Single-Word Memory Reference Instruction Machine Code Format..
Double-Word Memory Reference Instruction Machine Code Format ..
Byte Immediate Instruction Machine Code Format ................ .
Conditional
Jump Instruction Machine Code Format .............. .
Single-Register Shift Instruction Machine Code Format .......... .
Double- Register Shift Instruction Machine Code Format .......... .
Register Change Instruction Machine Code Format .............. .
Control Instruction Machine Code Format ....................... .
Input/Output Instruction Machine Code Format .................. .
Automatic
Input/Output Instruction Machine Code Format ........ .
Block
Input/Output Instruction Machine Code Format ............ .
x
Page
3-40
3-41
3-41
3-42
3-43
3-44
3-45
3-46
4-6
4-7
4-7
4-8
4-8
4-9
4-12
4-13
4-13
4-14
4-16
5-2
5-2
5-6
5-7
C-1
C-1
C-1
C-2
C-2
C-2
C-2
C-2
D-1
D-1
D-2
D-2
D-3
D-3
D-3
D-3
D-4
D-4
D-4

COMPUTER AUTOMATION, INC. f3!:1
LIST OF TABLES
Table
Page
2-1 Console Switches and Indicators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
A-1 Hexadecimal-Decimal Conversions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2
A-2 ASCII Teletype Codes ............. I I I I I I I I • I ••• I I • I I I I I I I II I I I I A-3
B-1 Recommended Device Addresses ... I •• I •••••• I • I •••••• I •••••• I • I B-2
B-2 Scratchpad/Page 0 Recommended Interrupt Address Map I I ••• I • I I B-3
E-1 Standard Core Memory Algorithm Variables .... I ••••••••••••••••• E-1
E-2 Execution Time Algorithms ................ I • I I I • I I I • I •• I • I I • • •• E-2
F-1 Assembler Directives ............ I •••••••••• I •• I ••••• I •••• I • • • • F-1
xi

COMPUTER AUTOMATION, INC. ~
Section 1
GENERAL DESCRIPTION
1.1 INTRODUCTION
The ALPHA 16 LSI and NAKED MINI 16 LSI (hereafter referred to as ALPHA LSI when
discussed together) are general purpose, stored program digital computers. They are
extensions of the successful and proven 16-bit computer family from Computer Automation.
1.1.1 Upward Compatibility
The ALPHA LSI is upward software and I/O compatible with earlier 16-bit computers
from Computer Automation. Upward software compatibility means that virtually all
programs written for the earlier 16-bit computers will run without change on the
ALPHA LSI .. However, due to the expanded and improved instruction set of the
ALPHA LSI, programs written for these computers may not run on the earlier computers.
1.1.2 General Features
The ALPHA LSI computer features a 16-bit word format and 162 basic instructions. The
instruction set is divided into seven major classes which provide memory-to-register
and register-to-register data movement as well as conditional jump, single and double-
register shift, register change, machine control and Input/Output instructions. The
computer utilizes eight addressing modes for effective and efficient management of
memory resources.
The ALPHA LSI computer has a fully buffered I/O structure coupled with five levels of
interrupts and five I/O modes which permit high speed, low speed, synchronous and
asynchronous data transfers to take place.
The ALPHA LSI may readily accommodate additional memory and I/O by adding expansion
chassis to the basic system .An optional Memory Banking feature permits the user to
extend the upper limit of memory from 32K words to 256K words.
1.2 THE NAKED MINI 16 LSI CONCEPT
The NAKED MINI 16 LSI computer consists of the Processor and first memory module
on one printed circuit board. The NAKED MINI 16 LSI is a complete stand alone
computer without a chassis, motherboard, power supply or operators console.
1-1

COMPUTER AUTOMATION,INC. ~
The NAKED MINI 16 LSI computer is designed to be used as a system component along
with other system components. It depends on the system power supply for a power
source, the system control panel for operational control signals and the system en-
closure for structural and environmental support.
1.3 THE ALPHA 16 LSI
Take a NAKED MINI 16 LSI computer and add a power supply module, a motherboard,
a chassis and an operator's console and you get the ALPHA 16 LSI computer. The
Motherboard interconnects the NAKED MINI 16 LSI computer with additional I/O and
memory modules, the power supply and the operator's console.
1.4 CHARACTERISTICS
The characteristics of the ALPHA LSI are explained in subsequent sections of this manual.
The following is an overview of the characteristics of this computer.
1.4.1 Processor
Some of the significant characteristics of the computer are:
Parallel processing of full 16-bit words and 8-bit bytes
Seven 16-bit hardware registers, one 8-bit Status Register
Memory word size of 16 bits, with each word addressable as a full 16-bit
word or as two separate 8- bit bytes.
Memory capacity is 1,024 words minimum, expandable to 32,768 words per
bank maximum (Up to 262,144 words with optional memory banking.)
Computer cycle time is 1. 6 microseconds
Direct Memory access (Standard) provides data transfer rates of 625,000
words per second in a single memory bank or 1,250,000 words per second
with inter leaved memory banks
Binary 2's complement arithmetic processing
Automatic memory scan (standard)
Hardware Multiply and Divide (standard)
1-2

COMPUTER AUTOMATION, INC. ~
1.4.2 Instruction Set
These computers have a very powerful instruction set consisting of 162 basic instructions
divided into seven classes. The instruction classes are:
1. Memory Reference.
Access memory in either full word or byte mode and perform logical and arith-
metic operations involving data in memory and data in hardware registers. The
hardware multiply, divide and normalize instructions are included in this class.
2. Byte Immediate
Similar to memory reference in that they perform logical and arithmetic operations
involving data in hardware registers. The memory data, however, is contained
within the instruction word so that it is immediately available for processing
without requiring an operand cycle to fetch it from memory.
3. Conditional Jump.
Test conditions within the processor and perform conditional branches depending
on the results of the tests performed. Jumps may be as much as ::!:. 64 locations
from the location of the conditional jump instruction.
4. Shift.
Include single-register logical, arithmetic and rotate shifts; double-register
logical and rotate shifts.
5. Register Change.
Provide logical manipulation of data within hardware registers.
6. Control.
Enable and disable interrupts; suppress status, control word or byte mode data
processing and perform other general control functions.
7. Input/Output.
Provide communications between the computer and external devices. They
include conventional I/O instructions plus Block Transfer and Automatic
Input/Output instructions. I/O may be to/from register or directly to/from
memory.
1-3

COMPUT£R AUTOMATION, INC. f3]1
1.4. 3 Memory Addressing
An important feature of these machines is the ability to access full 16-bit words and 8-bit
bytes (half words) in memory. Memory may be as small as lK x 16-bit words, and as
large as 32K x 16-bit words. Since memory may contain 32K words, and since each
word contains two bytes, provisions are made for addressing up to 64K bytes.
Instructions which access memory may operate in either word or byte mode. Memory
reference instructions are sixteen bits in length (one-word instructions) , with the eight
least-significant bits plus three control bits dedicated to memory addressing. The eight
least significant bits address 256 words or bytes. The ALPHA LSI computer uses the
three control bits to specify several addressing modes. These addressing modes are
discussed briefly below and are explained in detail in Section 3. The addressing modes
used are Scratchpad, Relative Forward, Relative Backward, Indexed, and Indirect.
1. Scratchpad
Scratchpad addressing accesses the first 256 words in memory in Word Mode, or
the first 256 bytes in Byte Mode. The first 256 words in memory are referred to
as "Scratchpad" memory, because these are common words which can be addressed
directly by instructions located anywhere in memory.
2. Relative
In Word Mode, relative addressing can address an area of memory extending
from the instruction address forward 256 words (+256) or backward 255 words
(-255). In Byte Mode, the range is forward 512 bytes. Bytes cannot be directly
addressed relative backward.
3. Indexed
The Index register (X register) can be added to the address field of memory refer-
ence instructions to form an effective memory word or byte address.
4. Indirect
Indirect addressing uses scratchpad or relative addressing to access a word in
memory which contains the address of a memory operand. The word that contains
a memory address rather than an operand is called an address pointer. In l.vord
Mode, multi-level indirect addressing is possible; i.e., one address pointer may
contain the address of another address pointer rather than the address of an
operand. In Byte Mode, only one level of indirect addressing is possible.
Indirect addressing may also be used in conjunction with indexing. When indexed
indirect addressing is specified, the indirect operation is performed first and then
the contents of the X register are added to the contents of the address pointer. This
process is called Post Indexing.
1-4

COMPUTER AUTOMATION,INC. ~
1.4.4 I/O Structure
The ALPHA LSI computer has a parallel I/O structure that provides both ease of inter-
facing and powerful peripheral control. Some special features of the I/O Structure are:
1. Vectored Interrupts.
These machines feature vectored hardware priority interrupts. Wherein each
peripheral controller supplies its own unique interrupt address to any location
in memory. There are five standard interrupt levels (two internal and three
external). The third external level with control lines can accommodate a vir-
tually unlimited number of vectored interrupts.
2. Direct Memory Channels.
Direct memory channels (DMC) provide data transfers between the computer and
peripheral components without affecting the operating registers of the computer.
DMC's are a standard feature of these computers. The maximum data transfer
rate using DMC's under interrupt control is 26,738 words/ sec.
3. Block Input/Output.
The Block I/O feature of these computers dedicates the computer to I/O data trans-
fer at the maximum possible transfer rate. The maximum transfer rate using Block
I/O is 131,579 words/ sec. Block I/O is a standard feature of these computers.
4. Parallel Busses
Separate busses providing device address selection, data transfer, and control
signals are used for ease of interfacing. Busses are not time shared for I/O
functions. This feature alone simplifies interface design considerably.
1.4. 5 Processor Options
There are four general options that are offered with the ALPHA LSI computer. They
are: Power Fail/Restart; the Teletype/CRT Interface; Real-time Clock, and Autoload.
The Power Fail/Restart option mounts directly on the NAKED MINI 16 LSI computer
printed circuit board. The other three options mount on a special option board which
plugs into a special connector (in piggyback fashion) on the NAKED MINI 16 LSI
computer printed circuit board. None of these options interface directly with the
motherboard.
1-5

COMPUTER AUTOMATION,INC. ~
1. Teletype/CRT Interface
Interfaces a modified ASR-33 or ASR-35 Teletype or CRT terminal to the computer.
This is a fully-buffered interface that includes remote Teletype motor on/off con-
trol. In addition to the standard TTY baud rate (110 baud) , nine user selectable
baud rates, ranging from 75 to 9600 bauds, are provided for driving a CRT
terminal.
2. Power Fail Restart
This option includes the hardware necessary to detect low input power conditions
and bring the computer to an orderly halt until normal input power is restored.
When normal power is restored, this option will generate an orderly restart. The
Power Fail Restart option allows completely unattended operation of the computer
at locations where power conditions are unreliable.
3 . Real Time Clock
The Real Time Clock option features a crystal controlled internal clock which may
be wired to produce clock rates of 100 microseconds, 1 millisecond, 10 milliseconds,
or twice the input AC line frequency (8.33 or 10 milliseconds -60Hz and 50Hz,
respectively). The 10 millisecond (crystal derived) rate is standard. An
external clock source may also be used. The Real Time Clock provides
time-of-day information to the computer and may be used to time periodic
events that must be controlled by the computer.
4. Multi-Device Autoload
The Multi-Device Autoload option consists of a Read-Only Memory (ROM) pro-
grammed with a complete binary loader which is capable of loading binary programs
from anyone of several input devices. The Autoload hardware consists of the
ROM when the LOAD switch is activated.
1. 4 . 6 PI ug- In Options
Locations are provided within the ALPHA 16 LSI computer chassis for the installation
of processor options, peripheral interfaces, and memory modules. The options are
mounted on printed circuit boards which plug into the locations within the computer
chassis. Some of the available plug-in processor options are:
1. DTL I/O buffers, up to 64 bits
2. Relay I/O buffers, up to 32 isolated relays
3 . Modem interfaces: non-synchronous and synchronous
4. Memory Banking Controller, extends upper limit of memory to 262,144 words.
5. Read Only Memory (ROM)
1-6

COMPlmR AUTOMATION,INC. ~
1.4.7 Peripheral Equipment
The following is a partial list of the various types of peripheral equipment for which
interfaces to the ALPHA LSI have been developed. This list does not imply that these
are the only devices for which interfaces can be developed. The interface structure of
these computers is such that virtually any peripheral device can be interfaced to the
computer.
1. ASR-33 and ASR-35 Teletypewriters
2. High speed paper tape readers and punches
3. Line printers
4. Card readers
5. Open reel and cassette magnetic tape units
6. Magnetic disks
7. AID and D/A converters
8. CRT terminals
9. Plotters
1.5 DATA HANDLING CHARACTERISTICS
1. 5. 1 Data Word Format
Processor registers and memory word locations are capable of storing data words con-
sisting of 16 binary digits or "bits". A word may be handled as a single 16-bit field
or as two 8-bit bytes. The following paragraphs describe the word format of the
computer. Byte format is described later in this section. I
1.5.1.1 Bit Identification
A data word may contain a single number, or it may contain a string of individual binary
bits, with each bit having a unique meaning. For purposes of explanation and identifica-
tion, each bit within a word is uniquely identified. The identification is accomplished
by numbering each bit within a word from right to left. The bit on the extreme right
of the word is bit 0, and the bit on the extreme left is bit 15. Figure 1-1 illustrates the
format of a 16-bit data word with the bit number shown above the bit position.
1-7

COMPUTER AUTOMATION,INC. ~
1.5.1.2 Bit Values
The ALPHA LSI is a binary computer, therefore numeric information stored in the com-
puter and processed by the computer must be in binary format. Figure 1-1 illustrates
the binary value of a one-bit in each bit position of the 16-bit data word. These values
are expressed as powers of two. For example, a one-bit in bit position 3 has the value
of 23 , or 8. The single exception to this rule is bit position 15 which is the sign bit.
1.5.1.3 Signed Numbers
The ALPHA LSI is capable of performing arithmetic operations with signed numbers. Bi-
nary two's complement notation is used to represent and process numeric information.
Bit 15 of a data word indicates the algebraic sign of the number contained within that
word.
1.5.1.4 Positive Numbers
A positive number is identified by a 0 in bit 15, and the binary equivalent of the magni-
tude of the positive number is stored in bits 0 to 14. The largest positive signed number
which can be stored in a 16-bit word is +32,76710.
1.5.1.5 Negative Numbers
A negative number is identified by a 1 in bit 15 of the data word. A negative number is
represented by the binary two's complement of the equivalent positive number. A neg-
ative number must follow the mathematical rule where:
0- (+n) = -n
For example:
o- (+5) = -5
Negative numbers must also be constructed such that:
(+n) +
(-n) =0
The binary two's complement of some numeric value may be constructed by subtracting
the binary representation of the absolute magnitude of that value from O.
Note that the formation of a binary two's complement negative number from the equivalent
positive number automatically sets the sign bit to a one. The largest negative number
that can be stored in a 16-bit word is -32,768
10
.
1-8

COMPUTER AUTOMATlON,INC, ~
1.5.2 Data Byte Format
A 16- bit data word is capable of storing two 8- bit bytes. Since most data transfers be-
tween mini computers and peripheral devices are in the form of bytes rather than words,
the ALPHA LSI computer provides the capability of addressing individual bytes as well
as full data words. Figure 1- 2 illustrates the storage of two bytes within one computer
word.
Bit positions within bytes are identified much the same as in 16-bit words. Figure 1-2
also illustrates the numbering of data bits within a byte. The bits are numbered 0
through 7, where bit 0 is the least-significant bit (LSB) , and bit 7 is the most-signi-
ficant bit (MSB) of the byte.
1& 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Figure 1-1. Data Word Bit Identification
16· BIT WORD
...
f 15 14
13 12 11
10 9 8 7 6 5 4 3 2 1 0 "
BYTE 0
7 II & 4 3 2 1 0
\,.
I
...
8· BIT BYTE
BYTE 1
7 II I 4 3 2 1
\,.
""
8· BIT BYTE
o
I
Figure 1-2. Byte Storage, Two Bytes Per Word
1-9

COMPUTER AUTOMATION,INC. ~
1. 5.2.1 Byte Mode Processing
There are two control instructions in the computer which control Word Mode processing
and Byte Mode processing. One of the instructions causes the computer to enter Byte
Mode processing, and the other causes the computer to enter Word Mode.
In Word Mode, all memory reference instructions access full words in memory. In Byte
Mode all memory reference instructions (except IMS, MPY, DIV, NRM, JMP, and JST)
access one byte within a word. The method of addressing individual bytes is discussed
in a subsequent part of this Section. The present discussion is concerned with computer
operations while in Byte Mode as contrasted with computer operations in Word Mode.
Byte Mode affects the operand cycle of the computer only. All other computer functions
operate the same as in Word Mode. In Byte Mode the computer operand cycle reads a
single byte from memory instead of a full word. The following paragraphs illustrate
Byte Mode operations for memory reference instructions.
1.5.2•2 Register Load
In Word Mode, the full word is loaded into the selected register. In Byte Mode, the
selected byte is loaded into the lower eight bits of the selected register and the upper
eight bits are set to zero. Note that the location of the byte within the memory word
does not determine the location the byte will occupy in the register being loaded.
1. 5.2 .3 Arithmetic Operations
For arithmetic purposes, bytes are handled as positive numbers only. The reason is that
a byte occupies the lower eight bits of a register, or a data bus, and the upper eight
bits contain zeros.
1.5.2.4 Data Packing
One of the most useful features of byte mode processing is in the packing and unpacking
of data in memory. Since most of the peripheral devices used with mini computers are
byte oriented, high-speed data transfers between the computer and the peripheral de-
vice generally require data to be packed one byte per word. Such an arrangement is
illustrated in Figure 1- 3. In this illustration, the upper eight bits of each data word
to be transmitted to a peripheral device contain zeros. A full 16-bit word is transmitted
to the device, but the device discards the upper eight bits and accepts only the lower
eight bits. Data received from a byte oriented peripheral device during high-speed
data transfers is packed in memory one byte per word in the format shown in Figure 1- 3.
If a software subroutine were required to pack the data two bytes per word, in the
format illustrated in Figure 1-4, it would waste memory and time in performing the
formatting required for high-speed data transfers.
1-10