Computime Z80 User manual

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zao S INGLE BOARD ro~t1PUTER
SBC880
REFERENCE MANUAL

•
COPYRIGHT NOTICE
Copyright (c) 1982 by COMPUTIME. All Rights Reserved Worldwide.
No part of this publication may be reproduced, transmitted,
transcribed, stored in a retieval system, or translated into any
human or computer language, in any form or by any means,
electronic, mechanical, magnetic, optical, chemical, manual, or
o the r wi s e , wit h0u t the exp res s wr itt en per m iss ion 0fooMPUTI ME ,
8614 Hamilton Ave. Huntington Beach, California 92646 U.S.A.
DI SCLAlMER
SUNTRONICS CO., INC. makes no representations or warranties with
respect to the contents of this manual itself, whether or not the
product it describes is covered by a warranty or repair
agreement. Further, SUNTRONICS CO., INC. reserves the right to
revise this pUblication and to m~ke changes from time to time in
the content hereof without obligation of SUNTRONICS 00., INC. to
notify any person of such revision or changes, except when an
agreement to the contrary exisits. .
i

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TABLE OF CONTENTS
Page Number
SECTION I GENERAL DESCRIPTION ......•......... 1
SECTION II FUNCTIONAL DESCRIPTION ............• 3
SECT I ON I I I I NTERF ACES ..............••••....•. 5
SECTION IV BOARD OPTIONS .•.....•.•.....••..... 9
SECTION V DETAIL DESCRIPTION .•.••...•.•••••..• 11
APPENDIX - A USART - TIMER AND I/O ADDRESS ING. 15
APPENDIX - B USART
19
APPEl·mIX - C PROGRA\'l\W3LE INTERVAL TII'rIER 27
APPENDIX - D PARALLEL PRINTER INSTALLATION..... 31
APPENDIX - E INTERFACING NON- IEEE DYNAMIC MEMORY 33
S~· S T'E1'Y1. l\DN I TOR •••••••••••••••••••••••••••••••• 35

•
SECTION I
GENERAL DESCRIPTION
I
NTRODUcr I ON
------------
The SBC880 Processor Board is a powerful Z80 based design which
is compatible with the IEEE S100/696 bus standard. The SBC880
contains enough features to allow its use as a stand alone single
board system or as the main CPU board in a larger system.
The board is manufactured using quality components that are
conservatively rated to assure long life. All boards are burned
in and tested to assure that the board will work properly when
you
receive it.
Before installing the board read this manual and become familiar
with the SBC880 features and options. The board comes configured
for a 2708 EPROM. If you want to use one of the other type of
EPROM then refer to Section V Board options for modifications.
FEATURES
--------
An on board EPROM can be addressed on any"1K or 2K boundary. AlK
by 8 static RAM may be used in place of the EPROM if desired.
Power-on jump is available directly to the EPROM (or RAM). The
EPROM may optionally be used in shadow mode to allow the full use
of 64K or more of RAM. Devices that can be used in the EPROM
location (U23) are the 2708, 2716 EPROMS or the 4118 static RAM.
In addition to the EPROM, an additional lK of static ram is
provided and it can be located on any 1K boundary. If the EPROM
is not used and the static ram is used instead at the EPROM
location, a total of 2K bytes of ram may be present on the board.
The board is equipped with a USART and aRS232 interface. The
baud rate is programmable by means of a programmable timer. All
model signals required by terminal type equipment is provided for
and terminal equipment may be connected directly to the RS232
connector(J1). Reverse channel capability is available for use
wit h buf fer edt ype de vic es sue has pr int er s. Th ere ver sec hanne 1
is occasionally needed as abUSy or ready indication from the
connected device. It can sense things such as out of paper or
rib bon. A 4 MH z cry s tal pro v ide s a I I s Ys t em tim i ng and can
be selected for 2 or 4 MHz operation.
A DMA capability is provided as well as a means of having the
MWRT signal generated on the CPU board or elsewhere in the system
under control of DMA logic or a front panel.
Two prgrammable timers are available for use by user programs.
The timer output and controls are available at the parallel I/O
connector J2. A parallel input and a parallel output port
is available for use at connector J2.
1

All 5-100 bus sijnals are fUlly buffered and regulators are used
tor all on board voltages to assure an electrically clean and
stable design. A quality PC board is used with solder mask on
both sides, plated through holes and gold plated contacts.
2

Z80A CPU
---- ---
-
SECTION II
FUNCTIONAL DESCRIPTION
The SBC880 is a single board microcomputer designed around the
Z80 microprocssor. The Z80 provides the major control sighals
required to read and write to memory and the I/O ports. A 16 bit
address bus and a 8 bit bi-directional data bus are generatedby
the Z80. The 8BC880 can be run at either 4 or 2 MHz by changing a
simp 1e jumper .
A
crystal controller circuit provides all the timing for the SlOO
bus, the Z80A CPU, the Baud rat timer, and the two programmable
timers. Associated with this circuit are the wait state generator
for the EPROM and reset circuitry which also generates a power-on
clear signal.
STATUS AND CONTROL BUFFERS
------ --- ------- -------
The status and control buffers interface the CPU status and
control signals to the 8-100 bus. These buffers may be tri-stated
by a DMA device to allow a transfer of data between the DMA
device and memory. The DMA device assumes control on thestatus
and control for the duration of the DMA transfer. When a DMA
access is requested by activating the CPU DMA request signal, the
acknowledgment signal from the CPU is made available on the 8-100
bus.
ADDRESS BUFFER
The address buffer is a16 bit tri-state buffer which drives the
CPU's sixteen address bits to the 8-100 bus and to other
circuitry on the CPU board. The buffer is also tri-stated by DMA
devices when a transfer of data is to occur. The DMA device will
then provide the address for the duration of the data transfer.
!2~!~ Q~ ~Q££~g
The data out buffer is an 8 bit tri-state buffer which drives the
eight data bus signals from the CPU to the 8-100 data out bus.
The data out bus will only contain valid data during memory write
or I/O output cycles. The data out bus will be tri-stated by DMA
devices when they are transferring data to memory.
The 8-100 data in bus is provided to the CPU during memory read
or I/O input cycles to devices external to the board. The data in
buffers are disabled during memory write or I/O output cycles
when the CPU is driving data to the data out buffers. The data ~n
3

buffers are dlsabled whenever devices on the CPU board are being
accessed to allow~t~ device being accessed to place data on the
CPU bu s.
The memory decode and control circuitry decodes the hig~ order
address bits and selects the EPROM or static R_~ that is located
on the board.
EPROM
----
The EPROM can be a lK (2708 type), 2K (2716 type), or a lK by 8
static RAM (4118 type). The EPROM may be selected on any lK or 2K
boundary and the optional ram can be selected on any lK boundary.
lK BY 8STATIC RAM
-- -- - ------ ---
The lK of on-board ram may be selected to any lK boundary. The
type of ram provided is static (2114 type) and requires no
refresh. This ram may be used to hold the stack when running
diagnostic tests on a bad dynami~ ram board or it allows the use
of the SBC880 as a stand alone system.
The I/O decode and control circuitry decodes the lower 8 bits of
the add res s bus t0de t e r min e w hen the US ART, tim e r 0r par aI I eI
I/O ports on the board are being address for input or output
operations.
The serial I/O provides asynchronous communication via aRS232
interface. The baud rate is provided by a programmable timer. The
USART is a 8251.
P~W3LE TIMERS
------------ ------
Two programmable timers are available for use on the board. An
8253 or 8254 timer can be used. The timers are clocked from the
crystal controlled clock oscillator on the board.
An 8 bit parallel output port and a 8 bit parallel input port are
provided on the board. The ports are implemented with TTL type
circuitry (74LS373 and 74LS374).
4

•
SECTION III
INTERFACES
EPRO:\1 I NTERF ACE
The EPROM will be selected for access under the following
conditions:
1. When power-on jump is enabled (I to U present) and the
power-on jump latch is set. The EPROM U23 is
unconditionally selected until the latch is reset. The
power on latch is set any time the system is powered up
or the system reset button is pressed. The power-on
latch is reset when amemory read ·operation is performed
and the address being read compares to the switch
set tin gs 0r the EPROM se 1e c t s wit ch SW 3. For 1Kx8E PRO M
(2708 type) the 8131 (U30) compares address bits 10
through 15 to the SW3. For 2K x8 EPROM (2716 type) U30
compares address bit 11 through 15 to the SW3.
2. When not using the phantom option (Q to R present) and a
memory
read operat ion is per formed wi th an address that
compares with the EPROM switch settings (as detected by
the 8131 comparator)
The EPROM may optionally be replaced by a4118 RAM. When the RAM
is used the MEMRD signal is replaced by MRQ so that the RAM
signal is accessed dur ing memory read and wr i te operations. The
CPU WR! signal is jumpered to the ~~ WE! input to allow the CPU
tow r i ted a t a i n tot he RAM d uri ng me m0r y wr i t e cyc Ie s w hen the
RA~ iss eIec ted.
The EPROM or optional RAM is directly connected to the CPU bi-
directional data bus and only appears on the S-100 bus indirectly
through the data out bus drivers. NOTE that only the CPU can
directly access the EPROM or optional R~~. It is not necessary to
have the S-100 bus in operational condition to suc~essfully
access the EPROM or optional ~'1. This feature allows diagnostic
programs to be run in EPROM to diagnose a failing 5-100 bus. The
boa r d can co mm un i cat e wit hat e r min aI and run d i ag nos tic t est s
even when the S-100 bus is completely inoperative.
PHANTOM M:>DE
------- ----
When the phantom EPROM option is used (Q to R cut) the EPROM is
only selected after a power-up or when the system reset is
pre sse dan d the powe r- 0n I at chi sse 1. The EPROM wi lIb e se Ie c ted
for all memory read operations that occur while the power-on
latch is set. During this time a memory write operation will
address memory external to the board in a normal fashion.
Likewise I/O input and output cycles are unaffected by the power-
on latch. Therefore, the program in the EPROM can be used to boot
data from an I/O device into memory after a power-up o.r syst"em
reset operation. The EPROM select switch can be set to detect
5

the starting ad&tess of the code that the EPROM program boots
into memory. Ajump to the starting. address will then be detected
by the 8131 comparator and will reset the power-on ·latch. When
the power-on latch is reset, the EPROM can not be-accessed (the
comparator. cannot select the EPROl\l because Q to R is open). The
data in memory is now accessed in a normal fashion and the EPRQ;\l
effectively disappears from the system until needed at the next
power-up or system reset operation.
A 1K x 8 b I 0c k 0f s tat i cRAM i s imp Ierne n ted u sin g two 211 4 RAM
chips on the board. The RAM is selected by a8131 comparator that
com par e sad d res s bit s lOt hr 0 ugh 1St 0 the RAM se lee t s wit ch.
When amemory
operation is performed by the CPU (MRQ active) and
the comparator detects a match between the address and the RAM
switch, the C8/ lead goes active (low) at the RAM chips. When a
memory
write operation is performed the CPU WR/ signal is active
( low) a t the WE / i n put s0f the RAM chi pst 0a I low the CPU to
wr i ted a t a i n to· the RAM. The RAl'vl 0 nth e boa r dis d ire c t 1Y
connected to the CPU bi-directional data bus and can only be
accessed directly by the CPU. The RAM data is indirectly
available at the 8-100 data out bus. The on-board ~~~, EPROM and
U8ART will function independently of the 8-100 bus and this
allows diagnostics to be performed by the board when the 8-100
bus is inoperative. An example of this feature would be running a
memory diagnostic on the board while diagnosing a dynamic RAM
board that contains the balance of the system memory. The
diagnostic programs can use the on-board static RAM for
scratchpad and stack operations. The diagnostic routines would
run properly even if the RAM board being diagnosed was affecting
signals on the 8-100 bus. In normal use, the on-board RA\1 may be
located in the same address space as other memory in ycur system
with no conflicts between the memory devices. This will be
necessary if your system uses a full 64K of RAM. Whenever the on-
board RAM is accessed during a memory read operation the 8-100
bus data in bus receivers are disabled and the on-board static
RAM i s a I lowed t0 sup ply da tad ire c t 1Y tot he CPU. Th usa n
ext ern a Ide vic ere s po n din gt·) the 5 am e me m0 rye yc 1e W 0 u1d have
its da t a i g nor ed bY the boa r dan d the 0n- boa r d RA:,l w0u 1d sup ply
data instead. When your system RAM is inoperative, the on-board
RA~ will be available to help you get your system going again.
The CPU I/O devices are selected by an 8131 comparator. The 8131
compares address bits A3 through A7 to the I/O select switch
and looks for 10RQ to be active (high) indicating that an I/O
access is in process. The CPU uses address bits AO through A7 to
address I/O devices. Address bits A3 through A7 are tested by the
8131 comparator and address bits Ai and A2 are decoded with gates
to select the individual I/O devices on the board as follows:
6

RD
WR A2
Al
AO
Device Selected
OQeratlon
1-
(f-
n- n-
(f- -
-~25! fTmer---
Read-baue rate
time
01000"'11
tl
Write baud
rate time
10001" " Read
counter
1
01001""
Write counter 1
10010" " Read
counter
2
01010""
Write counter 2
10011""
Illegal
01011""
Write mode word
10100
Input
Port
Read
input
port
011 0 0
Output
Port
Write output
port
10 1 01
Input Port
Read
input
port
01101
Output Port
Write output port
101108251
USART
Read
data
register
011 1 0
tl
"
Write data register
10 1 1 I"
tl
Read
status registe'
01111"" Write
control register
The final I/O port address for each device is determined by the
I/O select switch which determine what state of address bits A3
through A7 will cause the I/O devices on the board to be
selected. NOTE that for some devices during an input cycle (RD
active) a different operation takes place than for an output
cycle (WR active) at the same address. When A2 is high and Al is
low, ani n put cyc I e s e lee t s the i n put po r t, and an 0u t pu tcYc I e
selects the output port. Adderss bit AO is ignored when accessing
the parallel input and output ports and the same devices are
selected with AO high or low.
8253 TIMER INTERFACE
---- ----- ---------
The board provides a2Mhz clock from the clock oscillator
circuitry to the count inputs of timer zero and timer one of the
8253. Timer zero is used as a programmable baud rate generator
for the 8251 USART and its output is connected directly to the
transmit and receive clock inputs of the USART. The gate input to
timer zero (GO) is tied active (high) to permanently enable this
counter. The output of timer one (01) is connected to the input
of timer two (CS) and the two timers can be used together to form
a 32 bit counter/timer. The gate inputs, count inputs, and count
out put s are ava i IabIe for use ate 0nnec tor J 2. Re fer to Ap pendix
C
for a description of the 8253 functions.
8251A USART INTERFACE
----- ----- ---------
Tim e r ze roo f the 8253 d i v ide s the 2 MH z c I 0ck dow nan d pro v ide s
the transmit and receive clocks (TXC and RXC) to the USART.
Transmit data at the RS232 connector Jl pin 2 is level shifted by
a
1489 RS232 receiver and applied to the receive data input (RXD)
of the USART. Transmit data (TXD) from the US ART is level shifted
by a 1488 RS232 transmitter to J1 pin 3. The reverse channel
transmit Jl pin 11 input at the RS232 connector is level shifted
by the 1489 and provided to the DSR/ input of the USART. This
input can be sensed as a status bit in the status register and
has no other affect on the operation of the USART. This allows
7

programs to sensea nott-rpady or buffer full cond it ions on ser ial
I/O devices. The CTS/ input of the USART is tied active (low)
permanently at the input of the USART. This tells the USART that
the RS 232 int er fa ce i 5a Iway s rea dy tot ran s mit dat a. Th e act ua I
par t use d for the US AR T wi I I be an 8251A0r955 1. The 0 Ide r8 2,5 1
will not be used on the board. Refer to Appendix B for a
functional description of the USART device. .
The RS232 connector is configured to allow direct connection to a
device without modems. Any modem signals required by the
connected device will be satisfied by jumpers on the board. The
RS232 connector jumpers together the following RS232 signals at
the connector. Request to send is jumpered to Clear to send Pins
4 and 5. Data terminal ready is jumpered to Data set ready and
Carrier detect Pins 6, 8 and 20.
BAUD RATE DIVISORS
---- ---- --------
When the baud rate timer is initialized a divisor must be
s e Ie c
ted t hat wi I I d i v ide the 2 MH z c 10ck t 0afr e que nc y t hat i s
16
times the baud rate desired. The following list of baud rate
divisors will be of help in selecting the one for your
application.
Baud Rate
---9600--
4800
2400
1200
600
300
150
110
Divisor
-----13
26
52
104
208
417
833
1136
The parallel output port is implemented with a 74LS374 edge-
triggered register. The register outputs are buffered on the chip
and need no additional buffering. The clock to the output port
register is provided to the I/O connector J2. Output data is
latched at the rising (low to high) transition of this clock.
This clock will transition every time the output port is selected
during an I/O output cycle.
The parallel input port is implemented with a 74LS373 octal
transparent latch. The tri-state buffers on this chip provide
da tad ire c t I y tot he CPU b i - d ire c t ion a I da tab u s w hen the i n put
por tis se Iec ted d uri ng the I /0 in put cyc Ie. Th e da tap res en tat
the latch inputs when the latch select strobe goes from high to
low (input port selected) will be latched and then presented to
the CPU data bus. The latch strobe signal is made available at
the I/O connector J2.
8

•
(':,. «-
SECTION
IV
BOARD OPTIONS
OPTION 1 ON BOARD EPROM -2708
EPROM
------ - -- ----- -----
The SBC880 comes
etched
for the
2708
EPROM. These
defaults
are
as
follows:
l.
Z
to
K open
2.
Y to G open
3.
F
to G shorted
4.
H to
I shorted
5.
J
to K shorted
6. L
to
M open
7. P
to 0 shorted
8.
P
to N open
9.
L to
K open
10.
H to
M open
1l. V
to
W
shorted
12.
X to
V
open
OPTION 2-2716 EPRQ\1
------ -
TI
3 Voltage
EPRQ\1
1 nte I+5
vo I t
EPRQ\1
1 • F
to G
shorted
1 . F
to
G open
2.
H to I
shorted
2. H
to 1
shorted
3 . J
to K shorted
3. J
to
K open
4.
L to
M shorted
4. L
to
M
open
5. P
to
0 open
5.
P
to
0
open
6.
P
to
N
shorted
6. 0 to
N
shorted
7• L
to K open
7 .•
L
to
K shorted
8.
H to
M open
8 . H to
1\1 shorted
9 • V
to W shorted
9.
V
to W
shorted
10.
X to
V
open
10.
X
to
V
open
11.
y
to G
open
11.
Y to
G
open
12.
Z to K
open
12 .Z to K
open
13.
Sw it ch 6
of SW3 closed
13. Sw itch
6
of
SW3
closed
14.
G to
+5
OPTION 3-4118 RA.\i
substituted
for EPRO:\1
------ -
l. F
to
G
open
2 . H
to
1 shorted
3.
J to
K
open
4.
L to
M
open
5.
L to K
open
6 • H
to
M shorted
7.
P
to a
shorted
8.
p
to N
open
9. V
to
W
open
10.
X to
V
shorted
1l.
y
to G
shorted
12.
Z to K shorted
9

OPTION 4 - Power-on Jump no Phantom Mode
------ --"
~ 'tt_
An EPRO~ must be present to use the power-on jump feature. The
board is etched for the 2708 EPROM and the power-on jump with no
Phantom mode as follows:
1. T to U shorted
2. Q to R shorted
Q~I!Q~ ~ - Power-on Jump with Phantom Mode
The Eprom
must be present to use this option.
1. T to U shorted
2. Q to R open
Q~I!Q~ ~ - No Power-on Jump
The
EPROM or optional RAM may be used with this option.
1. T to U open
2. Q to R shorted
OPTION 7 - No EPROM
------ -
To disable address selection of the EPROM entirely.
1. Q to R open
2. T to U open
Q~!!Q~ ~ - l\IWRT genera ted by CPU
This option is etched on the board.
1. C to E shorted
2. D to E open
Q~!!Q~ ~ - MWRT generated by external devices
1. C to E open
2. D to E open
Q~!!Q~ !Q - MWRT generated by CPU and external devices
1. C to E open
2. D to E shorted
10

SECTION V
•
DETAIL DESCRIPTION
-Refer to the SBC880 schematic while reading the de"scriptions of
each functional block that follows.
ADDRESS BUS
------- ---
The address bus of the CPU is buffered using 74LS241 devices.
During DMA operations the DMA device will drive S-100 pin 22
(ADDSB/) low
to tri-state the address bus drivers. The DMA device
can then place its own address on the bus.
DATA IN BUS
---- -- ---
During memory read or I/O input operations, the S-100 data in bus
is received and driven to the CPU bi-directional data bus by a
74LS241 type device. Circuitry is provided (l/2 of 7420) to
disable the data in buffers under the following conditions:
1. EPROM or optional ram selected
2. On-board static ram selected
3. Programmable timer selected
4. Parallel 1/0 port selected
5. Memory write or 1/0 output operation in progress
DATA OUT BUS
---- --- ---
Th e CPU b i - d ire c t ion a I da tab u sis dr Iven tot he S -1 00 da tao ut
bus by 74LS241 type buffers. The buffers provide write data from
the CPU to devices on the S-100 bus during memory write
operations. A DMA device wishing to transfer data on the data out
bus wi I I dr i ve pin 23 (DOD SB /) 0 nth e S- 100 bus to a low s tat e.
This will disable the data out buffers on the board and allow the
~L~ device to place data on the bus.
STATUS SIGNALS
------ -------
Status signals SM1, SMEMR, SIN?, SOUT, SINTA, and SWO/ are
provided to the S-100 bus by a8097 type tri-state buffer. A D7.1A
device may drive pin 18 (STATDSB/) low to tri-stat the status
bu f fer to a I low the DMA de vic e tog a inc 0nt r 0I0f the bus.
Control signals PSYNC, PWR/, and PDBIN are provided to the S-100
bus by one section of a8097 type tri-state buffer. A DMA device
may drive pin 19 (C/CDSB/) low to disable this buffer and gain
control of the bus. The MWRITE signal is provided to the bus by
the other half of the 8097 buffer that was used by the control
signals. This buffer may be controlled in several ways: The board
as you received it has this buffer permanently enabled so that
the CPU boa r dis a 1way s the sour ceo f the M\\"R I TE s igna I• I f you r
system contains another device that is to be the source of the
MWRITE signal, then you may cut the etch between points C and E
to disable the buffer on the board. If desired, the MM~ITE buffer
may be disabled by the STATDSB/ signal when a D~iA device is ~sing
11

the bus. This option is enabled by cutting the etch between
poi n t s Can d E ~ a n dot Ii en ins tal lin g a jum per bet wee n poi n t s 0 and
E. This option requires that the DMA device hav~ a buffer to
provided the MWRITE signal that is enabled by the STATDBS/ signal
or a signal with the same timing. This is necessary to prevent
flo a tin g the MWR ITE s i g na Ion the S -100 bus wh i let ran s fer r in g
control of the bus. Data in memory may be overwritten if this
signal is left floating.
The signal SOUT is active (high) when WR/ and IORQ/ signals are
active (low) at the CPU. SINP is active (high) when the signals
RD/ and IORQ/ are active (low) at the CPU. SMEMR is active (high)
w hen the s i gna 1s RD / and MREQ / are act i ve (low) at the CPU.
MWRITE
is active (high) when signals WR/ and MREG/ are active
(low) at the CPU. SMl goes active (high) when Ml/ goes active
(low) at the CPU.
OTHER STATUS SIGNALS
SINTA goes active (high) when Ml/ and IORQ/ go active (low) at
the CPU. SWO/ goes active (low) when the CPU is not performing
any input cycles. This signal is used to provide an early
indication that a write or output cycle is going to take place.
SWO/ is active (low) when RD/ is inactive (high) or SINTA is
inactive (low) will be active (high) at the CPU. The signal
SX TRQ / i s not ge n era ted by the boa r d be c a use 0n I y 8 bit da t a i s
required by the CPU. SXTRQ/ is used to request 16 bi t data
transfers. SHLTA goes active (high) when HLTA/ goes active (low)
at the CPU.
CONTROL SIGNALS OUTPUT
------- ------- ------
The signals PSYNC, PWR/ and PDBIN are tri-stated when C/CDSB/
goes active (low). C/CDSB/ will be driven low by a DMA type
device when the device wants to take control of the bus. The
PSYNC signal goes active (high) momentarily at the start of any
valid I/O or memory cycle. The timing for this signal is
developed by a flip flop and produces timing as defined by the
IEEE S-100 specification. The PSYNC signal is not produced during
CPU memory refresh cycles. PWRl RC"~S active (low) when WRi goes
active (low) at the CPU. The si;r-al PDBIN goes active when a
memory read of I/O input cycle is in process or when an interrup~
is being acknowledged (SINTA high). PDBIN is active (high) when
RD / i sac tiv e (low) at the CPU 0r w hen S I NTA i sac ti ve (h ig h).
PHLDA goes active (high) when BUSAK/ goes active (low) at the
CPU. Th iss i g na I a c k now 1e dge s a DMA r e que s tan din d i cat est hat
th~ requesting device with the highest priority may take control
of the bus. The CPU generates this signal in response to the
signal BUSRQ/ going active (low). BUSRQ/ goes active (low) when a
DMA device drives the S-100 signal PHOLD/ active (low). BUSAK/
only goes active when BUSRQ/ has gone active and the CPU is at a
point in its operation where a DMA access can be perfomed
properly. PHLDA/ is always driven and cannot be tri-stated.
12

CONTROL SIGNALS Ir?UT
------- ------- -----
The IEEE 5-100 bus signal 5IXTN/ is not used by the board
because only'S bit accesses are required by' the CPU. The
signal SIXTN/ is a response to a request for a 16 bit ~emory
access. Since a 16 bit access is never requested by the. board,
this signal is ignored. The signals XRDY or PROY when driven low
will make the WAIT/ signal go active (low) at the CPU. The
EP~1 wait state generator can make the WAIT/ signal active for
one clock cycle during accesses to the on-board EPROM. The EPROM
wait state generator must be enabled by a jumper option. PRDY/
is normally used by slow memory or I/O devices to extend an
access cycle by inserting wait states at the CPU. The device
being accessed holds PRDY/ active (low) for the number of clock
cycles (wait states) desired. XRDY is normally used by front
panel type devices to halt or single step the processor. PWAIT/
goes active (high), WAIT/ goes active (low). When PINT/ is driven
active (low) at the S-100 bus, the signal INT/ will be active
(low) atthe CPU.This is one of the maskable interrupt request
input to the CPU. When NMI/ is driven active (low) at the S-100
bus, the signal NMI/ goes active (low) at the CPU. This is the
non-maskable interrupt request input to the CPU When PHOLD/ is
d r i ve n act i ve (low) a t the 5 - 100 bUS, the s i gna I BU5 RQ / wi I I be
active (low) at the CPU. r he PHOLD/ signal is used by the DMA
devices to request access to the bus.
DMA CONTROL LINES
--- ------- -----
The primary lines used to tri-state the bus drivers for DMA
operations are 0005B/, AD05B/, 5TATD5B/, and C/CD5B. OOD5B/ tri-
states the data out bus drivers when it is driven active (low).
AD05B/ tri-states the address bus drivers when it is driven
active (low). STATDSB/ tri-states the status signals SOUT, SINP,
5MEMR, 5M1, SImA and SWO/ when it is driven active (low). MWRITE
may be tri-stated by STATD5B/ if selected by a jumper option.
C/CDSB/ tri-states the signal PSYNC, PWR/ and POBIN when driven
active (low). When a DMA device is granted access to the bus by
PHLDA s i gna I go in g act i ve (h i g h) it wi I I nor rna I I Y8 C t i vat e the
I:X\1A control signals and drive its own signals on to the bus.
SYSTE\l POWER LINES
------ ----- -----
A positive 8 volts DC should be present on 5-100 bus pins 1 and
51. This voltage is regulated on the board to develop +5 volts.
The regulator is decoupled on its input by a 1.5 uf capacitor and
the +5 volt output is decoupled by .1 uf capacitors at various
places around the board. A negative 16 volts DC should be present
at S-100 bus pin 52. The voltage is regulated by two regUlators
on the board to develop -12 volts and -5 volts. Both regUlators
are decoupled with 1.5 uf capacitors at thier inputs and outputs.
A positive 16 volts DC should be present at 8-100 bus pin 2. This
voltage is regulated on the board to develop +12 volts. The
regUlator is decoupled by a 1.5 uf capacitor at its input and a
should be present on S-100 bus pins 50 and 53.
13

SYSTEM CLOCK
------ -----
The board generates all timing from a 4 MHz crystal controlled
oscillator. The 4 MHz clock is divided down to 2 MHz by a flip
flop. The 2/4 MRs jumpers selects which clock rate is applied to
the CPU and related circuitry. The selected clock is provided to
the S-100 bus at 02. An inverted version of 02 is provided ~s 01.
The 2
MHz clock is provided directly to S-100 bus as CLOCK/. This
clock is always 2 MHz and is not affected by the 2/4 MHz jumper.
~!~!§M !!~~~! !:~£!:!QNS
When PRESET is driven active (low) at the S-100 bus, a 100 uf
capacitor on this line is discharged. This signal is normally
driven low by the system reset button being pressed. The PRESET
signal is synchronized to the system clock with a flip flop and
is then applied to the following circuits:
1. The Z80 CPU
2. The 8251 USART
3. POC at the S-100 bus
4. The power-on jump latch
The reset signal will remain active (low) ~fter the switch is
released for approximately 470 milliseconds due to the time it
takes to charge the 100 uf capacitor to a true level. This same
circuit de-bounces the reset switch and provides a reset signal
during power up.
14

-
APPENDIX A
US ART
TIMER AND I/O ADDRESS ING
Swi tch
SWI
selects
the base address range
of
8 addresses
RANGE
SWl
SW2
SW3 SW4 SW5
-----
00-07
XX X X X
08-0F X X X X
10-17
X X X X
18-IF
X X X
20-27
X X X X
28-2F
XX X
30-37
XX X
38-3F
XX
40-47
X X X X
48-4F
X X X
50-57
XXX
58-SF X X
60-67
XXX
68-6F
X
X·
70-77
XX
78-7F
X
80-87
X X X X
88-8F
XX X
90-97
XXX
98-9F X X
AO-A7
XXX
A8-AF X X
BO-B7
XX
B8-BF X
CO-C7 X X X
C8-CF XX
DO-D7
X X
D8-DF X
EO-E7
X X
E8-EF X
FO-F7 X
F8-FF
First address
XO or
X8
-Timer o
Data
2nd "Xl
or
X9 -"1"
3rd
"
X2 or
XA
"2"
4th
"
X3 or
XB-
tl
Control
5th
"
X4 or
XC -
Parallel Input and Ou tpu t Port
6th
"
X5 or
XD -"""""
7th
"
X6 or XE
- USART Data
8th
"
X7 or
XF-
"
Control
15

SWI - 5
SWI -4
SWl -3
SWl -2
SWl - 1
------ -
~j [~~~~~~ ---Sase Address Seleelion
~~ [~~~~~~~~ -~I/O PorI Seleelion
A2 Al AO
--------------------------------------
Timer
0
Data
0 0 0
"1"0 0 1
"2"010
"
Control
011
Parallel
I/O
10 0
II
"101
US ART
Data 110
"
Control
111
16

Pin No
--- --
2
3
4
5
6
7
8
11
20
PIN NO
---1--
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
21
22
23
24
25
-.
TABLE 1
CONNECTOR Jl SIGNALS
Function
--------
RS232 Transmit Data
RS232 Receive Data
Reques t to Send
Clear to Send
Data Set Ready
Signal Ground
Carrier Detect
Reverse Channel Transmit
Data Terminal Ready
TABLE 2
CONNECTOR J2 SIGNALS
FUNCTIONS
--Output-Port Data Bit 0
Output Port Data Bit 1
Output Port Data Bit 2
Output Port Data Bit 3
Output Port Data Bit 4
Output Port Data Bit 5
Output Port Data Bit 6
Output Port Data Bit 7
Signal Ground
Output Port Clock
Counter 1 Gate Input
Counter 2 Gate Input
InDut Port Data Bit 0
In~ut Port Data Bit 1
ln~~t Port Data Bit 2
Input Port Data Bit 3
Input Port Data Bit 4
Input Port Data Bit 5
Input Port Data Bit 6
Input Port Data Bit 7
Signal Ground
Input Port Strobe
Counter 1 Output (also counter 2
input)
Counter 2 Output
17