Curtiss-Wright SCRAMNet+ SC150e Application guide

SC150e PCI, PMC & CPCI Bus
(Universal Signaling)
Hardware Reference
Document No. D-T-MR-PCPMCPE#-A-1-A4

FOREWORD
The information in this document has been carefully checked and is believed to be accurate; however, no
responsibility is assumed for inaccuracies. Curtiss-Wright Controls, Inc., reserves the right to make
changes without notice.
Curtiss-Wright Controls, Inc., makes no warranty of any kind with regard to this printed material,
including, but not limited to, the implied warranties of merchantability and fitness for a particular
purpose.
©Copyright 2007 Curtiss-Wright Controls, Inc., All Rights Reserved.
SCRAMNet®is a registered trademark of Curtiss-Wright Controls, Inc., US Patent # 4,928,289
ST®is a registered trademark of AT&T.
DIGITAL™and DEC™are trademarks of Digital Equipment Corporation.
PICMG®and CompactPCI®are registered trademarks of the PCI Industrial Computer Manufacturer’s
Group
Curtiss-Wright Controls, Inc., is an Associate Level member of PICMG and as such may use the PICMG
and CompactPCI logos.
Any reference made within this document to equipment from other vendors does not constitute an
endorsement of their product(s).
Revised: August 13, 2007
Curtiss-Wright Controls Embedded Computing
Data Communications
2600 Paramount Place Suite 200
Fairborn, OH 45324 USA
Tel: [phone] (U.S. only)
Tel: [phone]

FCC
This product is intended for use in industrial, laboratory, or military environments. This product uses and
emits electromagnetic radiation, which may interfere with other radio and communication devices. The
user may be in violation of FCC regulations if this device is used in other than the intended market
environments.
CE
As a component part of another system, this product has no intrinsic function and is therefore not subject
to the European Union CE EMC directive 89/336/EEC.

Copyright 2007 i SCRAMNet+ SC150e HARDWARE REFERENCE
TABLE OF CONTENTS
1. INTRODUCTION...................................................................................................................................... 1-1
1.1 How To Use This Manual ........................................................................................................ 1-1
1.1.1 Purpose .................................................................................................................. 1-1
1.1.2 Scope .....................................................................................................................1-1
1.1.3 Style Conventions.................................................................................................. 1-1
1.2 Related Information.................................................................................................................. 1-2
1.3 Quality Assurance .................................................................................................................... 1-3
1.4 Technical Support..................................................................................................................... 1-4
1.5 Ordering Process ...................................................................................................................... 1-4
2. SCRAMNET OVERVIEW........................................................................................................................ 2-1
2.1 Overview .................................................................................................................................. 2-1
2.2 Shared Memory ........................................................................................................................ 2-1
2.2.1 Dual-Port Memory Controller................................................................................ 2-1
2.2.2 Control/Status Registers (CSRs)............................................................................ 2-3
2.2.3 Virtual Paging........................................................................................................ 2-3
2.3 FIFO Buffers ............................................................................................................................ 2-3
2.3.1 Transmit FIFO ....................................................................................................... 2-3
2.3.2 Transceiver FIFO................................................................................................... 2-3
2.3.3 Interrupt FIFO........................................................................................................ 2-3
2.3.4 Receiver FIFO ....................................................................................................... 2-4
2.4 Network Ring ........................................................................................................................... 2-4
2.4.1 Protocol..................................................................................................................2-4
2.5 Auxiliary Control RAM (ACR)................................................................................................ 2-5
2.6 Interrupts .................................................................................................................................. 2-6
2.6.1 Network Interrupt Writes....................................................................................... 2-6
2.6.2 Selected Interrupt................................................................................................... 2-6
2.6.3 Forced Interrupt ..................................................................................................... 2-8
2.7 External Triggers...................................................................................................................... 2-9
2.8 General Purpose Counter/Global Timer ................................................................................... 2-9
2.9 Modes of Operation.................................................................................................................. 2-9
2.9.1 Data Filter Mode.................................................................................................... 2-9
2.9.2 High Performance (HIPRO) Mode ...................................................................... 2-10
2.9.3 Holdoff Mode ...................................................................................................... 2-10
2.9.4 Loopback Modes ................................................................................................. 2-10
2.9.5 Write-Me-Last Mode ........................................................................................... 2-11
3. PRODUCT OVERVIEW........................................................................................................................... 3-1
3.1 Overview .................................................................................................................................. 3-1
3.2 SCRAMNet+ SC150e Cards .................................................................................................... 3-1
3.2.1 SCRAMNet+ SC150e PCI Card............................................................................ 3-1
3.2.2 SCRAMNet+ SC150e PMC Card.......................................................................... 3-2
3.2.3 SCRAMNet+ SC150e CPCI Card ......................................................................... 3-3
3.3 LED Status Indicators............................................................................................................... 3-4
3.3.1 Insert LED ............................................................................................................. 3-4
3.3.2 Carrier Detect LED................................................................................................ 3-4
3.4 Software ................................................................................................................................... 3-4
3.5 Utility Software ........................................................................................................................ 3-4
3.5.1 SCRAMNet Diagnostics........................................................................................ 3-4
3.5.2 EEPROM Initialization (EPI) ................................................................................ 3-4
3.5.3 SCRAMNet Monitor ............................................................................................. 3-4
3.6 Options ..................................................................................................................................... 3-5
3.6.1 Fiber Optic Bypass Switch .................................................................................... 3-5
3.6.2 Quad Switch .......................................................................................................... 3-6
3.6.3 Fiber-Optic Cables................................................................................................. 3-7
4. INSTALLATION....................................................................................................................................... 4-1

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Copyright 2007 ii SCRAMNet+ SC150e HARDWARE REFERENCE
4.1 Installation Procedures ............................................................................................................. 4-1
4.2 Unpack the Card....................................................................................................................... 4-1
4.3 VisualIy Inspect the Card ......................................................................................................... 4-1
4.4 External Configuration ............................................................................................................. 4-6
4.4.1 Set/Verify EEPROM Jumpers ............................................................................... 4-6
4.5 Install the Card ......................................................................................................................... 4-7
4.5.1 PCI/PMC Card Installation.................................................................................... 4-7
4.5.2 CPCI Card Installation........................................................................................... 4-8
4.6 Cabling Configuration and Connection .................................................................................... 4-8
4.6.1 Fiber-optic Configuration ...................................................................................... 4-8
4.6.2 Fiber-optic Cables.................................................................................................. 4-9
4.6.3 Fiber-optic Connection ........................................................................................ 4-10
4.7 Fiber Optic Bypass Switch Option ......................................................................................... 4-11
4.7.1 Configuration and Connection with SC150e PCI and CPCI................................ 4-11
4.7.2 Configuration and Connection with SC150e PMC .............................................. 4-12
4.7.3 Auxiliary Connection on SC150e PCI and CPCI................................................. 4-14
4.7.4 Auxiliary Connection on SC150e PMC............................................................... 4-14
4.8 Internal Configuration ............................................................................................................ 4-15
4.8.1 SCRAMNet+ SC150e Control/Status Registers (CSR) ....................................... 4-15
4.8.2 SCRAMNet on DEC Computers ......................................................................... 4-16
4.8.3 EEPROM Initialization........................................................................................ 4-16
4.8.4 Node Identification .............................................................................................. 4-17
4.8.5 Network Time-out ............................................................................................... 4-17
4.9 Byte Swapping ....................................................................................................................... 4-17
4.10 DMA Operation.................................................................................................................... 4-18
4.11 Maintenance ......................................................................................................................... 4-18
4.12 Troubleshooting.................................................................................................................... 4-18
5. OPERATION ............................................................................................................................................. 5-1
5.1 Overview .................................................................................................................................. 5-1
5.2 Shared Memory ........................................................................................................................ 5-1
5.2.1 Virtual Paging........................................................................................................ 5-1
5.2.2 Memory Considerations......................................................................................... 5-3
5.2.3 Control/Status Registers ........................................................................................ 5-3
5.3 Initialization ............................................................................................................................. 5-4
5.4 Basic Send/Receive Configuration ........................................................................................... 5-4
5.5 Network Ring ........................................................................................................................... 5-4
5.5.1 Message Contents .................................................................................................. 5-5
5.5.2 Protocol..................................................................................................................5-5
5.5.3 Performance........................................................................................................... 5-7
5.5.4 Throughput ............................................................................................................ 5-8
5.6 Auxiliary Control RAM ........................................................................................................... 5-8
5.7 Interrupt Controls ................................................................................................................... 5-10
5.7.1 Interrupt Options.................................................................................................. 5-10
5.8 Interrupt Conditions................................................................................................................ 5-11
5.8.1 Network Data Write............................................................................................. 5-11
5.8.2 Network Error...................................................................................................... 5-15
5.8.3 Interrupt Handling ............................................................................................... 5-16
5.9 External Triggers.................................................................................................................... 5-17
5.10 General Purpose Counter/Timer ........................................................................................... 5-18
5.10.1 Available Modes................................................................................................ 5-18
5.10.2 Rollover/Reset ................................................................................................... 5-18
5.10.3 Presetting Values ............................................................................................... 5-18
5.11 Modes of Operation.............................................................................................................. 5-19
5.11.1 Data Filter.......................................................................................................... 5-19
5.11.2 HIPRO Mode..................................................................................................... 5-21
5.11.3 Loopback Modes ............................................................................................... 5-21
5.11.4 Holdoff Mode .................................................................................................... 5-27
5.11.5 Write-Me-Last Mode ......................................................................................... 5-28
5.12 Quad Switch ......................................................................................................................... 5-28

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Copyright 2007 iii SCRAMNet+ SC150e HARDWARE REFERENCE
APPENDICES
APPENDIX A - SPECIFICATIONS ........................................................................................................... A-1
APPENDIX B - CSR DESCRIPTION.......................................................................................................... B-1
APPENDIX C - CSR SUMMARY ............................................................................................................... C-1
APPENDIX D - CONFIGURATION AIDS .................................................................................................D-1
GLOSSARY................................................................................................................................ GLOSSARY-1
INDEX .................................................................................................................................................INDEX-1
FIGURES
Figure 2-1 Functional Diagram ...................................................................................................................... 2-2
Figure 2-2 ACR/Memory Access................................................................................................................... 2-5
Figure 2-3 Outgoing Interrupt ........................................................................................................................ 2-7
Figure 2-4 Incoming Interrupt........................................................................................................................ 2-8
Figure 3-1 SCRAMNet+ SC150e PCI Card................................................................................................... 3-1
Figure 3-2 SCRAMNet+ SC150e PMC Card................................................................................................. 3-2
Figure 3-3 SCRAMNet+ SC150e CPCI Card ................................................................................................ 3-3
Figure 3-4 Ring with Bypass Switches........................................................................................................... 3-6
Figure 3-5 Node Inclusion and Isolation ........................................................................................................ 3-6
Figure 4-1 PCI Layout (card revision B1)...................................................................................................... 4-2
Figure 4-2 PCI Layout (card revision C1 or higher) ...................................................................................... 4-3
Figure 4-3 PMC Layout ................................................................................................................................. 4-4
Figure 4-4 CPCI Layout................................................................................................................................. 4-5
Figure 4-5 EEPROM WRITE (J303) ............................................................................................................. 4-6
Figure 4-6 EEPROM READ (J304) ............................................................................................................... 4-6
Figure 4-7 PMC Card Installation .................................................................................................................. 4-7
Figure 4-8 Fiber-optic ST Connector ............................................................................................................. 4-9
Figure 4-9 Fiber-Optic Connections............................................................................................................. 4-10
Figure 4-10 Inserted State (Power On)......................................................................................................... 4-11
Figure 4-11 Bypass State (Power Off) ......................................................................................................... 4-11
Figure 4-12 Inserted State (Power On)......................................................................................................... 4-12
Figure 4-13 Bypass State (Power Off) ......................................................................................................... 4-13
Figure 4-14 Auxiliary Connection................................................................................................................ 4-14
Figure 4-15 PMC Faceplate With Auxiliary Connection .............................................................................4-14
Figure 5-1 Memory Sharing With Virtual Paging.......................................................................................... 5-2
Figure 5-2 Transmit Interrupt Logic............................................................................................................. 5-12
Figure 5-3 Receive Interrupt Logic .............................................................................................................. 5-14
Figure 5-4 Data Filter Logic......................................................................................................................... 5-20
Figure 5-5 Monitor and Bypass Mode.......................................................................................................... 5-22
Figure 5-6 Wire Loopback Mode................................................................................................................. 5-23
Figure 5-7 Mechanical Switch Loopback Mode .......................................................................................... 5-24
Figure 5-8 Fiber-optic Loopback Mode ....................................................................................................... 5-25
Figure 5-9 Insert Mode................................................................................................................................. 5-27
Figure 5-10 Quad Switch ............................................................................................................................. 5-29
Figure 5-11 Interrupt Service Routine............................................................................................................ 1-1

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Copyright 2007 iv SCRAMNet+ SC150e HARDWARE REFERENCE
TABLES
Table 4-1 PCI Auxiliary Connection Pinout ................................................................................................ 4-14
Table 4-2 PMC Auxiliary Connection Pinout .............................................................................................. 4-15
Table 4-3 SCRAMNet+ SC150e Control/Status Registers .......................................................................... 4-15
Table 4-4 EEPROM Table ........................................................................................................................... 4-16
Table 4-5 EEPROM Initialization................................................................................................................ 4-16
Table 4-6 Byte Ordering Comparisons......................................................................................................... 4-17
Table 4-7 PCI_MAP0/PCI _MAP1 Swapping Options ............................................................................... 4-17
Table 5-1 SCRAMNet+ SC150e Message Contents ...................................................................................... 5-5
Table 5-2 ACR Functions .............................................................................................................................. 5-8
Table 5-3 Interrupt Controls......................................................................................................................... 5-10
Table 5-4 Interrupt Error/Status Conditions................................................................................................. 5-15
Table 5-5 General Purpose Counter/Timer Modes....................................................................................... 5-18
Table 5-6 Data Filter Options....................................................................................................................... 5-19
Table 5-7 Monitor and Bypass Mode States................................................................................................. 5-22
Table 5-8 Wire Loopback Mode States........................................................................................................ 5-23
Table 5-9 Mechanical Switch Loopback Mode States ................................................................................. 5-24
Table 5-10 Fiber-optic Loopback Mode States ............................................................................................ 5-25
Table 5-11 Node Insert Mode ...................................................................................................................... 5-26

Copyright 2007 1-1 SCRAMNet+ SC150e HARDWARE REFERENCE
1. INTRODUCTION
1.1 How To Use This Manual
1.1.1 Purpose
This document is a reference manual for the SCRAMNet+ SC150e PCI, PMC and
CompactPCI network interface cards (NIC). It provides a physical and functional
description of the SCRAMNet+ SC150e NIC and describes how to unpack, set up, install
and operate the hardware. Hereafter in this manual “CompactPCI” is referred to as
“CPCI.”
1.1.2 Scope
This information is intended for systems designers, engineers, and network installation
personnel. You need at least a systems level understanding of general computer
processing, of memory and hardware operation, and of the specific host processor to use
this manual effectively.
1.1.3 Style Conventions
•Hexadecimal values are written with a “0x” prefix. For example, 0x03FF.
•Switch, signal and jumper abbreviations are in capital letters. For example,
RSW1, J5, etc.
•Register bits and bit ranges are specified by the register identification followed
by the bit or range of bits in brackets [ ]. For example, CSR6[4], CSR3[15:0],
ACR [1,2]
•Bit values are shown in single-quotes. For example, set bit 15 to ‘1.’
•Code and monitor screen displays of input and output are boxed and indented on
a separate line. Text that represents user input is bolded. Text that the computer
displays on the screen is not bolded. For example:
C:\>ls
file1 file2 file3
•Large samples of code are Courier font, at least one size less than context, and
are usually on a separate page or in an appendix.

INTRODUCTION
Copyright 2007 1-2 SCRAMNet+ SC150e HARDWARE REFERENCE
1.2 Related Information
•SCRAMNet Network Programmer’s Reference Guide (Doc. Nr. D-T-MR-
PROGREF) - A collection of routines to assist SCRAMNet users with
application development.
•SCRAMNet Network Utilities User Manual (Doc. Nr. C-T-MU-UTIL) - A user’s
manual for the SCRAMNet Classic, SCRAMNet-LX, and SCRAMNet+ SC150e
hardware diagnostic software, SCRAMNet+ SC150e EEPROM initialization
software, and the SCRAMNet Network Monitor.
•SCRAMNet Network Media User’s Guide (Doc. Nr. D-T-MU-MEDIA)—A
description of network cabling hardware accessories for the SCRAMNet+
SC150e Network.
•PCI Special Interest Group (PCI-SIG). The PCI-X specification is available to
PCI-SIG members and can be downloaded from www.pcisig.com
•PCI Industrial Computer Manufacturer’s Group (PCIMG). The CPCI Core
specification is available to members and can be downloaded from
www.picmg.org.

INTRODUCTION
Copyright 2007 1-3 SCRAMNet+ SC150e HARDWARE REFERENCE
1.3 Quality Assurance
Curtiss-Wright Controls’ policy is to provide our customers with the highest quality
products and services. In addition to the physical product, the company provides
documentation, sales and marketing support, hardware and software technical support,
and timely product delivery. Our quality commitment begins with product concept, and
continues after receipt of the purchased product.
Curtiss-Wright Controls’ Quality System conforms to the ISO 9001 international standard
for quality systems. ISO 9001 is the model for quality assurance in design, development,
production, installation, and servicing. The ISO 9001 standard addresses all 20 clauses of
the ISO quality system, and is the most comprehensive of the conformance standards.
Our Quality System addresses the following basic objectives:
•Achieve, maintain, and continually improve the quality of our products through
established design, test, and production procedures.
•Improve the quality of our operations to meet the needs of our customers,
suppliers, and other stakeholders.
•Provide our employees with the tools and overall work environment to fulfill,
maintain, and improve product and service quality.
•Ensure our customer and other stakeholders that only the highest quality product
or service will be delivered.
The British Standards Institution (BSI), the world’s largest and most respected
standardization authority, assessed Curtiss-Wright Controls’ Quality System. BSI’s
Quality Assurance division certified we meet or exceed all applicable international
standards, and issued Certificate of Registration, number FM 31468, on May 16, 1995.
The scope of Curtiss-Wright Controls’ registration is: “Design, manufacture and service
of high technology hardware and software computer communications products.” The
registration is maintained under BSI QA’s bi-annual quality audit program.
Customer feedback is integral to our quality and reliability program. We encourage
customers to contact us with questions, suggestions, or comments regarding any of our
products or services. We guarantee professional and quick responses to your questions,
comments, or problems.

INTRODUCTION
Copyright 2007 1-4 SCRAMNet+ SC150e HARDWARE REFERENCE
1.4 Technical Support
Technical documentation is provided with all of our products. This documentation
describes the technology, its performance characteristics, and includes some typical
applications. It also includes comprehensive support information, designed to answer any
technical questions that might arise concerning the use of this product. We also publish
and distribute technical briefs and application notes that cover a wide assortment of
topics. Although we try to tailor the applications to real scenarios, not all possible
circumstances are covered.
Although we have attempted to make this document comprehensive, you may have
specific problems or issues this document does not satisfactorily cover. Our goal is to
offer a combination of products and services that provide complete, easy-to-use solutions
for your application.
If you have any technical or non-technical questions or comments, contact us. Hours of
operation are from 8:00 a.m. to 5:00 p.m. Eastern Standard/Daylight Time.
•Phone: [phone] or [phone]
•E-mail: [email protected]
•Fax: [phone]
•World Wide Web address: www.cwcembedded.com
1.5 Ordering Process
To learn more about Curtiss-Wright Controls’ products or to place an order, please use
the following contact information. Hours of operation are from 8:00 a.m. to 5:00 p.m.
Eastern Standard/Daylight Time.
•Phone: [phone] or [phone]
•E-mail: [email protected]
•World Wide Web address: www.cwcembedded.com

Copyright 2007 2-1 SCRAMNet+ SC150e HARDWARE REFERENCE
2. SCRAMNET OVERVIEW
2.1 Overview
The SCRAMNet+ SC150e Network is a real-time communications network, based on a
replicated, shared-memory concept. Each host processor on the network has access to its
own local copy of shared memory that is updated over a high-speed, serial-ring network.
The network is optimized for high-speed data transfer among multiple, real-time
computers all solving portions of the same real-time problem.
2.2 Shared Memory
In its simplest form, the SCRAMNet+ SC150e Network system is designed to appear as
general-purpose memory. The use of this memory depends only on the conventions and
limitations imposed by the specific host computer system and operating system. On most
processors, this means that the application program can use this memory in basically the
same way as any other data-storage area of memory. However, the memory cannot be
used as instruction space.
The major difference between SCRAMNet+ SC150e memory and system memory is any
data written into SCRAMNet+ SC150e memory is automatically sent to the same
SCRAMNet+ SC150e memory location in all nodes on the network. This is why it is also
referred to as replicated shared memory. A good analogy is the COMMON AREA used
by the FORTRAN programming language. Where the COMMON AREA makes variables
available to subroutines of a program, SCRAMNet+ SC150e makes variables available to
processors of a network.
When a host computer writes to the shared memory, the proper handshaking logic is
supplied by the SCRAMNet+ SC150e node host adapter. The shared memory behaves
somewhat like resident or local memory.
A software driver is usually not required except for interrupt handling.
2.2.1 Dual-Port Memory Controller
The Dual-Port Memory Controller (see Figure 2-1) allows the host to read from or write
to shared memory with a simultaneous network write to shared memory. Unless an
interrupt has been authorized for that memory address, the host is not aware the network
is writing to shared memory. This is why caching must be disabled for SCRAMNet
memory. If an interrupt has been authorized, the interrupt will then be sent to the host
processor.

SCRAMNET OVERVIEW
Copyright 2007 2-2 SCRAMNet+ SC150e HARDWARE REFERENCE
NODE
IN
NODE
OUT
Interrupt
FIFO
Transceiver
FIFO
Receiver
Network
Control Logic
Transmitter
Replicated
Shared
Memory
Transmit
FIFO
Dual
Port
Memory
Host
Interface
Logic
All Reads
All Reads
All Writes
ASIC
Port1-Host
Port 2Network
P1
Figure 2-1 Functional Diagram

SCRAMNET OVERVIEW
Copyright 2007 2-3 SCRAMNet+ SC150e HARDWARE REFERENCE
2.2.2 Control/Status Registers (CSRs)
CSRs control the SCRAMNet+ SC150e card’s Input/Output (I/O) operations The location
of the CSRs in the computer’s address space is determined by the plug-and play BIOS in
the host system. You can find the CSRs address offsets in chapter 4: INSTALLATION.
Most modes of operation are set during initialization in registers embedded in the PCI
target controller, and remain unchanged during run time.
2.2.3 Virtual Paging
The SCRAMNet+ SC150e network may include a variety of SCRAMNet+ SC150e nodes
having varying amounts of shared memory. However, all SCRAMNet+ SC150e nodes
use the same 8 MB shared memory map. This feature permits different SCRAMNet+
SC150e cards with 4 MB of shared memory or less to be paged into different sections of
the 8 MB memory map. A card with a 4 MB or smaller memory may be located on any
shared-memory address boundary that is an even multiple of itself (For example, 2 MB
can page to 0, 2, 4 or 6 MB address).
2.3 FIFO Buffers
The SCRAMNet+ SC150e card contains various FIFO buffers used for temporarily
storing information during normal send and receive operation of the node. Refer to Figure
2-1.
2.3.1 Transmit FIFO
The Transmit FIFO is a message holding area for native messages waiting to be
transmitted. Each host write to SCRAMNet+ SC150e memory may constitute a write to
the Transmit FIFO. (Data Filtering and HIPRO features may interfere with this.) Each
write to the Transmit FIFO contains 21 bits of address (A22-A2), 32 bits of data, and one
bit of interrupt information. The Transmit FIFO can hold up to 1024 writes before
becoming full.
When the Transmit FIFO reaches a FULL condition (CSR1[0] ON), one more host write
could cause a message to be lost. To prevent this, the CSR-controllable, built-in
SCRAMNet+ SC150e feature called HOLDOFF mode extends the computer write cycle
until the Transmit FIFO is able to empty at least one message.
2.3.2 Transceiver FIFO
The Transceiver buffer is used to receive foreign messages from the network, and send
them on, or to hold received foreign messages while inserting a native message from the
host onto the network.
Each node is responsible for receiving foreign messages, writing them to its copy of
shared memory, and re-transmitting the message to the next node.
2.3.3 Interrupt FIFO
The Interrupt FIFO contains a 21-bit address (A22 - A2) and a retry-status bit for each
shared-memory-based interrupt received. The Interrupt FIFO can hold 1024 interrupt
addresses. This FIFO can be read using CSR4 and CSR5.

SCRAMNET OVERVIEW
Copyright 2007 2-4 SCRAMNet+ SC150e HARDWARE REFERENCE
2.3.4 Receiver FIFO
The Receiver FIFO is designed as a temporary holding place for incoming foreign
messages while the shared memory is busy servicing a host request. This FIFO is three
messages deep, and is designed so it can never be overrun. Each item in the Receiver
FIFO contains 21 bits of address (A22 - A2), 32 bits of data, and one incoming interrupt
bit. When the messages are 1024 bytes, the initial header information data stays in the
FIFO, the subsequent four bytes of data are loaded in, and the address is incremented by
four.
2.4 Network Ring
The SCRAMNet+ SC150e Network is a ring topology network. Data is transmitted at a
rate of 150 Mbits/s over dual fiber-optic cables. Together, the two lines produce the
incoming data clock. Due to the network speed and message packet size, the network can
accommodate over 1,800,000 message packets passing by each node every second. There
is an approximate 247 ns (minimum) delay at each node as the message packet works its
way around the ring. The maximum delay depends on the selection of fixed-length or
variable-length message packets. A fixed-length message packet has a maximum delay of
800 ns, a 256-byte variable-length message packet is 16.2 µs, and a 1024-byte variable-
length message packet is 62 µs. Delay can be imposed when a node must complete the
transmission of a native message packet before retransmitting a foreign message packet.
A SCRAMNet+ SC150e Network can accommodate up to 256 nodes per network ring.
2.4.1 Protocol
The protocol is a register-insertion methodology and is NOT a token ring. Depending on
the protocol selected, all message packets are the same size or are variable (as in the
PLUS modes), and multiple nodes can transmit data simultaneously. There is no master
node, and all nodes have equal priority for network bandwidth. The message protocol is
designed specifically for real-time applications where data must be passed very rapidly.
When the node operates in BURST or BURST PLUS mode, the node will never re-
transmit its own messages for error correction. When operating in PLATINUM or
PLATINUM PLUS mode, error detection is enabled, and re-transmission can occur.
BURST MODE
BURST mode is an open loop, non-error-corrected communication mode. This mode
allows multiple 82-bit messages (46-bit header plus 32-bite data and four parity bits) per
node on the ring at a time. The limited-message-packet length enhances the data latency
characteristics of the network by providing the shortest possible media access delay. The
messages are transmitted as fast as the system will allow.
PLATINUM MODE
PLATINUM mode is BURST mode with error correction enabled. The messages are
transmitted as fast as the system will allow, but error checking is used to detect and re-
transmit corrupted message packets.

SCRAMNET OVERVIEW
Copyright 2007 2-5 SCRAMNet+ SC150e HARDWARE REFERENCE
PLUS MODES
The PLUS mode protocol enhancement can increase the maximum network throughput
from 6.5 MB/sec to approximately 15.2 to 16.7 MB/sec by the use of variable-length
message packets. Each SCRAMNet+ SC150e message packet has a 46-bit header plus
the data. The user-selectable maximum message packet size increases the data size from
the normal 32 bits to either 256 or 1024 bytes of data. Data must be written to sequential
longword addresses.
2.5 Auxiliary Control RAM (ACR)
The Auxiliary Control RAM (ACR) provides external triggering and interrupt control by
offering a choice of four actions to occur when a particular SCRAMNet+ SC150e shared-
memory address is written into. Each shared-memory location has its own action or set of
actions associated with it.
0
1
Shared Memory
ACR Memory
CSR0[4]
Host READ/WRITE
request to a specific
32-bit memory address
Byte 0 Byte 1 Byte 2 Byte 3
Byte 0
PHYSICAL
MEMORY CHIP DOES NOT
REALLY EXIST
LEGEND
Figure 2-2 ACR/Memory Access
In Figure 2-2, host CPU read/write operations are channeled to either SCRAMNet+
SC150e memory or to the ACR. The ACR is a physically separate memory from the
shared memory. Channeling is based on a user-controlled switch setting and may be
toggled to the desired position by writing to a bit in the SCRAMNet+ SC150e CSR.
When access to the ACR is enabled, shared memory is not accessible by the host and the
ACR byte is viewed as the least significant byte (LSB) of every shared-memory four -
byte address. The ACR bits define the necessary external trigger and/or interrupt action(s)
taken whenever writing to any byte of the SCRAMNet+ SC150e shared-memory four-
byte word.
Only five bits of the ACR are associated with every four-byte word of shared memory
(on even four-byte boundaries). The other 27 bits of the ACR are not used.

SCRAMNET OVERVIEW
Copyright 2007 2-6 SCRAMNet+ SC150e HARDWARE REFERENCE
2.6 Interrupts
SCRAMNet+ SC150e allows a node processor to receive interrupts from and transmit
interrupts to any node on the network. This includes the originating node, provided the
receiving node is set up to receive an interrupt message. Interrupts are generated under
two different conditions:
•SCRAMNet+ SC150e network data writes to shared memory; and
•SCRAMNet+ SC150e network errors detected on the local node.
SCRAMNet+ SC150e interrupts usually require a device driver to interface with the node
processor. The driver is required primarily to permit the host processor to handle
interrupts from the SCRAMNet device.
2.6.1 Network Interrupt Writes
FOREIGN MESSAGE
The node can receive a message from another node with the interrupt bit set. If Receive
Interrupt Enable ACR[0] and Interrupt Mask Match Enable CSR0[5] are enabled, the
data is written to shared memory and the address is placed on the Interrupt FIFO.
NATIVE MESSAGE
If the message received was originated by the node, and Write Own Slot Enable CSR2[9]
and Enable Interrupt on Own Slot CSR2[10] are enabled, the host has authorized a Self-
Interrupt. The data is written to shared memory and the address is placed on the Interrupt
FIFO.
Network Interrupt writes are accomplished by two methods:
•Selected. Data writes to selected shared-memory locations from the network.
•Forced. Any data writes to any shared memory from the network.
In either case, the node can be configured to write to itself. This condition is called “Self
Interrupt”.
2.6.2 Selected Interrupt
The selected-interrupt method requires choosing SCRAMNet+ SC150e shared-memory
locations on each node to receive and/or to transmit interrupts. These shared-memory
locations may also be used to generate signals to external triggers. The procedure for
selecting shared-memory locations for interrupts and/or external triggers is explained in
the paragraph on the Auxiliary Control RAM, paragraph 2.5.
OUTGOING INTERRUPT
The Outgoing Interrupt is described in Figure 2-3. If both Transmit Interrupt Enable
ACR[1] and Network Interrupt Enable CSR0[8] are set, and a data item is transmitted to
any of the selected-interrupt memory locations, then an interrupt message is sent out on
the network. This message will generate interrupts to any processors on the network that
have that same shared-memory location selected to receive interrupts.

SCRAMNET OVERVIEW
Copyright 2007 2-7 SCRAMNet+ SC150e HARDWARE REFERENCE
INCOMING INTERRUPT
Figure 2-4 demonstrates the process of receiving a message with the interrupt bit set. The
data is written to shared memory and the address is placed in CSR5 and CSR4 to await
being sent to the host. If the Receive Interrupt Enable ACR[0], Host Interrupt Enable
CSR0[3], and the Interrupt Memory Mask Match Enable CSR0[5] are set, and network
interrupt data is received for any one of the selected interrupt memory locations the
following occurs:
•The data is stored in that location
•The SCRAMNet+ SC150e address of the memory location is placed on the
Interrupt FIFO queue, and
•An interrupt is sent to the processor.
NETWORK ERRORS
The Interrupt on (Network) Errors mode is enabled by setting CSR0[7] ON. Network
errors are defined in CSR1 according to an interrupt mask set in CSR9. When an
incoming foreign message generates an interrupt, there is no way to mask the interrupt
according to the content of the message. However, specific error conditions are identified.
CPU
ACR SHARED MEMORY
Address
Data
Interrupt Bit
RINGNETWORK
LOGIC
RING
Address
Data
OUTGOING
A22 - A0
D31 - D0
TIE D31 - D0
A22 - A0
D31 - D0
1
Figure 2-3 Outgoing Interrupt

SCRAMNET OVERVIEW
Copyright 2007 2-8 SCRAMNet+ SC150e HARDWARE REFERENCE
INCOMING
INTERRUPT
CPU
INTERRUPT FIFO
ACR SHARED MEMORY
Address
Address
Data
Interrupt Bit
RING
NETWORK
LOGIC
RING
CSR 4 CSR 5
A16 - A0 A22 - A16
A22 - A0 RIE D31 - D0
A22 - A0
D31 - D0
1
Figure 2-4 Incoming Interrupt
Error conditions are listed in CSR1 and are masked by setting the corresponding bit in
CSR9. If the Mask bits in CSR9 are all set to ‘1’, any error will generate an interrupt.
Otherwise, only errors with a ‘1’ in the appropriate Mask bit will generate an interrupt.
2.6.3 Forced Interrupt
The forced-interrupt method works the same for selected-interrupt except for the choice
of interrupt locations. All shared-memory locations are automatically set up to receive
and/or transmit interrupts depending on the ACR override conditions set in CSR0[6]
and/or CSR0[9].
When Override Receive Interrupt Enable CSR0[6] is set, an interrupt will be sent to the
host by any network-interrupt-data message , regardless of the status of the ACR Receive
Interrupt bit.
When Override Transmit Interrupt Enable CSR0[9] is set, an interrupt will be sent out on
the network regardless of the status of the ACR Transmit Interrupt bit.
A third condition, Receive Interrupt Override CSR8[10], is used to designate all
incoming network traffic as interrupt messages. The network message interrupt bit does
not need to be set.