Curtiss-Wright CHAMP-AV8 Instructions for use
Artisan Technology Group is your source for quality
new and certied-used/pre-owned equipment
• FAST SHIPPING AND
DELIVERY
• TENS OF THOUSANDS OF
IN-STOCK ITEMS
• EQUIPMENT DEMOS
• HUNDREDS OF
MANUFACTURERS
SUPPORTED
• LEASING/MONTHLY
RENTALS
• ITAR CERTIFIED
SECURE ASSET SOLUTIONS
SERVICE CENTER REPAIRS
Experienced engineers and technicians on staff
at our full-service, in-house repair center
WE BUY USED EQUIPMENT
Sell your excess, underutilized, and idle used equipment
We also offer credit for buy-backs and trade-ins
www.artisantg.com/WeBuyEquipment
REMOTE INSPECTION
Remotely inspect equipment before purchasing with
our interactive website at www.instraview.com
LOOKING FOR MORE INFORMATION?
Visit us on the web at www.artisantg.com for more
information on price quotations, drivers, technical
specications, manuals, and documentation
Contact us: (888) 88-SOURCE | sales@artisantg.com | www.artisantg.com
SM
View
Instra
Document Number:
Version:
Date:
Curtiss-Wright
Defense Solutions
333 Palladium Drive
Ottawa, Ontario, Canada
K2V 1A6
(613) 599-9199
PROPRIETARY NOTICE: This document is the property of Curtiss-Wright Controls Inc. (CW Controls) and shall not
be copied or used, in whole or in part, without prior written permission from CW Controls.
CHAMP-AV8 (VPX6-462)
VPX QUAD-CORE
INTEL CORE™ i7
DSP BOARD
HARDWARE USER’SMANUAL
826448
5
March 2015
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com
CHAMP-AV8 (VPX6-462) HARDWARE USER’SMANUAL CURTISS-WRIGHT
II PROPRIETARY 826448 VERSION 5 MARCH 2015
VERSION HISTORY
Version By Date Description
1 JP July 2011 First release.
2 TM September 2012 Updated document template.
Updated section, “General Description” on page 1-2.
Updated section, “Feature Summary” on page 1-3.
Updated Figure 1.2, “CHAMP-AV8 Functional Block Diagram,” on page 1-5.
Updated “Quad-Core Intel Core i7 Processors” on page 1-6.
Updated Figure 1.3, “CHAMP-AV8 PCI Express Distribution,” on page 1-7.
Updated section, “PCI Express Architecture” on page 1-7.
Updated Table 1.1 on page 1-8.
Updated Figure 1.5, “CHAMP-AV8 SRIO Port Connections,” on page 1-11.
Updated section, “Core Functions FPGA” on page 1-12.
Updated section, “Double Data Rate (DDR3) SDRAM with ECC” on page 1-13.
Updated section, “Protected Boot Flash Memory” on page 1-14.
Updated section, “NAND Flash Memory” on page 1-14.
Updated section, “Non-Volatile RAM (NVRAM)” on page 1-15.
Updated section, “Interrupt Controller” on page 1-24.
Updated section, “Specifications” on page 1-31.
Updated Table 1.8, “CHAMP-AV8 Weight,” on page 1-33.
Updated Table 1.9, “VPX6-462-A Air-Cooled Ruggedization Levels,” on page 1-34.
Updated section “Mezzanine Module Power Considerations” on page 2-5.
Updated Table 2.2, “Maximum Supply Current for XMC Site,” on page 2-5.
Updated section “Installation Checklist” on page 3-3.
Updated section “Choose a VPX Slot Location” on page 3-4.
Replaced Figure 3.2, “System Boot Screen,” on page 3-11.
Updated section “Display the Initial Screen Message” on page 3-13.
Replaced Figure 3.3, “GRUB Loading Message,” on page 3-13.
Updated section, “Troubleshooting” on page 3-14.
Updated Table 3.7, “Summary of LED Behavior,” on page 3-15.
Updated Appendix A, "Connector Pin Assignments".
Added Appendix B, "Statement of Memory Volatility".
Added Appendix C, "Memory Write Protection".
3 JP February 2013 Updated Figure 1.2, “CHAMP-AV8 Functional Block Diagram,” on page 1-5.
Updated section “PCI Express Architecture” on page 1-7.
Updated Table 1.1, “XMC/Expansion Plane Interface Build-Time Options for PCIe,” on page 1-8
Added Figure 1.4, “PCIe Switch Partitions,” on page 1-9.
Updated section “SRIO Fabric” on page 1-10.
Updated section “XMC Site” on page 1-15.
Updated section “RTC/CMOS RAM Backup Power” on page 1-24.
Updated Table 1.6, “Power Requirements,” on page 1-32.
Updated section “Continuum IPC™ Library” on page 1-40.
Updated section “Detailed Power Requirements” on page 2-3.
Updated Table 2.1, “Voltage and Current Requirements,” on page 2-3.
Updated “XMC I/O” on page 2-4.
Updated “XMC Site” on page 2-4.
Updated section “Mezzanine Module Power Considerations” on page 2-5.
Updated section “VITA 46 P1 Fabric Connector” on page A-9.
Updated Table A.4, “P0 Utility Connector Signal Definitions,” on page A-15.
Updated Table A.39, “RTM SW2–SW18 Functions,” on page A-57.
4 JP June 2013 Updated “Configuring Jumpers” on page 2-7.
Updated Table A.39, “RTM SW2–SW18 Functions,” on page A-57.
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com
CURTISS-WRIGHT
826448 VERSION 5 MARCH 2015 PROPRIETARY III
5 JE March 2015 Updated "Reference Documentation" on page xv.
Updated “General Description” on page 1-2.
Updated “Feature Summary” on page 1-3.
Added note to section “PCI Express Architecture” on page 1-7.
Added note to section “SRIO Fabric” on page 1-10.
Deleted section “Intelligent Peripheral Management Controller” previously on page 1-15.
Updated “XMC Site” on page 1-15.
Updated “Serial Ports” on page 1-17.
Updated “1000Base-BX Ethernet” on page 1-20.
Updated “Voltage, Current, and Temperature Sensors” on page 1-22.
Updated Figure 1.11, “Location of Voltage, Current, and Temperature Sensors (Secondary
Side),” on page 1-23.
Updated “RTC/CMOS RAM Backup Power” on page 1-24.
Updated Table 1.3, “Interrupt Input Connections,” on page 1-26.
Updated Table 1.4, “VPX Compliance Summary,” on page 1-31
Updated Table 1.11, “Summary of CHAMP-AV8 Connectors, Functions Supported,” on page
1-39.
Updated “Continuum IPC™ Library” on page 1-40.
Updated “Continuum Vector™ Library” on page 1-41.
Updated “Backplane Requirements” on page 2-2.
Updated “Detailed Power Requirements” on page 2-3.
Updated “XMC Site” on page 2-4.
Removed the caution note in “Install the XMC Module on the Basecard” on page 3-3.
Updated Table 3.7, “Summary of LED Behavior,” on page 3-15.
Updated Appendix A, "CHAMP-AV8 I/O Mapping".
Updated Table A.4, “P0 Utility Connector Signal Definitions,” on page A-15.
Updated Table A.39, “RTM SW2–SW18 Functions,” on page A-57.
Added two notes to Appendix A, "Rear Transition Module (RTM) Configuration Switches".
Updated Table B.1, “Memory Devices Available On The CHAMP-AV8,” on page B-2.
Version By Date Description
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com
CHAMP-AV8 (VPX6-462) HARDWARE USER’SMANUAL CURTISS-WRIGHT
IV PROPRIETARY 826448 VERSION 5 MARCH 2015
COPYRIGHT NOTICE
The information in this document is subject to change without notice and should not
be construed as a commitment by Curtiss-Wright Controls, Inc. While reasonable
precautions have been taken, Curtiss-Wright Controls, Inc. assumes no
responsibility for any errors that may appear in this document.
No part of this document may be copied or reproduced without the prior written
consent of Curtiss-Wright Controls, Inc.
The proprietary information contained in this document must not be disclosed to
others for any purpose, nor used for manufacturing purposes, without written
permission of Curtiss-Wright Controls, Inc. The acceptance of this document will be
construed as an acceptance of the foregoing condition.
Copyright © 2015, Curtiss-Wright Controls, Inc. All rights reserved.
TRADEMARKS
Adobe and Acrobat are trademarks of Adobe Systems Incorporated.
Ethernet is a trademark of Xerox Corporation.
Fedora, is a trademark of Red Hat, Inc.
Intel and Intel Core are trademarks or registered trademarks of Intel Corporation.
Linux is a registered trademark of Linus Torvalds.
PCIe is a registered trademark of PCI-SIG.
RapidIO is a registered trademark of the RapidIO Trade Association.
SourcePoint is a trademark of American Arium.
VxWorks, Tornado and Wind River Systems are registered trademarks of Wind River
Systems, Inc.
All other brand and product names are trademarks or registered trademarks of their
respective owners.
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com
CURTISS-WRIGHT TABLE OF CONTENTS
826448 VERSION 5 MARCH 2015 PROPRIETARY V
TABLE OF CONTENTS
Preface ......................................................................................................................................... xiii
Purpose ................................................................................................................................... xiii
Audience.................................................................................................................................. xiii
Scope...................................................................................................................................... xiii
Documentation Roadmap ...........................................................................................................xiv
Related Software Documents ......................................................................................................xiv
Reference Documentation ........................................................................................................... xv
Conventions Used in this Manual ................................................................................................. xvi
Technical Support Information ..................................................................................................... xx
1. Product Overview ................................................................................. 1-1
In This Chapter ..............................................................................................................................1-1
General Description ........................................................................................................................1-2
Feature Summary...........................................................................................................................1-3
Technical Description ......................................................................................................................1-5
Quad-Core Intel Core i7 Processors .............................................................................................1-6
PCI Express Architecture ............................................................................................................1-7
SRIO Fabric............................................................................................................................ 1-10
Core Functions FPGA ............................................................................................................... 1-12
Double Data Rate (DDR3) SDRAM with ECC ................................................................................1-13
Protected Boot Flash Memory....................................................................................................1-14
NAND Flash Memory................................................................................................................ 1-14
Non-Volatile RAM (NVRAM).......................................................................................................1-15
Non-Volatile Memory Security ...................................................................................................1-15
XMC Site................................................................................................................................ 1-15
Utility Features, Semaphores, Timers......................................................................................... 1-16
Avionics Style Watchdog Timer ................................................................................................. 1-16
Multi-board Synchronous Clock ................................................................................................. 1-17
Serial Ports ............................................................................................................................ 1-17
1000Base-T Ethernet ............................................................................................................... 1-19
1000Base-BX Ethernet............................................................................................................. 1-20
USB and SATA Interfaces .........................................................................................................1-20
LVTTL Discrete Digital I/O ........................................................................................................ 1-21
EIA-422 Differential Discrete Digital I/O ..................................................................................... 1-21
Voltage, Current, and Temperature Sensors................................................................................ 1-22
Indicator LEDs ........................................................................................................................ 1-23
Cables and Rear Transition Modules........................................................................................... 1-24
RTC/CMOS RAM Backup Power.................................................................................................. 1-24
Interrupt Controller ................................................................................................................. 1-24
Specifications............................................................................................................................... 1-31
VPX Compliance...................................................................................................................... 1-31
Power Requirements................................................................................................................ 1-32
Dimensions ............................................................................................................................ 1-33
Weight .................................................................................................................................. 1-33
Ruggedization Levels ............................................................................................................... 1-34
Physical Characteristics ................................................................................................................. 1-35
VPX6-462-A Front Panel........................................................................................................... 1-37
Location of Status LEDS on Conduction-Cooled Variant................................................................. 1-38
Mating Connectors .................................................................................................................. 1-39
Overview of Available Software ...................................................................................................... 1-40
Built In Test (BIT) Firmware ..................................................................................................... 1-40
Operating System Software ......................................................................................................1-40
Continuum IPC™ Library ..........................................................................................................1-40
Continuum Vector™ Library ......................................................................................................1-41
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com
CHAMP-AV8 (VPX6-462) HARDWARE USER’SMANUAL CURTISS-WRIGHT
VI PROPRIETARY 826448 VERSION 5 MARCH 2015
2. Pre-Installation Tasks .......................................................................... 2-1
In This Chapter.............................................................................................................................. 2-1
Unpacking the Card........................................................................................................................ 2-2
Checking Hardware Requirements .................................................................................................... 2-2
Chassis Requirements ............................................................................................................... 2-2
Backplane Requirements ........................................................................................................... 2-2
Detailed Power Requirements.....................................................................................................2-3
BIOS Configuration Parameters .................................................................................................. 2-4
XMC Module Installation Requirements ........................................................................................ 2-4
XMC Site ................................................................................................................................. 2-4
Cable Requirements.................................................................................................................. 2-6
Configuring Jumpers ...................................................................................................................... 2-7
3. Hardware Installation........................................................................... 3-1
In This Chapter.............................................................................................................................. 3-1
Introduction .................................................................................................................................. 3-2
Electro-Static Discharge (ESD) Precautions .................................................................................. 3-2
Installation Prerequisites................................................................................................................. 3-3
Installation Checklist................................................................................................................. 3-3
Unpack and Configure the Card .................................................................................................. 3-3
Install the XMC Module on the Basecard ...................................................................................... 3-3
Choose a VPX Slot Location ....................................................................................................... 3-4
Quick Installation and Power Up Procedure ........................................................................................ 3-4
Detailed Installation Procedure ........................................................................................................ 3-4
Insert the Basecard in the Chassis ..............................................................................................3-4
Connect a Terminal................................................................................................................... 3-5
Connect Ethernet Ports ............................................................................................................. 3-6
CBL-462-FPL-000 Front Panel Cable Connections .......................................................................... 3-8
Booting: Entering the BIOS Setup Utility.....................................................................................3-11
Initiate the Power-Up Sequence ................................................................................................3-12
Display the Initial Screen Message .............................................................................................3-13
Troubleshooting............................................................................................................................3-14
Verify Insertion in Chassis ........................................................................................................3-14
LED Diagnostics ......................................................................................................................3-14
LED Start-Up Sequence (Power On) ...........................................................................................3-19
LED Start-Up Sequence (Reset).................................................................................................3-20
Sign-on Message Garbled .........................................................................................................3-20
The Next Step ..............................................................................................................................3-20
A. Connector Pin Assignments .................................................................. A-1
In This Appendix............................................................................................................................ A-1
Connector Overview ....................................................................................................................... A-3
Backplane VPX Connectors ........................................................................................................A-3
About VITA 46 and ANSI/VITA 65 ............................................................................................... A-4
CHAMP-AV8 I/O Mapping...........................................................................................................A-8
Using the CHAMP-AV8 Pinout Configurator ................................................................................. A-10
Selecting the XMC Module ....................................................................................................... A-11
Generating Pinouts ................................................................................................................. A-12
Saving the Pinout Table........................................................................................................... A-13
Defining New XMC Modules...................................................................................................... A-13
Loading XMC Module Definitions ............................................................................................... A-13
Backplane VPX Connectors—Detailed Description ............................................................................. A-14
CHAMP-AV8 P0 Utility Connector Pin Assignments....................................................................... A-14
Corresponding VPX Backplane J0 Utility Connector Pin Assignments .............................................. A-16
CHAMP-AV8 P1 (SRIO Fabric) Connector Pin Assignments ............................................................ A-17
Corresponding VPX Backplane J1 (SRIO Fabric) Connector Pin Assignments.................................... A-19
CHAMP-AV8 P2 (PCIe Expansion) Connector Pin Assignments ....................................................... A-20
Corresponding VPX Backplane J2 (PCIe Expansion) Connector Pin Assignments .............................. A-22
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com
CURTISS-WRIGHT TABLE OF CONTENTS
826448 VERSION 5 MARCH 2015 PROPRIETARY VII
CHAMP-AV8 P3 (XMC Site’s PMC User I/O) Connector Pin Assignments ...........................................A-23
Corresponding VPX Backplane J3 (XMC Site’s PMC User I/O) Connector Pin Assignments ..................A-25
CHAMP-AV8 P4 (Basecard I/O) Connector Pin Assignments ...........................................................A-26
Corresponding VPX Backplane J4 (Basecard I/O) Connector Pin Assignments ..................................A-29
CHAMP-AV8 P5 (XMC User I/O) Connector Pin Assignments ..........................................................A-30
Corresponding VPX Backplane J5 (XMC User I/O) Connector Pin Assignments..................................A-32
CHAMP-AV8 P6 (XMC/DIO/SATA/USB) Connector Pin Assignments.................................................A-33
Corresponding VPX Backplane J6 (XMC/DIO/SATA/USB) Connector Pin Assignments ........................A-35
J1 Front Panel Connector ...............................................................................................................A-36
XMC Site's PMC J14 Connector .......................................................................................................A-39
XMC Site's PMC J14 User I/O Connector .....................................................................................A-39
XMC J15 and J16 Connectors..........................................................................................................A-42
XMC J15 Connector .................................................................................................................A-42
XMC J16 User I/O Connector.....................................................................................................A-45
Rear Transition Module (RTM) ........................................................................................................A-52
Rear Transition Module Panel-Mounted Connectors ......................................................................A-54
Rear Transition Module (RTM) Configuration Switches ..................................................................A-57
Rear Transition Module (RTM) PWB Header Connectors ................................................................A-58
B. Statement of Memory Volatility ............................................................ B-1
In This Appendix ........................................................................................................................... B-1
CHAMP-AV8 Statement of Volatility .................................................................................................. B-2
C. Memory Write Protection..................................................................... C-1
In This Appendix ........................................................................................................................... C-1
NVRAM Write Protection ................................................................................................................. C-2
BIOS SPI Flash Write Protection....................................................................................................... C-3
On-Board SATA (NAND) Flash Write Protection .................................................................................. C-4
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com
CHAMP-AV8 (VPX6-462) HARDWARE USER’SMANUAL CURTISS-WRIGHT
VIII PROPRIETARY 826448 VERSION 5 MARCH 2015
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com
CURTISS-WRIGHT LIST OF FIGURES
826448 VERSION 5 MARCH 2015 PROPRIETARY IX
LIST OF FIGURES
Figure 1.1: Air-Cooled CHAMP-AV8 Isometric View...............................................................................1-3
Figure 1.2: CHAMP-AV8 Functional Block Diagram ...............................................................................1-5
Figure 1.3: CHAMP-AV8 PCI Express Distribution .................................................................................1-7
Figure 1.4: PCIe Switch Partitions......................................................................................................1-9
Figure 1.5: CHAMP-AV8 SRIO Port Connections .................................................................................1-11
Figure 1.6: Core Functions FPGA Block Diagram ................................................................................1-12
Figure 1.7: Boot Flash SPI Bus Architecture ......................................................................................1-14
Figure 1.8: CHAMP-AV8 Serial Port Implementation ...........................................................................1-18
Figure 1.9: CHAMP-AV8 Serial Port Detail .........................................................................................1-19
Figure 1.10: Location of Voltage, Current, and Temperature Sensors (Primary Side) ................................1-22
Figure 1.11: Location of Voltage, Current, and Temperature Sensors (Secondary Side) ............................1-23
Figure 1.12: CHAMP-AV8 Interrupt Controller Block Diagram ................................................................1-25
Figure 1.13: Interrupt Routing Block (Part A)......................................................................................1-28
Figure 1.14: Interrupt Routing Block (Part B)......................................................................................1-29
Figure 1.15: CHAMP-AV8 Board Layout—Primary Side) ........................................................................1-35
Figure 1.16: CHAMP-AV8 Board Layout—Secondary Side ......................................................................1-36
Figure 1.17: Status LEDS on Conduction-Cooled Variants .....................................................................1-38
Figure 2.1: CBL-462-FPL-000 (CHAMP-AV8 Standard Front Panel Cable Assembly)...................................2-6
Figure 2.2: Configuration Jumper Locations ........................................................................................2-8
Figure 3.1: Location of CHAMP-AV8 Ethernet Activity LEDs....................................................................3-7
Figure 3.2: System Boot Screen ......................................................................................................3-11
Figure 3.3: GRUB Loading Message..................................................................................................3-13
Figure A.1: VPX System Connectors Overview .................................................................................... A-3
Figure A.2: VPX RT2 Type Connector................................................................................................. A-4
Figure A.3: VPX RT2 Wafer Routings ................................................................................................. A-5
Figure A.4: CHAMP-AV8 Backplane P0-P6 Connector Orientation ........................................................... A-7
Figure A.5: I/O Mapping to the CHAMP-AV8 VITA 46 Connectors........................................................... A-8
Figure A.6: CHAMP-AV8 Pinout Configurator Main Window ..................................................................A-11
Figure A.7: Sample P5 Pinout Table .................................................................................................A-12
Figure A.8: CHAMP-AV8 P0 Utility Connector .....................................................................................A-14
Figure A.9: CHAMP-AV8 P1 SRIO Fabric Connector.............................................................................A-17
Figure A.10: CHAMP-AV8 VITA 46 P2 Connector ..................................................................................A-20
Figure A.11: P3 XMC Site’s PMC User I/O Connector ............................................................................A-23
Figure A.12: P4 Basecard I/O Connector.............................................................................................A-26
Figure A.13: P5 XMC User I/O Connector............................................................................................A-30
Figure A.14: P6 XMC/DIO/PCIe Connector ..........................................................................................A-33
Figure A.15: J1 Contact Numbering Arrangement (Looking into the Front Panel) ......................................A-38
Figure A.16: Location of CHAMP-AV8 J14 Connector.............................................................................A-39
Figure A.17: Location of CHAMP-AV8 XMC J15 and J16 Connectors ........................................................A-42
Figure A.18: CHAMP-AV8 Rear Transition Module Views........................................................................A-52
Figure A.19: RTM Printed Wiring Board Component Side View ...............................................................A-53
Figure A.20: Serial Port Loopback Control via RTM P3 ..........................................................................A-55
Figure A.21: Proper Jumper Orientation for RTM P3 Jumpers .................................................................A-56
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com
CHAMP-AV8 (VPX6-462) HARDWARE USER’SMANUAL CURTISS-WRIGHT
XPROPRIETARY 826448 VERSION 5 MARCH 2015
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com
CURTISS-WRIGHT LIST OF TABLES
826448 VERSION 5 MARCH 2015 PROPRIETARY XI
LIST OF TABLES
Table 1.1: XMC/Expansion Plane Interface Build-Time Options for PCIe.....................................................1-8
Table 1.2: CPS-1432 SRIO Switch Port Numbering............................................................................... 1-10
Table 1.3: Interrupt Input Connections............................................................................................... 1-26
Table 1.4: VPX Compliance Summary................................................................................................. 1-31
Table 1.5: XMC Compatibility Identification Block................................................................................. 1-31
Table 1.6: Power Requirements ......................................................................................................... 1-32
Table 1.7: CHAMP-AV8 Dimensions .................................................................................................... 1-33
Table 1.8: CHAMP-AV8 Weight .......................................................................................................... 1-33
Table 1.9: VPX6-462-A Air-Cooled Ruggedization Levels ....................................................................... 1-34
Table 1.10: VPX6-462-C Conduction-Cooled Ruggedization Levels ........................................................... 1-34
Table 1.11: Summary of CHAMP-AV8 Connectors, Functions Supported .................................................... 1-39
Table 2.1: Voltage and Current Requirements .......................................................................................2-3
Table 2.2: Maximum Supply Current for XMC Site ..................................................................................2-5
Table 2.3: Jumper Block Definition.......................................................................................................2-7
Table 3.1: CBL-462-FPL-000 USB (J1) Signal Mapping ............................................................................3-8
Table 3.2: CBL-462-FPL-000 EIA-232 Node A Serial Port 0 (J2) Signal Mapping .........................................3-8
Table 3.3: CBL-462-FPL-000 EIA-232 Node B Serial Port 0 (J3) Signal Mapping .........................................3-9
Table 3.4: CBL-462-FPL-000 Ethernet Port A (J4) Signal Mapping ............................................................3-9
Table 3.5: CBL-462-FPL-000 Ethernet Port B (J5) Signal Mapping .......................................................... 3-10
Table 3.6: CBL-462-FPL-000 Reset Pushbutton (SW1) Signal Mapping .................................................... 3-10
Table 3.7: Summary of LED Behavior ................................................................................................. 3-15
Table A.1: Wafer Usage - CHAMP-AV8 P0 Utility Connector......................................................................A-6
Table A.2: Wafer Usage - CHAMP-AV8 P1-P6 Connectors.........................................................................A-6
Table A.3: P0 Utility Connector Pin Assignments ..................................................................................A-15
Table A.4: P0 Utility Connector Signal Definitions ................................................................................. A-15
Table A.5: VPX Backplane J0 Pin Assignments .....................................................................................A-16
Table A.6: P1 SRIO Fabric Connector Pin Assignments ..........................................................................A-17
Table A.7: P1 SRIO Fabric Connector Signal Definitions.........................................................................A-18
Table A.8: VPX Backplane J1 Pin Assignments .....................................................................................A-19
Table A.9: P2 PCIe Expansion Plane Connector Pin Assignments.............................................................A-21
Table A.10: P2 PCIe Expansion Plane Connector Signal Definitions ...........................................................A-21
Table A.11: VPX Backplane J2 Pin Assignments .....................................................................................A-22
Table A.12: P3 XMC Site’s PMC User I/O Connector Pin Assignments ........................................................A-24
Table A.13: P3 XMC Site’s PMC User I/O Connector Signal Definitions.......................................................A-24
Table A.14: VPX Backplane J3 Pin Assignments .....................................................................................A-25
Table A.15: P4 Basecard I/O Connector Pin Assignments ........................................................................ A-27
Table A.16: P4 Basecard I/O Connector Signal Definitions ....................................................................... A-27
Table A.17: VPX Backplane J4 Pin Assignments .....................................................................................A-29
Table A.18: P5 XMC User I/O Connector Pin Assignments........................................................................ A-31
Table A.19: P5 XMC User I/O Connector Signal Definitions ...................................................................... A-31
Table A.20: VPX Backplane J5 Pin Assignments .....................................................................................A-32
Table A.21: P6 XMC/DIO/SATA/USB Connector Pin Assignments ..............................................................A-34
Table A.22: P6 XMC/DIO/SATA/USB Connector Signal Definitions.............................................................A-34
Table A.23: VPX Backplane J6 Pin Assignments .....................................................................................A-35
Table A.24: J1 Front Panel Connector Description .................................................................................. A-36
Table A.25: J14 Connector Description (Pn4/Jn4 User Defined I/O) ..........................................................A-40
Table A.26: J15 Primary XMC Connector Pin Assignments ....................................................................... A-43
Table A.27: J15 Primary XMC Connector Signal Definitions ......................................................................A-43
Table A.28: J16 Secondary XMC Connector Pin Assignments ................................................................... A-45
Table A.29: J16 Secondary XMC Connector Signal Definitions ..................................................................A-45
Table A.30: XMC J16 User I/O Connector Description (Row A) .................................................................A-46
Table A.31: XMC J16 User I/O Connector Description (Row B) .................................................................A-47
Table A.32: XMC J16 User I/O Connector Description (Row C) ................................................................. A-48
Table A.33: XMC J16 User I/O Connector Description (Row D) .................................................................A-49
Table A.34: XMC J16 User I/O Connector Description (Row E) .................................................................A-50
Table A.35: XMC J16 User I/O Connector Description (Row F) .................................................................A-51
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com
CHAMP-AV8 (VPX6-462) HARDWARE USER’SMANUAL CURTISS-WRIGHT
XII PROPRIETARY 826448 VERSION 5 MARCH 2015
Table A.36: RTM ENET A (J5), ENET B (J6) Connector Details.................................................................. A-54
Table A.37: RTM RS422 (J4) Connector Details .....................................................................................A-54
Table A.38: RTM EIA-232 COM Ports A-D (J2-J3) Connector Details ......................................................... A-55
Table A.39: RTM SW2–SW18 Functions................................................................................................ A-57
Table A.40: RTM Header Functions ...................................................................................................... A-58
Table A.41: RTM PMC I/O (JB2) Pin Assignments................................................................................... A-59
Table A.42: RTM Discrete I/O (P4, P5) Pin Assignments ......................................................................... A-61
Table A.43: RTM Geographical Address (P12) Pin Assignments................................................................ A-61
Table A.44: XMC Single Ended I/O (JB6) Pin Assignments ...................................................................... A-62
Table A.45: RTM XMC Differential User I/O (J7) Pin Assignments ............................................................. A-63
Table B.1: Memory Devices Available On The CHAMP-AV8 ...................................................................... B-2
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com
CURTISS-WRIGHT
826448 VERSION 5MARCH 2015 PROPRIETARY XIII
PREFACE
PURPOSE
This manual describes the OpenVPX (VITA 65) based CHAMP-AV8 and applies to L0
(commercial) and L100/L200 (air-cooled and conduction-cooled) products. When differences
exist between these versions of the product, the differences will be noted. After explaining the
capabilities of the CHAMP-AV8, the manual provides the procedure for installing it and
checking its operation.
AUDIENCE
This document is aimed at readers with a technical understanding of hardware engineering
fundamentals, as well as a basic understanding of the VPX, PCIe, and digital signal processing
hardware and software.
SCOPE
This manual contains the following chapters:
Chapter 1, "Product Overview". This chapter provides an overview of the features and
functions of the CHAMP-AV8 product. This includes a technical description and a block
diagram.
Chapter 2, "Pre-Installation Tasks". This chapter discusses tasks that must be performed
before installing the CHAMP-AV8 in a system, including checking power requirements.
Chapter 3, "Hardware Installation". This chapter explains how to install the CHAMP-AV8
into a VPX chassis and verify that it is operating correctly.
Appendix A, "Connector Pin Assignments". This appendix lists the interface connector
pinouts for the CHAMP-AV8.
Appendix B, "Statement of Memory Volatility". This appendix contains the Curtiss-Wright
“Certificate of Memory Volatility” and provides a description of the various types of memory
available on the CHAMP-AV8 hardware.
Appendix C, "Memory Write Protection". This appendix provides information and
procedures for hardware memory write protection.
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com
CHAMP-AV8 (VPX6-462) HARDWARE USER’SMANUAL CURTISS-WRIGHT
XIV PROPRIETARY 826448 VERSION 5MARCH 2015
DOCUMENTATION ROADMAP
The figure below will help you understand what documentation is available for the
CHAMP-AV8. These documents are provided in Portable Document Format (PDF) format
(readable by Adobe® Acrobat® Reader software), and are available from our Continuum
Support Center web site at:
http://csc.cwcdefense.com/
Figure 1: Documentation Roadmap
RELATED SOFTWARE DOCUMENTS
For information on installing the CHAMP-AV8 software, refer to the CHAMP-AV8 Linux BSP
Software User’s Manual, Curtiss-Wright document number 826449. Alternatively, installation
information can be found in the CHAMP-AV8 VxWorks BSP Software User’s Manual,
Curtiss-Wright document number 826452.
CHAMP-AV8
VPX Quad-core
Intel Core i7
DSP Board
Hardware User’s
Manual
826448
Contents:
- hardware functional description
- installation instructions
- detailed connector pinout info.
CHAMP-AV8 Hardware Documentation
Contents:
- information about the specific
hardware configuration of your
particular variant
CHAMP-AV8
Product Release
Notes
8xxxxx
CHAMP-AV8
VPX Quad-core
Core i7 DSP
Board
BIOS
Release Notes
826451
Contents:
- information about the most
recent CHAMP-AV8 BIOS
release.
CHAMP-AV8
VPX Quad-core
Core i7 DSP
Board
VxWorks BSP
Software User’s
Manual
826452
Contents:
- BSP overview
- BSP installation instructions
- Memory maps, usage
- Programming instructions
- BSP interface
CHAMP-AV8
VPX Quad-core
Core i7 DSP
Board
VxWorks BSP
Release Notes
826454
Contents:
- information about the most
recent CHAMP-AV8
VxWorks BSP release.
CHAMP-AV8
VPX Quad-core
Core i7 DSP
Board
Linux BSP
Software User’s
Manual
826449
Contents:
- BSP overview
- BSP installation instructions
- Memory maps, usage
- Programming instructions
- BSP interface
CHAMP-AV8
VPX Quad-core
Core i7 DSP
Board
Linux BSP
Release Notes
826453
Contents:
- information about the
most recent CHAMP-AV8
Linux BSP release.
CHAMP-AV8 Software Documentation
CHAMP-AV8
VPX Quad-core
Core i7 DSP
Board
BIOS Setup
Utility Software
User’s Manual
826450
Contents:
- information about the
BIOS software, how to
access it, etc.
- Card-level diagnostics
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com
CURTISS-WRIGHT
826448 VERSION 5MARCH 2015 PROPRIETARY XV
REFERENCE DOCUMENTATION
Refer to the following standards for information about the specifications the CHAMP-AV8 is
designed for compliance with:
• VITA 46.0-2007 - Advance Module Format, R1.2
• VITA 46.3 - 4x Serial RapidIO Signal Mapping for VITA 46, Revision 0.5
• VITA 46.4 - PCI Express Mapping and Advanced Switch Signal Mapping for VITA 46,
Draft 0.5
• VITA 46.9 - VITA 46 PMC/XMC Pinout Mapping, Revision 0.9
• VITA 46.10 - Rear Transition Module for VITA 46, Revision 0.08
• VITA 42.0 - XMC Specification, Revision 0.29
• VITA 42.3-2006 - XMC PCI Express Protocol Layer Standard
• VITA 48.0 - Enhanced Rugged Design Implementation, Draft 0.17
• VITA 48.1 - Air Cooling applied to VITA 46, Draft 0.20
• VITA 48.2 - Conduction Cooling applied to VITA 46, Draft 0.14
• VITA 65 - OpenVPX System Specifications, ANSI/VITA 65-2010
• PCI Express Base Specification Revision 2.1., March 4, 2009, PCI-SIG
• Interface Between Data Terminal Equipment and Data Circuit-Terminating Equipment
Employing Serial Binary Data Interchange, ANSI/TIA/EIA-232-F-1997, September 30,
1997
• RapidIO Interconnect Specification, Part IV: Physical Layer 1x/4x, LP Serial Specifica-
tion, Revision 1.2, June 2002
• Interface Between Data Terminal Equipment and Data Circuit-Terminating Equipment
Employing Serial Binary Data Interchange, ANSI/TIA/EIA-232-F-1997, September 30,
1997
• Electrical Characteristics of Balanced Voltage Digital Interface Circuits
(ANSI/TIA/EIA-422-B-1994) (R2000) (R2005), May 1994
• XMC PCI Express Protocol Layer Standard, ANSI/VITA 42.3-2006, 2006
• IEEE Standard for Information Technology, Part 3: Carrier Sense Multiple Access with
Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications, IEEE
802.3-2008, 2008
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com
CHAMP-AV8 (VPX6-462) HARDWARE USER’SMANUAL CURTISS-WRIGHT
XVI PROPRIETARY 826448 VERSION 5MARCH 2015
CONVENTIONS USED IN THIS MANUAL
This manual uses various icon conventions and abbreviations to make the information clearer
and easier to read. These conventions cover typography for such elements as sample software
code and keystrokes, signal meanings, and graphical elements for important information such
as warnings or cautions.
Product Naming
Conventions The generic product name “CHAMP-AV8” is used throughout this manual to represent the
following more specific product variants:
• VPX6-462-A (commercial non-ruggedized or air-cooled rugged version of the
CHAMP-AV8)
• VPX6-462-C (conduction-cooled rugged version of the CHAMP-AV8)
Typographic
Conventions Table 1 lists the typographical conventions used in this documentation package.
Signal
Conventions Table 2 lists symbols that can follow a signal name. For example, the asterisk (*) is used with
a VMEbus signal name, such as BERR*.
Abbreviations Table 3 on page xvii lists the abbreviations used to describe the size of a memory device or a
range of addresses.
Table 1: Typographic Conventions
Item Convention Example
Keystrokes Keys are listed as they appear on most keyboards,
surrounded by < > marks. Combinations of key-
strokes appear within a single set of < > brackets.
Type < Ctrl-Alt-C > to return to the previous menu.
Type < Esc > to exit.
File Names File names are set in italics. Copy the file named bootA.exe.
Directory Names Directory names show the full directory path. The
last directory in the path does not have a trailing
slash following it.
Go to the c:\windows\temp\backup directory.
Monitor Displays
and Code
Prompts and other text appearing on monitors is
set in monospace type (Lucida Console font).
Copyright (c) 2015, Curtiss-Wright
Controls, Inc.
Text entered Any information you need to enter is set in bold
monospace type (Lucida Console font).
yes
Monitor Com-
mands
Within paragraphs, monitor commands are shown
in bold face.
fwupd
Table 2: Signal Conventions
Symbol Description
_H The signal is active HIGH.
_L The signal is active LOW.
P The signal is the positive signal in a differential pair.
N The signal is the negative signal in a differential pair.
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com
CURTISS-WRIGHT
826448 VERSION 5MARCH 2015 PROPRIETARY XVII
Acronyms The following is a list of acronyms associated with the CHAMP-AV8 product:
AC Alternating Current
ANSI American National Standards Institute
AT Anti-Tamper
BIT Built-In Test
BMC Baseboard Management Controller
BT Base-T (Ethernet)
CBIT Continuous Built-In Test
CCA Circuit Card Assembly
CHF Common Hardware Features
CLD Card Level Diagnostics
CPU Central Processing Unit
DC Direct Current
DDIO Differential Discrete Input Output
DDR Double Data Rate
DIO Discrete Input Output
DMA Direct Memory Access
DVT Design Verification Test
ECC Error Correction Code
EEPROM Electrically Erasable Programmable Read Only Memory
EIA Electronic Industries Association
EMI Electro Magnetic Interference
EPROM Erasable Programmable Read Only Memory
FPGA Field Programmable Gate Array
GND Ground
GPIO General Purpose Input Output
HUM Hardware User’s Manual
I/F Interface
IBIT Initiated Built-in Test
I/O or IO Input/Output
IEEE Institute of Electrical and Electronic Engineers
Table 3: Memory Size Abbreviations
Abbreviation Convention
1 Kbyte 1,024 bytes
1 Mbyte 1,024 Kbytes
1 Gbyte 1,024 Mbytes
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com
CHAMP-AV8 (VPX6-462) HARDWARE USER’SMANUAL CURTISS-WRIGHT
XVIII PROPRIETARY 826448 VERSION 5MARCH 2015
IPMC Intelligent Platform Management Controller
IPMI Intelligent Platform Management Interface
JTAG Joint Test Action Group
LED Light Emitting Diode
LPB Local Processor Block
LPC Low Pin Count
MBSC Multi-Board Synchronous Clock
MTBF Mean Time Between Failures
NVRAM Non-Volatile Random Access Memory
PABS Permanent Alternate BOOT Site
PBIT Power-up Built-In Test
PCH Platform Controller Hub
PCI Peripheral Component Interconnect
PCIe PCI Express
PCISIG PCI Special Interest Group
PICMG PCI Industrial Computer Manufactures Group
PMC PCI Mezzanine Card
PROM Programmable Read-Only Memory
PSB Processor-Specific Block
PWB Printed Wiring Board
RAM Random Access Memory
RTM Rear Transition Module
SATA Serial ATA
SDRAM Synchronous Dynamic RAM memory
SHMUART Shared Memory UART
SPI Serial Peripheral Interface
SRAM Static Random Access Memory
SRIO Serial RapidIO
SSD Solid State Drive
TPM Trusted Platform Module
UART Universal Asynchronous Receiver/Transmitter
USB Universal Serial Bus
VITA VMEbus International Trade Association
VPD Vital Product Data
XMC Switched Mezzanine Card
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com
CURTISS-WRIGHT
826448 VERSION 5MARCH 2015 PROPRIETARY XIX
Memory
Addresses Unless otherwise stated, all memory addresses are shown in hexadecimal notation.
Icons The following icons are used throughout the documentation package:
Tip
Tips provide extra information on the subject matter. This could include hints about how to
use your current Curtiss-Wright card to its maximum potential.
Note
This is a note. The note icon highlights exceptions and special information.
Caution
This is a caution. The caution icon indicates non-catastrophic incidents, complex practices,
or procedures which, if not observed, could result in damage to the hardware. Cautions
include specific instructions for avoiding or minimizing these incidents.
Warning
This is a warning. The warning icon indicates procedures in the manual that, if not carried
out, or if carried out incorrectly, could cause physical injury, electrical damage to
equipment, or a non-recoverable corruption of data. Warnings include instructions for
preventing such damage.
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com
Table of contents
