DVC DigitEyes Series User manual

Technical Manual for
DVC’s DigitEyes Cameras
Manual Number: 86-0001-03
Release Date: December 29, 1996
DVC Company
7101 Midwood Parkway
Austin, TX 78736
Phone : [phone]
Fax No: 512-288-2961
e-mail: [email protected]
WWW: http://www.dvcco.com

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Table of Contents
1. INTRODUCTION:..............................................................................................................................1
2. CAMERA SPECIFICATIONS:..........................................................................................................2
2.1 OPTICAL ...........................................................................................................................................2
2.2 DIGITAL VIDEO OUTPUT ...............................................................................................................3
2.3 ANALOG VIDEO OUTPUT...............................................................................................................3
2.4 ELECTRICAL ....................................................................................................................................3
2.5 MECHANICAL ..................................................................................................................................3
3. DVC CAMERA FUNCTIONAL DESCRIPTION .............................................................................4
3.1 CCD SENSOR:......................................................................................................................................4
3.1.1 Integration:..................................................................................................................................4
3.1.2 Parallel Transfer:.........................................................................................................................4
3.1.3 Readout:.......................................................................................................................................4
3.2 VIDEO PRE-PROCESSING: ......................................................................................................................4
3.3 ANALOG VIDEO PROCESSING:...............................................................................................................5
3.4 VIDEO DIGITIZATION:...........................................................................................................................5
3.5 SYNC AND POWER BOARD: ...................................................................................................................5
4. TC-245 CCD DETAILS ......................................................................................................................6
4.1 TC-245 CCD FUNCTIONAL DETAILS ....................................................................................................6
4.2 FUNCTIONAL DESCRIPTION:.........................................................................................................8
4.2.1 Image Sensing and Storage Area:.................................................................................................8
4.2.2 Multiplexer with Transfer Gates and Serial Register:...................................................................8
4.2.3 Correlated-Clamp-Sample-and-Hold (CCSH) Amplifier with Charge Detection Nodes:..............10
5. DVC CAMERA OPTIONS AND SPECIAL MODIFICATIONS....................................................11
5.1 TYPICAL MODE CONTROL TABLES...........................................................................................11
5.1.1 “N” Field Integration, Pulse Driven Integration & Asynchronous Reset :..................................11
5.1.2 “N” Field Integration; 4 values of “N”, Two-speed Electronic Shutter, Pulse Driven Integration
& Asynchronous Reset: .......................................................................................................................12
5.2 ELECTRONIC SHUTTERING MODE:............................................................................................12
5.3 PULSE DRIVEN INTEGRATION MODE:.......................................................................................14
5.4 N FIELD INTEGRATION:...............................................................................................................15
5.5 ASYNCHRONOUS RESET AND GENLOCK ...............................................................................................17
5.5.1 Standard Mode:..........................................................................................................................17
5.5.2 Asynchronous Reset Mode:.........................................................................................................17
5.5.3 Genlock Mode:...........................................................................................................................18
5.6 GAIN AND OFFSET........................................................................................................................19
5.6.1 Standard Configuration:.............................................................................................................19
5.6.2 Manual External Gain Control:..................................................................................................19
5.6.3 Manual External Offset Control:................................................................................................20
5.6.4 Computer Driven External Gain Control:...................................................................................21
5.6.5 Computer Driven External Offset Control:.................................................................................22
5.6.6 Automatic Gain Control (AGC):.................................................................................................23
5.7 REMOTE CONTROL BOX:.............................................................................................................24
5.8 CUSTOM CABLE SPLITTER (“Y” CABLE): .............................................................................................25
5.9 GAMMA CORRECTION.........................................................................................................................27
5.9.1 Definition:..................................................................................................................................27
5.9.2 Gamma Equations:.....................................................................................................................27

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5.9.3 Fixed Gamma Settings in DVC Cameras:...................................................................................28
5.9.4 Adjustable Gamma Setting in DVC Cameras:.............................................................................28
5.10 ACCESS PORTS : ..........................................................................................................................29
5.10.1 Access port for analog gain control :........................................................................................29
5.10.2 Access port for analog offset control:.......................................................................................29
5.10.3 Access port for digital gain control:.........................................................................................29
5.10.4 Accesss port for digital offset control:......................................................................................30
5.10.5 Access port for adjustable analog Gamma control :..................................................................30
6. DVC CAMERA IMAGE PROCESSOR COMPATIBILITY..........................................................30
6.1 IBM (PCI).........................................................................................................................................30
6.2 IBM-PC ............................................................................................................................................31
6.3 MAC (PCI) .......................................................................................................................................31
6.4 VME.................................................................................................................................................31
6.5 SUN (S-BUS)....................................................................................................................................31
6.6 SGI DIGITAL......................................................................................................................................31
7. ORDERING INFORMATION & MODEL INDEX ........................................................................32
7.1 DVC “DIGITEYES” CAMERA MODEL INDEX................................................................................32
8. FREQUENTLY ASKED QUESTIONS (ADAPTED FROM DVC’S WWW SITE) ..................33
8.1 PRODUCT INFORMATION ............................................................................................................33
8.1.1 What is the "DigitEyes" product series? .....................................................................................33
8.1.2 What are the differences between the DVC-0A, DVC-08 and DVC-10 products? ........................33
8.1.3 I've heard your cameras described as "upgradeable". What does that mean to the user?............33
8.1.4 What kind of a warranty is available on DVC products?.............................................................34
8.1.5 Are your cameras available in board form for OEM applications?.............................................34
8.2 SYSTEM ISSUES.............................................................................................................................34
8.2.1 What is the minimum system configuration I need to use DVC cameras?....................................34
8.2.2 Should I use a digital or an analog camera?...............................................................................35
8.2.3 What are the benefits of using a digital camera?........................................................................35
8.2.4 Do I need a frame grabber to use digital cameras? ....................................................................36
8.2.5 How should I go about selecting a frame grabber for my application?........................................36
8.2.6 Do I need to cool the camera?....................................................................................................36
8.3 PRODUCT FEATURES....................................................................................................................37
8.3.1 What is the single, most important reason to buy a DVC camera vs. the "competition"?.............37
8.3.2 Can you define the term signal-to-noise ratio ?..........................................................................37
8.3.3 How are Signal-to-Noise Ratio (SNR) and sensitivity related?....................................................38
8.3.4 How do the DVC cameras compare with the "mega-pixel" cameras ?.........................................38
8.3.5 Do I need a digital output camera to benefit from the higher signal-to-noise ratio of DVC
cameras?.............................................................................................................................................39
8.3.6 What is the best way to "benchmark" the DVC camera vs. the “competition" in a side-by-side
comparison?........................................................................................................................................39
8.3.7 What is meant by Equivalent Number of Bits (ENOBs) ? ............................................................39
8.3.8 How does the signal-to-noise ratio (in dB) relate to Equivalent Number of Bits (ENOBs)?.........40
8.3.9 Why would I need to control the Gain of the Camera in my application?....................................40
8.3.10 How is the “Back Focus distance” set on DVC’s DigitEyes cameras ?.....................................41
8.3.11 How do I access the user adjustable controls?..........................................................................42
8.3.12 What user adjustable controls are available within the camera?...............................................43
8.4 CCD RELATED QUESTIONS .........................................................................................................45
8.4.1 What CCD sensor is used in the “DigitEyes” cameras? Who manufactures it ?..........................45
8.4.2 What other kinds of CCD sensors are out there ?........................................................................45
8.4.3 How do Frame Transfer CCDs compare with Interline Transfer CCDs?.....................................45
8.4.4 What is meant by the dynamic range of a CCD ?........................................................................46

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8.4.5 What is the image format of the CCD ? ......................................................................................47
8.4.6 What is meant by pseudo-interlaced operation ?.........................................................................47
8.4.7 Can the pseudo-interlaced operation be disabled ? ....................................................................48
8.4.8 What is anti-blooming ?..............................................................................................................48
8.4.9 Can anti-blooming be disabled ?................................................................................................50
8.4.10 What is meant by integration time ?..........................................................................................50
8.4.11 What is the integration time in the standard mode of operation ? .............................................50
8.5 OPTIONS .........................................................................................................................................51
8.5.1 What non-standard modes of integration are available ?............................................................51
8.5.2 What is the difference between electronic shuttering and pulse driven integration ?...................51
8.5.3 Do I need a frame grabber for non-standard integration modes ?...............................................51
8.5.4 What is the image format (size) during electronic shuttering and pulse driven integration ?.......51
8.5.5 Can I use genlock/asynchronous reset & electronic shuttering simultaneously ?.........................51
8.5.6 What is genlock and how does it work ?......................................................................................51
8.5.7 What is auto-iris and how does it work ?.....................................................................................52
8.5.8 What is GAMMA - it sounds like Greek to me ?..........................................................................52
8.5.9 What options are available to control the Digital Video gain and offset ?...................................52
9. APPENDIX A: CAMERA CONNECTOR INFORMATION..........................................................53
9.1 PIN ASSIGNMENTS FOR THE DB-37 DIGITAL VIDEO CONNECTOR..........................................................53
9.2 PIN ASSIGNMENTS FOR THE POWER SUPPLY CONNECTOR......................................................................53
9.3 CONNECTOR PART NUMBERS...............................................................................................................53
10. APPENDIX B: CAMERA TIMING DIAGRAM...........................................................................54
11. APPENDIX C: CAMERA SCHEMATIC DIAGRAM ..................................................................55
12. APPENDIX D: CAMERA MECHANICAL DRAWINGS.............................................................56
13. APPENDIX E: CAMERA PERFORMANCE DATA (VM-700A PLOTS) ...................................57
14. WARRANTY: .................................................................................................................................61

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List of Figures
FIGURE 2-1: CAMERA SPECTRAL RESPONSE................................................................................................2
FIGURE 3-1: DIGITAL CAMERA BLOCK DIAGRAM.........................................................................................4
FIGURE 4-1: TC-245 BLOCK DIAGRAM (TEXAS INSTRUMENTS, 1994).......................................................6
FIGURE 4-2: TC-245 MECHANICAL DRAWING (TEXAS INSTRUMENTS, 1994) ............................................7
FIGURE 4-3: TC-245 GATE LEVEL DRAWING (TEXAS INSTRUMENTS, 1994)..............................................9
FIGURE 4-4: TC-245 CCSH AMPLIFIER CIRCUIT (TEXAS INSTRUMENTS, 1994)......................................10
FIGURE 5-1: SHUTTER MODE TIMING DIAGRAM ........................................................................................12
FIGURE 5-2: SHUTTER MODE DETAILS (VERTICAL BLANKING INTERVAL)...................................................13
FIGURE 5-3: PULSE DRIVEN INTEGRATION MODE ......................................................................................14
FIGURE 5-4: "N" FIELD INTEGRATION MODE.............................................................................................15
FIGURE 5-5: ASYNCHRONOUS RESET MODE TIMING DIAGRAM...................................................................17
FIGURE 5-6: MANUAL EXTERNAL GAIN CONTROL CURVE..........................................................................19
FIGURE 5-7: MANUAL EXTERNAL OFFSET CONTROL CURVE.......................................................................20
FIGURE 5-8: EXTERNAL GAIN CONTROL CURVE ........................................................................................21
FIGURE 5-9: EXTERNAL OFFSET CONTROL CURVE.....................................................................................22
FIGURE 5-10: REMOTE CONTROL BOX (TOP VIEW)....................................................................................24
FIGURE 5-11: TYPICAL APPLICATION USING THE SPLITTER..........................................................................25
FIGURE 5-12: GAMMA CORRECTION CURVES.............................................................................................27
FIGURE 5-13: ACCESS PORTS (TOP VIEW)..................................................................................................29
FIGURE 8-1: SKETCH SHOWING CAMERA BOARDS ......................................................................................43
FIGURE 8-2: VIDEO BOARD ADJUSTMENTS................................................................................................44
FIGURE 8-3: EXPOSURE CURVE SHOWING THE DYNAMIC RANGE OF THE CAMERA .......................................46
FIGURE 8-4: IMAGING AREA, SHOWING PSEUDO-INTERLACED OPERATION...................................................47
FIGURE 8-5: ANTI-BLOOMING CURVE ........................................................................................................49
FIGURE 9-1: POWER SUPPLY CONNECTOR PINOUT DIAGRAM......................................................................53
FIGURE 10-1: CAMERA TIMING DIAGRAM..................................................................................................54
FIGURE 11-1: CAMERA SCHEMATIC DIAGRAM ............................................................................................55
FIGURE 12-1: CAMERA MECHANICAL DRAWINGS ......................................................................................56
FIGURE 13-1: CAMERA NOISE SPECTRUM (MIN. GAIN, BANDWIDTH = 10KHZ TO FULL)..............................57
FIGURE 13-2: CAMERA NOISE SPECTRUM (MIN. GAIN, BANDWIDTH = 10KHZ TO 4.2MHZ).........................58
FIGURE 13-3: CAMERA NOISE SPECTRUM (MAX. GAIN, BANDWIDTH = 100KHZ TO 4.2MHZ) ......................59
FIGURE 13-4: CAMERA NOISE SPECTRUM (MAX. GAIN, BANDWIDTH = 10KHZ TO FULL).............................60
List of Tables
TABLE 5-1: "Y" CABLE: PINOUT OF CAMERA SIDE DB-37 CONNECTOR (MARKED "C") ................................25
TABLE 5-2: "Y" CABLE: PINOUT OF REMOTE BOX DB-37 CONNECTOR (MARKED "R").................................26
TABLE 5-3: "Y" CABLE: PINOUT OF DIGITAL DB-37 CONNECTOR (MARKED "D").......................................26
TABLE 7-1: DVC-0A ORDERING EXAMPLE ...............................................................................................32
TABLE 7-2: DVC-10 ORDERING EXAMPLE................................................................................................32
TABLE 9-1: PIN ASSIGNMENTS FOR THE DB-37 (FEMALE) DIGITAL VIDEO CONNECTOR..............................53
TABLE 9-2: POWER SUPPLY CONNECTOR (5 PIN DIN)................................................................................53
TABLE 9-3: CONNECTOR PART NUMBERS & MATING PART INFORMATION...................................................53

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1. Introduction:
DVC Company, a San Diego, California based manufacturer of cost-effective, rugged video
cameras, thanks you for purchasing from the “DigitEyes" series of digital and analog video
cameras.
This series of cameras is based on the premise that to-day's high-end image processing
applications DEMAND cameras that are designed for the maximum accuracy and repeatability
that can be achieved with to-day's CCDs. DVC's moderately priced cameras occupy a niche
BETWEEN the low-end "security and surveillance" cameras which are inexpensive but
inaccurate, and the expensive, non real-time, high resolution cameras that might be "overkill" for
many applications.
The 30 frames/sec video data is provided as 10 or 8 bit parallel, differential RS-422 data which is
"plug-and-play" compatible with industry-standard image processors and a simultaneous RS-170
composite video signal (Signal-to-Noise ratio ≥62 dB @ 0.5 lux, 100 IRE ). The digital data,
pixel clock, enable line, enable frame and field index signals are accessible via DB-37
connector. Manual (or remote) external gain / offset or Automatic Gain Control (AGC) functions
that can provide nearly 30 dB of gain are available with the RS-170 output to "tune" the dynamic
range of the camera to the application. This provides an optimum match between the dynamic
range & sensitivity of the camera and the requirements of the application - in some cases,
optimum imagery is obtained under low-light conditions in real time (30 frames per second)
without an external image intensifier !
The TC-245 CCD imager has a 755(H) X 484(V) interlaced image format and has on-chip
correlated clamp sample & hold circuitry that minimizes noise. The CCD has a full well of
>80,000 electrons and a noise floor of <30 electrons (at 25°C). It has no "dead" pixels or
"blemishes" that are found in low-end security and surveillance CCD cameras.
The CCD is physically mounted in a cavity within a high-precision opto-mechanical plate to
eliminate the stability problems that are caused by using imprecisely aligned cameras in high-
end applications. On-camera digitization using the CCD pixel clock eliminates pixel jitter,
improves repeatability and brings sub-pixel accuracy to image processing applications.
The DVC-0A (analog only RS-170 model) is upgradeable to the DVC-08 or DVC-10 models
which are 8 or 10 bit digital RS-422 cameras with simultaneous RS-170 output. The camera can,
literally, "grow" with your application ! Shuttering, Pulse driven integration, cooling to -25°C,
genlock (for multiple camera synchronization, removal of the sensor faceplate for UV
applications are options that are available upon request. All DVC cameras come with a standard
2 year warranty and use industry-standard C-mount lenses.
In today's state-of-the-art digital video applications, the parallel 8 or 10 bit digital data can be
serialized and transmitted via fiber optic cable or over other channels. This is achievable without
any degradation of the signal quality over long distances.
This manual applies to all three of the DigitEyes cameras. Since the Analog Video Output is
common to all three cameras, any reference to the Analog Video Output applies equally to all
three cameras. References to the Digital Video Output applies only to the DVC-08 and DVC-10
cameras.

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2. CAMERA SPECIFICATIONS:
2.1 OPTICAL
Optical Filtering IR filter (optional; see Figure 2-1 & 2-3)
Spectral Response See Figure 2-1, 2-2 and 2-3
Sensitivity (without IR filter) @ 2850°K 0.5 Lux (0.05 fc) @ CCD for 100 IRE video
(Signal-to-Noise Ratio ≥62 dB)
Figure 2-2: TC-245 CCD Spectral Responsivity Curve (Texas Instruments, 1994)
S pectral response inVisible region
(UV res pons e obs erved to 200nm with CCD faceplate removed;
IR Responseobservedto1100nm)
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
Wavelength(nm)
WithoutIR Filter
With IR Filter
Figure 2-1: Camera Spectral Response

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2.2 DIGITAL VIDEO OUTPUT
Digital Video Output (14.31818 Mbytes/sec) Ten or Eight bit parallel differential (RS-422)
Gamma 1.0 (linear)
AGCNone
2.3 ANALOG VIDEO OUTPUT
RS-170 Composite Video : 1Vp-p; 75ΩResolution: 565 TVL (H); 350 TVL (V)
Gamma (set at the factory) 0.45 (standard); 0.6 (optional); 1.0 (optional)
AGC (set at the factory) None (standard); 30 dB (optional)
Signal to Noise Ratio (no AGC, Gamma = 1) ≥62 dB (See VM-700 plots; Appendix E)
2.4 ELECTRICAL
Timing RS-170, 2:1 Interlaced
Power Supply Voltages &
Current requirements ±12 V DC each @ 250 mA steady state
+ 5 V DC @ 250 mA steady state.
Clock Rate 14.31818 MHz
Synchronization Internal crystal @ 14.31818 MHz
Genlock (Optional) Reverts to crystal lock w/o External Sync.
2.5 MECHANICAL
Weight (without lens) 1 lb. (approx.)
Temperature limits (operating) -10°C to 50°C
Temperature limits (storage) -30°C to 70°C
Dimensions 4¾" X 3¾" X 2½"
Lens mount Industry standard C- mount
Camera mount ¼ - 20 threaded hole
Digital Video Connector DB-37, female connector (See Appendix A)
Power Supply Connector 5 pin DIN connector (see Appendix A)
Analog Video Connector BNC female connector
IR FilterSpecifications
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
350400450500550600650700750800850
Wavelength (nm)
Transmission (%)
Figure 2-3: IR Filter Characteristics

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3. DVC Camera Functional Description
3.1 CCD Sensor:
Light from the scene is brought into focus at the imaging plane of the CCD. An optical block
(optional) filters out the IR component of the light.
The following functions take place within the CCD:
3.1.1 Integration:
During the integration period (1/60 sec.), charges are integrated in the active pixel wells of the
Imaging Area. The amount of charge that is integrated in each active pixel well is proportional to
the illumination received at each active pixel site on the CCD. Anti-blooming pulses during the
horizontal and vertical blanking areas trigger the anti-blooming gates that are an integral part of
the active pixel elements.
3.1.2 Parallel Transfer:
During the Vertical Blanking interval, the entire charge matrix that was integrated in the previous
field (1/60 sec) is shifted to the opaque storage area of the CCD. This is accomplished by a
series of 242 pulses, each of which causes the charge matrix to shift down by one line. This
process takes approximately 68µsec.
3.1.3 Readout:
In the following field, the charges are transferred from the storage area of the CCD to on-chip
serial shift registers and then sequentially to the detection nodes where they are made available
as signal voltages. Note: While one field is being read out from the Storage Area, the other field
is being integrated in the Imaging Area of the CCD.
3.2 Video Pre-processing:
The low-level video signal voltage from the CCD is fed through a high-speed sample-and-hold
amplifier, clamped (for black reference) and amplified before further video processing. It is in
CCD Sensor
3 Channel
S/H 3 Channel pre- amplifier:
Gain
Clamping
White Balance
Black Balance
3 : 1
Analog
multiplexer
Digital Video Amp:
Digital Gain
Digital Offset
Video Processor:
Gain & Offset
Gamma
Sync Insertion
(optional)
AD-10 or AD-08
board:
Analog/Digital
conversion
TTL to RS-422
drivers:
single ended TTL
to parallel,
differential, RS-
422
Linear Voltage
Regulators
Imaging
Area
Storage
Area
Timing and control logic:
Clock generation
Generation of all CCD control signals
Genlock PLL (optional)
Exposure control
Sensor and Video Board
Sync & Power Board
Analog to Digital Board
RS-170 Output
Processed
Analog Video
Multiplexed
Analog Video
Pre-amp
Video
CCD
Video
Serial
Parallel
S/H signals Clamp Multiplex signals Clock
Clock, Enable Line, Enable Frame, Field
Id
+12V, -12V, +5V
DIN Connector
(Power Supply)
DB-37
connector
(Digital Video)
Digital Video
(8 or 10 bits)
Serial
Driver
Parallel
Driver
Figure 3-1: Digital Camera Block Diagram

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this section that the three channels of video must be "equalized" before they can be multiplexed
into a single channel of video. In order to accomplish this, two channels are provided with
variable gain and offset; one channel (considered the reference channel) has a fixed gain and
offset. The two variable channels are adjusted by means of the White Balance and Black
Balance potentiometers until all the three channels are properly matched.
3.3 Analog Video Processing:
The signal from the pre-processor stage is fed to the Video Processor which performs the
following functions related to the Analog (RS-170) video:
• Gamma Correction
• Gain and Offset Control
• AGC & Auto-iris (optional)
• Sync Insertion - the Composite Sync signal is added to the Output Video Signal to create
Composite Video.
• Video Output Driver - The Video Processor is directly capable of driving a 75Ωco-axial
cable. It is recommended that the cable be terminated in its characteristic impedance of 75Ω
at the receiving end (the monitor or other receiving device).
3.4 Video Digitization:
The low-level video signal voltage from the pre-processor is clamped (for black reference) and
amplified on the Sensor & Video Board before Analog-to-Digital conversion (on the optional
Analog to Digital board). The Digital Video Data is latched and converted to an RS-422 format
for transmission as a balanced, differential signal along a cable which consists of shielded
twisted pairs.
3.5 Sync and Power Board:
This board performs the following functions:
• Voltage Regulation: Input voltages (+12V, -12V and +5V) are converted into several positive
and negative voltages required by the CCD and in the video processing circuits.
• Generation of CCD timing signals
• Generation of Video timing signals
• Asynchronous Reset function
• Genlock function
• Electronic Shutter function
• Pulse Driven Integration function
• TTL to RS-422 conversion of digital video data, and all handshaking signals (clock, csync,
field index, enable line & enable frame).

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4. TC-245 CCD Details
Note: This information has been derived from the Texas Instruments Databook Titled "Area Array
Image Sensor Products".
 Texas Instruments 1994
• Frame Transfer CCD Technology. Contiguous pixels for 100% fill factor. No "dead space"
between pixels.
• 755 (H) X 242 (V) active picture elements per field.
• Interlaced operation doubles effective vertical resolution; Image format is 755(H) X 484(V)
• 8.5µm (H) X 19.75µm (V) pixel size.
• On-chip correlated-clamp sample & hold circuits to minimize noise.
• On-chip shielded pixels provide "dark pixel" level for black level reference.
• 8 mm. image diagonal, compatible with ½ " optics.
• High sensitivity; unlike Interline Transfer CCDs which have "dead spaces" that lower
sensitivity.
• Solid state reliability with no image burn-in, residual imaging, image distortion, lag or
microphonics
• Minimum 100:1 blooming overload ratio (with Interlace on).
• 70 dB sensor dynamic range. Full well >80,000 electrons; Noise equivalent signal <30
electrons (typical 20 electrons)
• High photo-response uniformity; <5% photo-response-non-uniformity guaranteed (typical
<2%); blemish free sensor.
4.1 TC-245 CCD Functional Details
The TC-245 is a frame transfer charge coupled device (CCD) image sensor designed for use in
single chip B/W NTSC TV applications. The device is intended to replace a 1/2 inch vidicon tube
in applications requiring small size, high reliability and low cost.
Figure 4-1: TC-245 Block Diagram (Texas Instruments, 1994)

7
The Image Sensing area of the TC-245 is configured into 242 lines with 786 elements in each
line. 29 elements are provided in each line for dark reference. The blooming protection feature of
the sensor is based on recombining excess charge with charge of opposite polarity in the
substrate. This Anti-blooming is activated by supplying clocking pulses to the anti-blooming gate,
an integral part of each image-sensing element. The sensor is designed to operate in an
interlace mode, electronically displacing the image sensing elements in alternate fields by 1/2 of
a vertical line during the charge integration period, effectively increasing the vertical resolution
and minimizing aliasing. The device can also be operated as a 755(H) X 242(V) non-interlaced
sensor with significant reduction in the dark signal.
A gated floating-diffusion detection structure with an automatic reset and voltage reference
incorporated on-chip converts charge to signal voltage. The signal is further processed by a low-
noise, state-of-the-art correlated clamp-sample-and-hold circuit. A low-noise two-stage, source
follower amplifier buffers the output and provides high output drive capability. The image is
readout through three outputs, each of which reads out every third image column.
The TC-245 is built using TI-proprietary virtual-phase technology, which provides devices with
high blue response, low dark signal, good uniformity and single-phase clocking. The TC-245 is
characterized for operation from -10°C to 45°C.
Figure 4-2: TC-245 Mechanical Drawing (Texas Instruments, 1994)

8
4.2 FUNCTIONAL DESCRIPTION:
The TC-245 consists of four basic functional blocks:
1. Image-sensing area
2. Image-storage area
3. Multiplexer block with serial registers and transfer gates
4. The low-noise signal processing amplifier block with charge detection nodes.
The location of each of these blocks is identified in the functional block diagram.
4.2.1 Image Sensing and Storage Area:
As light enters the silicon in the image sensing area, free electrons are generated and are
collected in the potential wells of the sensing elements. During this time, blooming protection is
activated by applying a burst of pulses to the anti-blooming gate inputs every horizontal blanking
interval. This prevents blooming caused by the spilling of charge from over-exposed elements
into neighboring elements. After Integration is complete, the signal charge is transferred into the
storage area.
There are 29 1/2 columns of elements at the right edge of the image-sensing area that are
shielded from incident light; these elements provide the dark reference used in subsequent video
processing circuits to restore the video black level. There are also 1 1/2 columns of light shielded
elements at the left edge of the image-sensing area and two lines of light-shielded elements
between the image-sensing and image-storage areas (the latter prevent charge leakage from the
Image sensing into the Image storage area.
4.2.2 Multiplexer with Transfer Gates and Serial Register:
The Multiplexer and transfer gates transfer charge line-by-line from the storage-area columns
into the corresponding serial registers and prepare it for readout. The multiplexer vertically
separates the pixels for input into the serial registers. Multiplexing is activated during the
horizontal blanking interval by applying appropriate pulses to the transfer gate and the serial
registers.

9
Figure 4-3: TC-245 Gate Level Drawing (Texas Instruments, 1994)

10
4.2.3 Correlated-Clamp-Sample-and-Hold (CCSH) Amplifier with Charge
Detection Nodes:
Charge is converted into a video signal by transferring the charge onto a floating diffusion
structure in detection node 1 that is connected to the gate of a MOS transistor Q1. The
proportional charge-induced signal is then processed by the circuit shown above.
This circuit consists of a low pass filter formed by Q1 and C2, coupling capacitor C1, dummy
detection node 2, which restores the DC bias on the gate of Q3, sampling transistor Q5, holding
capacitor C3, and output buffer Q6. Transistors Q2, Q4 and Q7 are current sources for each
corresponding stage of the amplifier. The parameters of this high-performance signal processing
amplifier have been optimized to minimize noise and maximize the video signal.
The signal processing begins with a reset of detection node 1 and a restoration of the DC bias on
the gate of transistor Q3 through the clamping function of dummy detection node 2. After the
clamping is completed, the new charge packet is transferred onto detection node 1. The resulting
signal is sampled by the sampling transistor Q5 and is stored on the holding capacitor C3. This
process is repeated periodically and is correlated to the charge transfer in the registers. The
correlation is achieved automatically since the same clock lines used in shift registers S2 and S3
for charge transport serve for reset and sample. The multiple use of the clock lines significantly
reduces the number of signals required to operate the sensor. The amplifier also contains an
internal reference voltage generator that provides the reference bias for the reset and clamp
transistors. The detection nodes and the corresponding amplifiers are located some distance
away from the edge of the storage area. Therefore 11 dummy elements are incorporated at the
end of each serial register to span the distance. The location of the dummy elements, which are
considered to be a part of the amplifier is shown in the block diagram.
The above sequence of events helps to remove the noise (called kTc noise) that would otherwise
have been introduced due to the "floating" node. By clamping it to a "known" reference between
pixel values, and then charging it with the "delta" or the difference of potential due to the new
pixel value, a significant source of noise is removed.
Figure 4-4: TC-245 CCSH Amplifier Circuit (Texas Instruments, 1994)

11
5. DVC Camera Options and Special Modifications
• Electronic Shutter (1/1000 sec OR 1/2000 sec)
• Pulse Driven Integration Control
• “N” Field Integration: user specified value of “N”
• Asynchronous Reset Capability
• Genlock Option for multiple camera synchronization
• Gain & Offset Control
• Gamma Correction Options on the Analog Video Output
• Access ports for analog & digital gain/offset as well as for variable gamma control
• External Thermo-electric Cooler
• User Defined Optical Filter
• Board Level Cameras (for OEMs)
• Silicon Graphics Inc (SGI) INDY & INDIGO2 Digital Compatibility - Call DVC for an update !
• Electronically tunable (350nm to 1100nm) solid state LCD filter with fast switching for
sequential RGB and other multi-spectral applications; Call DVC for info !
• Serial Digital Video (for transmission via fiber optic, RF or twin co-ax)
5.1 TYPICAL MODE CONTROL TABLES
Some typical examples of mode control tables are shown the the next two sections. The actual
table in a particular camera depends upon the combination of options that are ordered. Note:
since the Mode Control 1 (MC1 or DB37-pin37) and the Mode Control 0 (MC0 or DB37-pin18)
are often used for the external analog video gain and offset control voltages, units that have
these external options selected are limited in the number of exposure control options that are
provided. In some cases, a special auxillary connector may be provided on the camera side
panel to increase the number of “mode control” inputs.
5.1.1 “N” Field Integration, Pulse Driven Integration & Asynchronous Reset :
DB37
- 19 DB37 -37
MC2 MC1 Mode Reset
0 0 Normal (Default: 1/60sec, Integ. period = 16.66ms) ↓edge
0 1 “N” Field Integ. (N = 60); Integ. period = 1 second inactive
1 0 Pulse driven integ. (Reset LOW sets Integ. period) ¯ |____| ¯
1 1 Normal (Default: 1/60sec, Integ. period = 16.66ms) ↓edge
Since all Mode Control (MC) and RESET pins are internally pulled up, the unit defaults to the
normal (1/60sec) mode until a pin is pulled LOW (via a computer, or by connecting it to ground).
Note: If a remote control box (with mode selection) is plugged in, the switch position
should be set to “NORMAL” before any of the Mode control pins is pulled LOW (via the
DB37 connector) by a computer or an external device other than the remote control box.

12
5.1.2 “N” Field Integration; 4 values of “N”, Two-speed Electronic Shutter, Pulse
Driven Integration & Asynchronous Reset:
DB-37 pins
19 37 18
MC2 MC1 MC0 Mode Reset pin 17
0 0 0 “N” Field Integration (N = 2) Integ. period = 33.33ms inactive
0 0 1 “N” Field Integration (N = 4) Integ. period = 66.66ms inactive
0 1 0 “N” Field Integration (N = 6) Integ. period = 99.99ms inactive
0 1 1 “N” Field Integration (N = 12) Integ. period = 199.99ms inactive
1 0 0 Shutter (1/1000 sec, Integration period = 1.0ms) inactive
1 0 1 Shutter (1/2000 sec, Integration period = 0.5ms) ↓edge
1 1 0 Pulse driven integ. (Reset duration sets Integ. period) ¯ |____| ¯
1 1 1 Normal (Default: 1/60sec, Integration period = 16.66ms) ↓edge
Since all Mode Control (MC) and RESET pins are internally pulled up, the unit defaults to the
normal (1/60sec) mode until a pin is pulled LOW (via a computer, or by connecting it to ground).
5.2 ELECTRONIC SHUTTERING MODE:
For integration periods less than 1/1000 sec, the following process (called electronic
shuttering) is carried out.
At the beginning of the Vertical Blanking Interval, the CCD is flushed by means of two charge
transfers. This takes approximately 140µsec. After the two "clearing" transfers, the Integration
Period begins. Before the end of the Vertical Blanking Interval, however, a "readout" transfer
takes place. The period between the two clearing transfers and the third (readout) transfer is the
Integration Period; it's duration is dependent on the user selected speed of the shutter (1/1000
sec or 1/2000 sec).
The following active field is used to read out the charge that was integrated in the Imaging Area
during the Integration Period. By completing the entire Integration Period within the Vertical
Blanking Interval, the electronic shuttering process can be done without disturbing the normal
sync and timing of the camera.
Shutter Mode
R
eadou
t EVEN FIELD
S
h
u
tt
e
r
ed
Im
age
TRANSFER PULSE
INTEG.
ODD
FIELD
CCD FLUSH PERIOD = 140us
Readout ODD FIELD
Shuttered Ima
g
e
ODD FIELD
1/60 sec
EVEN FIELD
1/60 sec
INTEG.
EVEN
FIELD
INTEG.
ODD
FIELD
SHUTTER DURATION = 1/1000s OR 1/2000s
EVEN FIELD
VERTICAL
BLANKING
INTERVAL
VERTICAL
BLANKING
INTERVAL
VERTICAL
BLANKING
INTERVAL
Figure 5-1: Shutter Mode Timing Diagram

13
Since the pseudo-interlacing is enabled during this mode, two distinct fields are obtained. For a
stationary object in the field-of-view, this produces two interlaced fields; or full vertical resolution.
Since the two integration periods are 1/60 sec apart, any movement in the field-of-view between
the two integration periods will be seen as inter-field flicker.
Therefore, if shuttering is used to "stop" motion, only one field (or half the normal vertical
resolution) per integration period is usable. If shuttering is used for exposure control and the
field-of-view is static (relative to the 1/60 sec between successive exposures), full vertical
resolution is available.
Both the Genlock and the Asynchronous Reset options have been found to work successfully
with the shutter mode, although the “slowest” shutter speed obtainable with Genlock or
Asunchronous Reset is approximately 600µsec (instead of 1/1000 sec).
Figure 5-2: Shutter Mode Details (Vertical Blanking Interval)

14
5.3 PULSE DRIVEN INTEGRATION MODE:
For integration periods greater than 1/1000 sec, the following process (called Pulse Driven
Integration) is followed. The camera operates in the standard mode (Integration Period = 1/60
sec) as long as all the mode control pins are High. Due to internal pull-up resistors, this is the
default mode.
If the Integration mode is selected (see mode selection table), then the falling edge of the
RESET input (pin 17 of the DB-37 connector) signal initiates the INTEGRATION MODE
sequence.
INTERRUPTED FIELD M FIELDS
Interru
p
ted Field
Inte
g
ration Mode
INTEGRATION PULSE
M * 1/60s
FIELD
(
N-2
)
1/60 sec
READOUT FIELD
(
N
)
1/60 sec
(
N+1
)
1/60 sec
(
N-1
)
INT
(
N+2
)
1/60 sec
Video
S
y
nc
Readout
(
N
)
EVEN FIELD
Inte
g
rated Ima
g
e
INTEGRATION PERIOD = DURATION OF PULSE - CCD FLUSH PERIOD
TRANSFER PULSE
CCD FLUSH PERIOD
Reset
Video Blanked
Enable Frame Enable Frame Enable Frame Enable Frame
Enable Line Enable Line Enable Line Enable Line
Video Blanked
Figure 5-3: Pulse Driven Integration Mode
The CCD is flushed by means of two quick, successive transfers. This takes approximately
140µsec. At the end of this period, the Integration Period begins.
When the RESET signal returns HIGH (rising edge), a vertical reset is generated. This resets the
Vertical Counter in the Camera; image transfer and readout begin immediately.
The total integration time is therefore can be computed as follows:
Tint = (Duration of the Low RESET pulse) - (CCD flush period)
OR
Tint = (Duration of the Low RESET pulse) - 140µsec

15
Note(s):
(1) Only one field (or half the normal vertical resolution) per integration period is obtained.
(2) Since charge transfer is initiated only when the RESET pulse is asserted (LOW), there is no
image generated by the camera except the one field due to each INTEGRATION
sequence.Therefore the monitor screen remains blank, until the next INTEGRATION sequence
is initiated by the next falling edge of RESET.
(3) The Pulse Driven Integration mode is designed for applications where the user has complete
control of the integration period. When the Pulse Driven Integration mode is selected (using the
Mode Control bits), the CCD does NOT integrate charge until the RESET pulse is asserted LOW.
Therefore, as long as RESET is HIGH, the camera does NOT produce an image. However, clock
and sync. are generated, so that a frame grabber (or image processor) can be in synchronization
with the camera. The Enable Frame and Enable Line signals are also generated. Since the
camera does not produce an image while it is waiting for an active LOW RESET pulse, any
frames of video data that are captured (or viewed on a monitor) during this waiting period will be
black.
(4) When the RESET pulse transitions (HIGH to LOW) the CCD is flushed (cleared of charge) by
means of two quick, successive charge transfers. As soon as the CCD is flushed, the active
integration period begins. This period lasts as long as the RESET pulse is LOW. During this
period, the Enable Frame and Enable Line signals are NOT asserted, since no active video is
being generated while the integration takes place.
(5) When the RESET pulse transitions (LOW to HIGH) the final “readout” transfer takes place.
The timing chip is also reset to line 6 of the ODD field (simultaneous to the readout transfer in
the CCD). Active video is output starting at line 20 (standard RS-170 format). The Enable Frame
and Enable Line signals are generated, beginning at line 20. This is the image of the scene that
was integrated on the CCD during the LOW duration of the RESET pulse.
(6) There is no lower or upper theoretical limit to the integration period. In reality, the upper limit
is determined by the amount of noise that can be tolerated and the dynamic range required by
the application. The lower limit is determined by the amount of light during image transfer and
the amount of smear that can be tolerated by the application. Cooling the CCD will result in
longer usable integration periods due to a reduction in the dark current of the CCD.
5.4 N FIELD INTEGRATION:
If the N Field Integration mode is selected, the following sequence is followed.
Figure 5-4: "N" Field Integration Mode
The CCD is flushed by means of two quick, successive transfers. This takes approximately
140µsec. At the end of this period, the Integration Period begins.