Dynamic Engineering PCI3IP-Minimap User manual

DYNAMIC ENGINEERING
435 Park Dr., Ben Lomond, Calif. 95005
831-336-8891 Fax [phone]
http://www.dyneng.com
[email protected]
Est. 1988
User Manual
PCI3IP-Minimap
PCI 3 Slot IP Compatible Carrier
2KB Address Space
Manual Revision A
Corresponding Hardware: Revision 3
Corresponding Firmware Revision A
10-1999-0403

Page 2 Electronics Design • Manufacturing Services
PCI3IPmm
PCI based IP Compatible Carrier
Dynamic Engineering
435 Park Drive
Ben Lomond, CA 95005
831-336-8891
831-336-3840 FAX
This document contains information of
proprietary interest to Dynamic Engineering. It
has been supplied in confidence and the
recipient, by accepting this material, agrees
t
hat the subject matter will not be copied or
reproduced, in whole or in part, nor its
contents revealed in any manner or to any
person except to meet the purpose for which
it was delivered.
Dynamic Engineering has made every effort to
ensure that this manual is accurate and
complete. Still, the company reserves the
right to make improvements or changes in the
product described in this document at any
t
ime and without notice. Furthermore,
Dynamic Engineering assumes no liability
arising out of the application or use of the
device described herein.
The electronic equipment described herein
generates, uses, and can radiate radio
frequency energy. Operation of this equipment
in a residential area is likely to cause radio
interference, in which case the user, at his
own expense, will be required to take
whatever measures may be required to
correct the interference.
Dynamic Engineering’s products are not
authorized for use as critical components in
life support devices or systems without the
express written approval of the president of
Dynamic Engineering.
Connection of incompatible hardware is likely
t
o cause serious damage.
©1999,2000,2002 by Dynamic Engineering.
Other trademarks and registered trademarks are owned by their
respective manufactures.
Manual Revision A. Revised May 20, 2002

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Table of Contents
PRODUCT DESCRIPTION 5
THEORY OF OPERATION 7
ADDRESS MAP 9
PROGRAMMING 10
Register Definitions 11
pci3ip_intreg0 11
pci3ip_intreg1 13
pci3ip_intreg2 14
APPLICATIONS GUIDE 15
Interfacing 15
Construction and Reliability 15
Thermal Considerations 17
WARRANTY AND REPAIR 17
Service Policy 18
Out of Warranty Repairs 18
or Service Contact: 18
SPECIFICATIONS 19
ORDER INFORMATION 20

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List of Figures
FIGURE 1 P I3IPMM ADDRESS MAP 9
FIGURE 2 P I3IPMM ONTROL PORT 11
FIGURE 3 P I3IPMM INTERRUPT STATUS PORT 13
FIGURE 4 P I3IPMM USER SWIT H PORT 14
FIGURE 5 P I3IPMM ONNE TOR REFEREN E 21

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Product Description
PCI3IPmm is part of the IP Compatible family of modular I/O components.
The PCI3IPmm provides three IndustryPack Compatible sites in one PCI
slot.
ID, IO, INT, and MEM access types are supported for read and write
cycles. All four spaces are limited to 128 bytes to provide a minimum
address space for systems with limited memory.
The PCI bus is 32 bits wide and most industry packs are 16 bit devices.
Byte, word, and long word accesses are supported. Bytes can be to any
address. Word accesses need to be word aligned. Long word accesses
need to be long word aligned. Each of the access types has a one-to-one
correspondence to the hardware. There are no "extra" accesses with the
PCI3IPmm design.
A long word access will automatically be converted into two back-to-back IP
accesses with the address incrementing between cycles unless the
increment disable function is selected (see control register description). For
a read, one 32-bit data will be returned. For example a long word read to
the ID space would yield 0xff50ff49 for many boards as the "0" location has
$49 and the next address has $50. The long word mode happens
automatically when all 4 of the byte lane enables are detected asserted.
The overall throughput is greatly enhanced with this mode of operation.
The PCI3IPmm has a watchdog timer function, which completes the IP
access if the IP does not respond within 7.6 us. The watchdog timer has a
status bit and an optional interrupt output.
Each slot is programmable for 8 or 32 MHz. operation. The control
register has separate bits for slot A, B, C and state-machine. The state
machine speed defines the speed between cycles.
The PCI3IPmm supports interrupts from each slot with separate mask bits.
Two interrupts from each of the three slots. In addition, an interrupt force
bit is supplied to aid in software development. The masked interrupts are
tied together and connected to INTA on the PCI bus.
The PCI3IPmm has LED's for power and user functions. The three voltages
from slot A are connected to three LED's. An additional 6 LED's are
supplied which are controlled via the control register for user-defined
purposes.

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An 8 bit "dip switch" is provided on the PCI3IPmm. The switch configuration
is readable via a register. The switch is for user-defined purposes. We
envision the switch being used for software configuration control or test
purposes.
The reset switch provided can be used to reset the IP devices without
affecting the PCI bus. Power-on, PCI reset, and the control register reset
bit also cause the IP Reset to be activated. The reset is controlled to be
synchronous to the 8 MHz clock. Alternatively, in development, the IP-
Debug-Bus card also has a reset switch, which allows for individual slot
resets.
The IO are brought to 50 pin headers.
The PCI3IPmm conforms to the VITA standard for IndustryPack Carriers.
This guarantees compatibility with multiple IndustryPack compatible
modules.
If your project can benefit from a "non-standard" implementation, or
features that we have not thought of, or implemented yet please let us
know. For example, if your project will use IP's that can operate at 33 MHz
instead of 32, then we could synchronize the IP and PCI clocks and save
several synchronization steps.

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Theory of Operation
The PCI3IPmm is used to act as a bridge from PCI to IP bus specifications.
The PCI bus will be the master in most cases with the IP boards being
accessed for read or write cycles. The PCI accesses are handled at the
lowest level by the PCI core.
The PCI bus provides multiplexed address and data plus control lines. The
data is separated from the address and the control lines decoded to
provide the inputs to the IP Interface state machines. The address is tested
to determine which slot the access belongs to and which type of access.
The IP strobes are generated. When acknowledge is detected to be
asserted the cycle is terminated back to the host. The PCI bus will see a
retry mode while the access is taking place and "disconnect with data"
when the cycle is completed.
Feature List Current
• 3 IP compatible slots
• 8 or 32 MHz operation in each slot independently
• byte, word, long word access
• Incrementing or static access to each IP slot from long word access
• Bus error abort response
• 1:1 50 pin headers with .012" traces between IO and header
• IP Reset Switch
• 8 position "DIP Switch"
• 6 User LED's
• 3 Power LED's
• Fused Filtered Power with resettable fuses in each slot.
• Continued development with a "PROM" program
We plan to add several drivers for various products including the
PCI3IPmm to our product line. If you develop a driver for one of our
products and are willing to allow others to use it we will add it to the web
site as a free of charge download and, if desired, give credit to the author.
As Dynamic Engineering adds features to the hardware we will update the
PCI3IPmm page on the Dynamic Engineering website. If you want some of
the new features, and have already purchased hardware, we will support
you with a PROM update. We will ship a new PROM with the updated
program to you for shipping plus $25 for the first PROM and $15 per
device after that when ordered at the same time. If you are interested
please send a PO with shipping instructions, the serial numbers of the
boards to upgrade and the programming charge.

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The basic PCI identifying information will not change with the updates. The
revision field will allow configuration control. Current revision is 0x01.
Firmware Revision Table
A Initial Release

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Address Map
Function Offset description
// PCI relative addresses //
#define pci3ip_intreg_0 0x00000000 base cntl reg
#define pci3ip_intreg_1 0x00000004 interrupt request read back
#define pci3ip_intreg_2 0x00000008 read back of switch
// control register internal to Xilinx part. clock selection, interrupt
enable and set, IPACK size //
#define pci3ip_ida_st 0x00000200 start address slot A ID space
#define pci3ip_ioa_st 0x00000280 start address slot A IO space
#define pci3ip_inta_st 0x00000300 start address slot A INT space
#define pci3ip_mema_st 0x00000380 start address slot A MEM space
#define pci3ip_mema_en 0x000003ff end address slot A MEM space
#define pci3ip_idb_st 0x00000400 start address slot B ID space
#define pci3ip_iob_st 0x00000480 start address slot B IO space
#define pci3ip_intb_st 0x00000500 start address slot B INT space
#define pci3ip_memb_st 0x00000580 start address slot B MEM space
#define pci3ip_memb_en 0x000005ff end address slot B MEM space
#define pci3ip_idc_st 0x00000600 start address slot C ID space
#define pci3ip_ioc_st 0x00000680 start address slot C IO space
#define pci3ip_intc_st 0x00000700 start address slot C INT space
#define pci3ip_memc_st 0x00000780 start address slot C MEM space
#define pci3ip_memc_en 0x000007ff end address slot C MEM space
FIGURE 1 P I3IPMM ADDRESS MAP
The address map provided is for the local decoding performed within
PCI3IPmm. The addresses are all offsets from a base address. The host
that the PCI3IPmm is installed into provides the base address and interrupt
level.
The host system will search the PCI bus to find the assets installed during
power-on initialization. The VendorId = 0x10EE and the CardId = 0x000E for
the PCI3IPmm. Interrupts are requested by the configuration space.
PCIView and other third party utilities can be useful to see how your system
is configured.
The VendorId and CardId parameters need to be set in the registry [NT].
The interrupt level expected and style is also set in the registry. Dynamic
Engineering recommends WinRT to provide the low level hardware interface
for Windows based systems.

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Si
Once the initialization process has occurred and the system has assigned
an address range to the PCI3IPmm card, the software will need to
determine what the address space is. We refer to this address as base0
in our software.
The next step is to initialize the PCI3IPmm. The main control register is
written to for clock selection, and interrupt mask. The default of no
interrupts enabled and 8 MHz operation will be valid in many cases.
Programming
The following is the initialization sequence that we use for our test software
in an NT environment. We use a program called WinRT to do the low level
accesses to the hardware. We use MS Visual C++ in conjunction with
WinRT to write our test software. Please feel free to copy the following set-
up code or to consider purchasing our engineering kit, which comes with
our test suite.
#include "G_ALL.h"
unsigned long int base0, address, data, iWinRTlength;
unsigned long int data_in, data_s, data_out, errorCode, error;
unsigned long int reg, reg_copy, result, i, j;
long int pci3ip_init() {
HANDLE hWinRT = WinRTOpenDevice(0, FALSE);
WINRT_CONFIGURATION configBuf;
DWORD iWinRTlength;
if (WinRTGetConfiguration(hWinRT, &configBuf, &iWinRTlength) != 0)
{
base0 = configBuf.memMin;
Your Software Goes Here accesses are relative to base0
WinRTCloseDevice(hWinRT);
return(0);
}
else
printf("Error: %d\n", GetLastError());
WinRTCloseDevice(hWinRT);
return(1);
}