Epson RA8804 CE Instructions for use

ETM60E-02
Preliminary
Application Manual
Real Time Clock Module
RA8804 CE

NOTICE
This material is subject to change without notice.
Any part of this material may not be reproduced or duplicated in any form or any means without the
written permission of Seiko Epson.
The information about applied circuitry, software, usage, etc. written in this material is intended for
reference only. Seiko Epson does not assume any liability for the occurrence of infringing on any
patent or copyright of a third party. This material does not authorize the licensing for any patent or
intellectual copyrights.
When exporting the products or technology described in this material, you should comply with the
applicable export control laws and regulations and follow the procedures required by such laws and
regulations.
You are requested not to use the products (and any technical information furnished, if any) for the
development and/or manufacture of weapon of mass destruction or for other military purposes. You
are also requested that you would not make the products available to any third party who may use the
products for such prohibited purposes.
These products are intended for general use in electronic equipment. When using them in specific
applications that require extremely high reliability, such as the applications stated below, you must
obtain permission from Seiko Epson in advance.
/ Space equipment (artificial satellites, rockets, etc.) / Transportation vehicles and related
(automobiles, aircraft, trains, vessels, etc.) / Medical instruments to sustain life /
Submarine transmitters / Power stations and related / Fire work equipment and security
equipment / traffic control equipment / and others requiring equivalent reliability.
All brands or product names mentioned herein are trademarks and/or registered trademarks of their
respective.

ETM60E Revision History
Rev No.
Date
Page
Description
ETM60E-01
30.Apr.2018
Release
ETM60E-02
27.Jun.2018
14
40
5) RESET bit
it explained detailed function of RESET.
8.15. Figure of 32 kHz-TCXO was updated.
SCL and SDA connects to GND.

RA8804 CE
ETM60E-02
Table of Contents
1. Overview...................................................................................................................................................... 1
2. Block Diagram............................................................................................................................................. 1
3. Terminal description.................................................................................................................................... 2
3.1. Terminal connections.................................................................................................................................................2
3.2. Pin Functions.............................................................................................................................................................2
4. Absolute Maximum Ratings ........................................................................................................................ 3
5. Recommended Operating Conditions......................................................................................................... 3
6. Frequency Characteristics .......................................................................................................................... 3
7. Electrical Characteristics............................................................................................................................. 4
7.1. DC Characteristics.....................................................................................................................................................4
7.2. AC characteristics......................................................................................................................................................5
8. Use Methods............................................................................................................................................... 6
8.1. Description of Registers.............................................................................................................................................6
8.1.1. Write/Read and Bank Select..........................................................................................................................6
8.1.2. Register table (Basic time and calendar register)...........................................................................................6
8.1.3. Register table (Time stamp, EVIN, SOUT, Timer)..........................................................................................7
8.1.4. Quick Reference ............................................................................................................................................7
8.2. Details of Registers....................................................................................................................................................8
8.2.1. Clock counter (SEC - HOUR).........................................................................................................................8
8.2.3. Alarm registers.............................................................................................................................................10
8.2.4. Fixed-cycle timer control registers................................................................................................................10
8.2.5. Extension register ........................................................................................................................................10
8.2.6. Flag register.................................................................................................................................................11
8.2.7. Control register.............................................................................................................................................13
8.3. Fixed-cycle Timer Interrupt Function .......................................................................................................................15
8.3.1. Diagram of fixed-cycle timer interrupt function.............................................................................................15
8.3.2. Related registers for function of fixed-cycle timer interruption......................................................................16
8.3.3. Timer register...............................................................................................................................................16
8.3.4. Fixed-cycle timer interrupt interval (example)...............................................................................................18
8.3.5. Fixed-cycle timer start timing........................................................................................................................18
8.4. EVIN Interrupt and Time stamp Function.................................................................................................................19
8.4.1. Diagram of EVIN interrupt function...............................................................................................................19
8.4.2. Operation example of Time-Stamp function.................................................................................................20
8.4.3. Related registers for EVIN Interrupt and Time stamp Function....................................................................20
8.5. SOUT Interrupt Function..........................................................................................................................................23
8.5.1. Operation example of SOUT function. .........................................................................................................23
8.5.2. Related registers for SOUT interrupt functions.............................................................................................24
8.6. Time Update Interrupt Function...............................................................................................................................25
8.6.1. Time update interrupt function diagram........................................................................................................25
8.6.2. Related registers for time update interrupt functions....................................................................................26
8.7. Alarm Interrupt Function..........................................................................................................................................27
8.7.1. Diagram of alarm interrupt function..............................................................................................................27
8.7.2. Related registers for Alarm interrupt function...............................................................................................28
8.7.3. Examples of alarm settings..........................................................................................................................29
8.8. About the interrupt function for operation /INT = “L”interrupt output.......................................................................30
8.9. Temperature compensation function. ......................................................................................................................30
8.9.1. Temperature compensation function............................................................................................................30
8.9.2. Related registers for temperature compensation function............................................................................30
8.10. Reading/Writing Data via the I2C Bus Interface.....................................................................................................31
8.10.1. Overview of I2C-BUS.................................................................................................................................31
8.10.2. System configuration..................................................................................................................................31
8.10.3. Starting and stopping I2C bus communications..........................................................................................32
8.10.4. Data transfers and acknowledge responses during I2C-BUS communications..........................................33
8.10.5. Slave address ............................................................................................................................................33
8.10.6. I2C bus protocol..........................................................................................................................................34
8.11. Backup and Recovery............................................................................................................................................35
8.12. About access at the time of backup return and Initial power supply ......................................................................36
8.13. Flow chart..............................................................................................................................................................37
8.14. Connection with Typical Microcontroller ................................................................................................................40
8.15. When used as a clock source (32 kHz-TCXO) ......................................................................................................40
9. External Dimensions/Marking Layout...................................................................................................... 41
9.1. RX8804CE..............................................................................................................................................................41
9.1.1. External dimensions.....................................................................................................................................41
9.1.2. Marking layout..............................................................................................................................................41
10. Application notes..................................................................................................................................... 42

RA8804 CE
Page - 1 ETM60E-02
I2C-Bus Interface Real-time Clock Module
RA8804 CE
Features built-in 32.768 kHz DTCXO.
Supports I2C-Bus's high speed mode (Up to 400 kHz)
Time -Stamp function with EVIN-Pin trigger.
Outputs to SOUT-Pin of each of detection Flag or others.
Alarm interrupt function for day, date, hour, and minute settings
Fixed-cycle timer interrupt function
244.14 µs to 32 years
Time update interrupt function
(Seconds, minutes)
Temperature compensated 32.768 kHz output with OE function
(FOE and FOUT pins)
Auto correction of leap years
(from 2000 to 2099)
Wide interface voltage range: 1.6 V to 5.5 V
Wide time-keeping voltage range:1.5 V to 5.5 V
Low current consumption: 0.35 µA / 3.0 V (Typ.)
AEC-Q100 compliant for automotive applications
1. Overview
This module is an I2C bus interface-compliant real-time clock which includes a 32.768 kHz DTCXO.
In addition to providing a calendar (year, month, date, day, hour, minute, second) function and a clock counter
function, this module provides an abundance of other functions including an alarm function, fixed-cycle timer
function, time update interrupt function, 32.768 kHz output function, Time-stamp function with EVIN-pin trigger,
and. Programmable output function to SOUT-pin of detection Flag or others.
The devices in this module are fabricated via a C-MOS process for low current consumption, which enables
long-term battery back-up.
2. Block Diagram
INTERRUPTS
CONTROLLER
ALARM REGISTER
/ INT
BUS
INTERFACE
CIRCUIT
( 32.768 kHz )
CONTROL
REGISTER
DIVIDER
CLOCK
POWER
CONTROLLER
and
SDA
VDD
SCL
CALENDR
TIMER REGISTER
DTCXO
CONTROLLER
FOUT
FOUT
FOE
CONTROLLER
SOUT
SOUT
CONTROLLER
EVENT DETECTION
EVIN
CAPTURE
BUFFER
VDD
SYSTEM
CONTROLLER

RA8804 CE
Page - 2 ETM60E-02
3. Terminal description
3.1. Terminal connections
RA8804CE
1.
FOE
10.
/ INT
2.
VDD
9.
GND
3.
EVIN
8.
T2
4.
FOUT
7.
SDA
5.
SCL
6.
SOUT
3.2. Pin Functions
Signal
name
I/O
Function
SDA
I/O
This pin's signal is used for input and output of address, data, and ACK bits, synchronized
with the serial clock used for I2C communications.
Since the SDA pin is an N-ch open drain pin during output, be sure to connect a suitable
pull-up resistance relative to the signal line capacity.
SCL
Input
This is the serial clock input pin for I2C Bus communications.
FOUT
Output
This is the C-MOS output pin with output control provided via the FOE pin.
When FOE =”H”(high level), this pin outputs a 32.768 kHz signal. (depend on FSEL bit)
When output is stopped, the FOUT pin = Hi-Z (high impedance).
FOE
Input
This is an input pin used to control the output mode of the FOUT pin.
When this pin's level is high, the FOUT pin is in output mode. When it is low, output via the
FOUT pin is stopped.
/ INT
Output
This pin is used to output alarm signals, timer signals, time update signals, and other signals.
This pin is an open drain pin.
EVIN
Input
Trigger input terminal for time-stamps. Built in disconnectable Pull-up resistor.
SOUT
Output
SOUT is push-pull for the inside state output.
SOUT outputs state of a specified flag bit or selected logical 1 or 0.
VDD

This pin is connected to a positive power supply.
GND

This pin is connected to a ground.
T2

Use only for testing in the factory.
(Do not connect externally.)
Note: Be sure to connect a bypass capacitor rated at least 0.1 μF between VDD and GND.

RA8804 CE
Page - 3 ETM60E-02
4. Absolute Maximum Ratings
5. Recommended Operating Conditions
GND=0 V
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
Operating supply voltage
VACC
Between VDD and GND
1.6
3.0
5.5
V
Temp. compensation voltage
VTEM

1.5
3.0
5.5
V
Clock supply voltage
VCLK

1.5
3.0
5.5
V
Operating temperature
TOPR
No condensation
40
+25
+105
C
* To apply Min. value of VACC and VCLK, the VDD needs to be supplied with more than 1.5 V at least for the oscillation to stabilize
(oscillation start time tSTA).
* The Min. value of VCLK is the Min. voltage required to retain the time counting function; it is however necessary to maintain VTEM till the
oscillation of the oscillator has stabilized (oscillation start time tSTA).
* The temperature compensation stops working below Min. value of VTEM.
6. Frequency Characteristics
GND=0V
Item
Symbol
Condition
Rating
Unit
Frequency stability
f/f
XA
Ta = 0 to +50 C, VDD = 3.0 V
Ta = -40 to +85 C, VDD = 3.0 V
Ta = -85 to +105 C, VDD = 3.0 V
1.9*1
3.4*2
8.0*3
10-6
XB
Ta = 0 to +50 C, VDD = 3.0 V
Ta = -40 to +85 C, VDD = 3.0 V
Ta = -85 to +105 C, VDD = 3.0 V
3.8*4
5.0*5
8.0*3
Frequency/voltage
characteristics
f/V
Ta= +25 C, VDD=1.5 V to 5.5 V
1.0 Max.
10-6/V
FOUT duty cycle
Duty
50% VDD
+25 C, VDD=1.5 V to 5.5 V
50 10
%
Oscillation start time
tSTA
Ta = +25 C, VDD = 1.5 V 5.5 V
Ta = -40 to +85 C, VDD = 1.6 V to 5.5 V
1.0 Max.
3.0 Max.
s
Aging
fa
Ta = +25 C, VDD = 3.0 V, first year
3 Max.
10-6/year
Reflow
fref
260 C (Max.), 2 times
3*6 Max.
10-6
*1 5 sec error per a month.
*2 9 sec error per a month.
*3 21 sec error per a month.
*4 10 sec error per a month.
*5 13.2 sec error per a month.
*6 The result that it was measured at 25

C, 24 hours after processing of reflow soldering.
GND=0V
Item
Symbol
Condition
Rating
Unit
Supply voltage
VDD
Between VDD and GND
0.3 to +6.5
V
Input voltage (1)
VIN1
FOE, SCL, SDA, EVIN pins
ND0.3 to +6.5
V
Input voltage (2)
VIN2
EVIN pin
GND0.3 to VDD+0.3
V
Output voltage (1)
VOUT1
FOUT and SOUT pin
GND0.3 to VDD+0.3
V
Output voltage (2)
VOUT2
SDA and /INT pins
GND0.3 to +6.5
V
Storage temperature
TSTG
When stored separately,
without packaging
55 to +125
C

RA8804 CE
Page - 4 ETM60E-02
7. Electrical Characteristics
7.1. DC Characteristics
*Unless otherwise specified, GND=0V,VDD=1.5Vto5.5V,Ta=40Cto+105C
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
Average Current consumption(1)
IDD1
fSCL = 0 Hz. / INT = Hi-Z.
FOUT is stopped.
Temp compensation interval 2.0 s
VDD=5 V
0.40
1.6
µA
Average Current consumption(2)
IDD2
VDD=3 V
0.35
1.5
Average Current consumption(3)
IDD3
fSCL = 0 Hz. / INT = Hi-Z.
FOUT outputs 32 kHz. CL = 0 pF
Temp compensation interval 2.0 s
VDD=5 V
1.1
3.1
Average Current consumption(4)
IDD4
VDD=3 V
1.0
3.0
Average Current consumption(5)
IDD5
fSCL = 0 Hz. / INT = Hi-Z.
FOUT outputs 32 kHz. CL = 30 pF
Temp compensation interval 2.0 s
VDD=5 V
6.1
8.1
Average Current consumption(6)
IDD6
VDD=3 V
4.0
6.0
Average Current consumption(7)
IDD7
fSCL = 0 Hz. / INT = Hi-Z.
FOUT is stopped.
Temp compensation is stopped.
VDD=5 V
0.38
1.55
Average Current consumption(8)
IDD8
VDD=3 V
0.33
1.45
Peak Current consumption(1)
IDD9
fSCL = 0 Hz. / INT = VDD.
FOUT is stopped.
Temp compensation ON (peak)
VDD=5 V
55
100
Peak Current consumption (2)
IDD10
VDD=3 V
50
95
High-level input voltage
VIH1
SCL, SDA, FOE
0.8 VDD
5.5
V
VIH2
EVIN
0.8 VDD
VDD
Low-level input voltage
VIL
SCL, SDA, FOE, EVIN
GND 0.3
0.2 VDD
High-level output voltage
VOH1
FOUT, SOUT
VDD = 5 V, IOH = 1 mA
4.5
5.0
VOH2
VDD = 3 V, IOH = 1 mA
2.2
3.0
VOH3
VDD = 3 V, IOH = 100 µA
2.9
3.0
Low-level output voltage
VOL1
FOUT, SOUT
VDD = 5 V, IOL = 1 mA
GND
GND+0.5
VOL2
VDD = 3 V, IOL = 1 mA
GND
GND+0.8
VOL3
VDD = 3 V, IOL = 100 µA
GND
GND+0.1
VOL4
/ INT
VDD = 5 V, IOL = 1 mA
GND
GND+0.25
VOL5
VDD = 3 V, IOL = 1 mA
GND
GND+0.4
VOL6
SDA
VDD 2 V, IOL = 3 mA
GND
GND+0.4
Input leakage current
ILK
INPUT pins, VIN = VDD or GND
0.5
0.5
µA
Output leakage current
IOZ
Output pins, output voltage = VDD or GND
0.5
0.5
Pull-up Resistor
REVIN
EVIN
125
500
2000
kΩ
Detection voltage of VDET
VDET
VDD
1.41
1.45
1.49
V
Detection voltage of VLF
VLOW
VDD
0.9
1.0
1.2
Temperature compensation and consumption current
0.7 ms Temp compensation ON (peak)
IDD9,10
Temp Compensation interval (2.0 s)
IDD7,8
IDD1,2
Temp Compensation OFF
Average
The current consumption of RA8804 increases at a timing of a temperature compensation.
As for this peak current consumption, it occurs in about 0.7ms.
IDD1, IDD2 is the average current consumption at temperature compensation in 2 seconds cycle.

RA8804 CE
Page - 5 ETM60E-02
7.2. AC characteristics
* Unless otherwise specified, GND=0V,VDD=1.6Vto5.5V,Ta=40Cto+105C
Item
Symbol
Condition
SCL = 100 kHz
(Standard-Mode
SCL = 400 kHz
(Fast-Mode)
Unit
Min.
Max.
Min.
Max.
SCL clock frequency
fSCL


100

400
kHz
Start condition setup time
tSU;STA

4.7

0.6

µs
Start condition hold time
tHD;STA

4.0

0.6

µs
Data setup time
tSU;DAT

250

100

ns
Data hold time
tHD;DAT

0

0

ns
Stop condition setup time
tSU;STO

4.0

0.6

µs
Bus idle time between
start condition and stop condition
tBUF

4.7

1.3

µs
Time when SCL = ”L”
tLOW

4.7

1.3

µs
Time when SCL = “H”
tHIGH

4.0

0.6

µs
Rise time for SCL and SDA
tr


1.0

0.3
µs
Fall time for SCL and SDA
tf


0.3

0.3
µs
Allowable spike time on bus
tSP


50

50
ns
Timing chart
tHD ; DAT
tSU ; DAT
tHD ; STA
tLOW
tHIGH
1 / fSCL
tr
tf
tSU ; STA
SDA
SCL
START
CONDITION
(S)
BIT 7
MSB
(A7)
BIT 6
(A6)
ACK
(A)
Protocol
tBUF
tSU ; STO
STOP
CONDITION
(P)
START
CONDITION
(S)
(P)
(A)
tHD ; STA
tSU ; STA
(S)
BIT 0
LSB
(R/W)
(S)
tSP
Note:
1. As for the communication of I2C, completion of less than 1 second is recommended. If such
communication requires 1 second (Max.) or longer, the I2C bus interface is reset by the internal bus
timeout function. When bus-time-out occur, SDA turns to Hi-Z input mode.
2. But readout data of a clock is stable anytime, and there isn’t contradiction. And it does not occur
that data of a clock delay even if access time is prolonged.
Reference characteristic data (Typical) I2C-bus active current

RA8804 CE
Page - 6 ETM60E-02
8. Use Methods
8.1. Description of Registers
8.1.1. Write/Read and Bank Select
Address 00h to 0Fh: Basic time and calendar register. It compatible with RX-8803 and RX/RA8900
Address 10h to 1Fh: Extension register
Access to more than address 20h is possible, but there is some control register for quality inspection. When more than
Address auto increment is looping in lower 4 bits address.
Upper 4bits address are fixed. (00, ..., 0E, 0F, 00, 01) (10, ..., 1E, 1F, 10, 11)
Basic register
Time stamp register
Access is prohibited
Address (8bit)
0Fh from 00h
1Fh from 10h
FFh from 20h
8.1.2. Register table (Basic time and calendar register)
Address
Function
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Init
Write
00
SEC

40
20
10
8
4
2
1

01
MIN

40
20
10
8
4
2
1

02
HOUR


20
10
8
4
2
1

03
WEEK

6
5
4
3
2
1
0

04
DAY


20
10
8
4
2
1

05
MONTH



10
8
4
2
1

06
YEAR
80
40
20
10
8
4
2
1

07
RAM









08
MIN Alarm
AE
40
20
10
8
4
2
1

09
HOUR Alarm
AE

20
10
8
4
2
1

0A
WEEK Alarm
AE
6
5
4
3
2
1
0

DAY Alarm

20
10
8
4
2
1
0B
Timer Counter 0
128
64
32
16
8
4
2
1

0C
Timer Counter 1
32768
16384
8132
4096
2048
1024
512
256

0D
Extension Register
TEST
WADA
USEL
TE
FSEL1
FSEL0
TSEL1
TSEL0
[0:2]

0E
Flag Register


UF
TF
AF

VLF
VDET
[0:0]
Clear
only
0F
Control Register
CSEL1
CSEL0
UIE
TIE
AIE


RESET
[4:0]

Writing is avoid. Read value is 0, always. It can read and write. is available. avoid.
“Init”shows value of after power-on Reset. Unit is Hex.
Note
After the initial power-up (from 0V) or in case the VLF bit returns “1”, make sure to initialize all registers, before
using the RTC.
Be sure to avoid entering incorrect date and time data, as clock operations are not guaranteed when the data or
time data is incorrect.
-
During the initial power-up,the following are the default settings for the register values
Initial value_0: TSVLF, TSVDET,TEST, WADA, USEL, TE, FSEL1, FSEL0, TSEL0, UF, TF, AF, CSEL1, UIE, TIE,
AIE, RESET, ECP, EHL, EPU, RCE, EIE, ET1, ET0, EF, EVMON, SOE0 ~ SOE7, DCE, DC, SRV,
FS0～FS2, TRES, TSTP, All bits of address 1Ch, 1Dh, 1Eh, and 1Fh.
Initial value_1: TSEL1, VLF,VDET,CSEL0
At this point, all other register values are undefined, so be sure to perform a reset before using the module.
-
Only a 0 can be written to the UF, TF, AF, VLF, VDET and EF bit.
The EVMON bit is read only bit.
-
Any bit marked with “”should be used with a value of “0”after initialization.
-
Any bit marked with “”is a RAM bit that can be used to read or write any data.
-
The TEST bit is used by the manufacturer for testing. Be sure to set “0”for this bit when writing.
-
If an alarm function is not used, registers 08h-0Ah can be used as RAM. (AIE : “0”)
-
Reading register value of address 0Bh-0Ch and 1Fh is pre-set data.
If a timer function is not used, register of 0Bh-0Ch and 1Fh can be used as RAM. (TE,TIE : “0”)

RA8804 CE
Page - 7 ETM60E-02
8.1.3. Register table (Time stamp, EVIN, SOUT, Timer)
Address
Function
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Init
Write
10
Time stamp Seconds

40
20
10
8
4
2
1
[0:0]

11
Time stamp Minutes

40
20
10
8
4
2
1
[0:0]

12
Time stamp Hours


20
10
8
4
2
1
[0:0]

13
Time stamp Weekday

6
5
4
3
2
1
0
[0:0]

14
Time stamp Days


20
10
8
4
2
1
[0:0]

15
Time stamp Months
TSVLF
TSVD
ET

10
8
4
2
1
[0:0]

16
Time stamp Years
80
40
20
10
8
4
2
1
[0:0]

17
EVIN Control
ECP
EHL
EPU
RCE
EIE

ET1
ET0
[0:0]

18
EVIN Monitor
EF



EVMON



[0:0]

19
SOUT Control 1
SOE7
SOE6
SOE5
SOE4
SOE3
SOE2
SOE1
SOE0
[0:0]

1A
SOUT Control 2
DCE
DC


SRV
FS2
FS1
FS0
[0:0]

1B
Timer Control
TSTP
TRES






[0:0]

1C
Monitor of Timer0
128
64
32
16
8
4
2
1
[0:0]

1D
Monitor of Timer1
32768
16384
8192
4096
2048
1024
512
256
[0:0]

1E
Monitor of Timer2
8388608
4194304
2097152
1048576
524288
262144
131072
65536
[0:0]

1F
Timer Counter 2
8388608
4194304
2097152
1048576
524288
262144
131072
65536
[0:0]

Writing is avoid. Read value is 0, always. It can read and write. is available. avoid.
“Init”shows value of after power-on Reset. Unit is Hex.
8.1.4. Quick Reference
Update interrupt timing
Default
USEL = 0
Once per seconds

USEL = 1
Once per minutes
Output Frequency selection
FSEL1, FSEL0 = 00
32.768 kHz

FSEL1, FSEL0 = 01
1024 Hz
FSEL1, FSEL0 = 10
1 Hz
FSEL1, FSEL0 = 11
32.768 kHz
Timer source clock selection
TSEL1, TSEL0 = 00
4096 Hz
TSEL1, TSEL0 = 01
64 Hz
TSEL1, TSEL0 = 10
Every seconds update

TSEL1, TSEL0 = 11
Every minutes update
Temperature compensation selection
CSEL1, CSEL0 = 00
0.5 sec
CSEL1, CSEL0 = 01
2.0 sec

CSEL1, CSEL0 = 10
10 sec
CSEL1, CSEL0 = 11
30 sec

RA8804 CE
Page - 8 ETM60E-02
8.2. Details of Registers
8.2.1. Clock counter (SEC - HOUR)
Address
Function
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
00
SEC

40
20
10
8
4
2
1
01
MIN

40
20
10
8
4
2
1
02
HOUR


20
10
8
4
2
1
“o”indicates write-protected bits. A zero is always read from these bits.
The clock counter counts seconds, minutes, and hours.
The data format is BCD format. For example, when the “seconds”register value is “0101 1001”it indicates
59 seconds.
Note with caution that writing non-existent time data may interfere with normal operation of the clock
counter.
1) Second counter
Address
Function
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
00
SEC

40
20
10
8
4
2
1
This second counter counts from “00”to “01”, “02”, and up to 59 seconds, after which it starts again from
00 seconds.
When written data to a second register, less than a Second counter (512 Hz from 2 Hz) is cleared to zero.
When more highly precise time synchronization is needed, RESET bit is most suitable. When 60
seconds were written to a second register, it returns to 00 second in next update. This special update is
the same as plus-adjustment of leap second. This behavior is useful in the adjustments of Leap
seconds.
2) Minute counter
Address
Function
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
01
MIN

40
20
10
8
4
2
1
This minute counter counts from “00”to “01”, “02”, and up to 59 minutes, after which it starts again from 00
minutes.
3) Hour counter
Address
Function
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
02
HOUR


20
10
8
4
2
1
This hour counter counts from “00”hours to “01”, “02””o indicates write-protected bits. A zero is always
read from these bits.

RA8804 CE
Page - 9 ETM60E-02
8.2.2. Calendar counter (WEEK - YEAR)
Address
Function
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
03
WEEK

6
5
4
3
2
1
0
“o”indicates write-protected bits. A zero is always read from these bits.
1) Day of the WEEK counter
The day (of the week) is indicated by 7 bits, bit 0 to bit 6.
The day data values are counted as follows: Day 01hDay 02hDay 04hDay 08hDay
10hDay 20hDay 40hDay 01hDay 02h, etc.
The correspondence between days and count values is shown below.
WEEK
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Day
Data [h]
Write/Read
0
0
0
0
0
0
0
1
Sunday
01 h
0
0
0
0
0
0
1
0
Monday
02 h
0
0
0
0
0
1
0
0
Tuesday
04 h
0
0
0
0
1
0
0
0
Wednesday
08 h
0
0
0
1
0
0
0
0
Thursday
10 h
0
0
1
0
0
0
0
0
Friday
20 h
0
1
0
0
0
0
0
0
Saturday
40 h
Write prohibit
Do not set “1”to more than one day at the same time.
Also, note with caution that any setting other than the
seven shown above should not be made as it may
interfere with normal operation.


Address
Function
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
04
DAY


20
10
8
4
2
1
05
MONTH



10
8
4
2
1
06
YEAR
80
40
20
10
8
4
2
1
“o”indicates write-protected bits. A zero is always read from these bits.
The auto calendar function updates all dates, months, and years from January 1, 00 to December 31, 99.
The data format is BCD format. For example, a date register value of “0011 0001”indicates the 31st.
Note with caution that writing non-existent date data may interfere with normal operation of the calendar
counter.
2) Date counter
Address
Function
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
04
DAY


20
10
8
4
2
1
The updating of dates by the date counter varies according to the month setting.
A leap year is set whenever the year value is a multiple of four (such as 04, 08, 12, 88, 92, or 96). In
February of a leap year, the counter counts dates from “01”, “02”, “0”3, to “28”, “29”, “01”, etc.
DAY
Month
Date update pattern
Write/Read
1, 3, 5, 7, 8, 10, or 12
01, 02, 03 30, 31, 01 
4, 6, 9, or 11
01, 02, 03 30, 01, 02 
February in normal year
01, 02, 03 28, 01, 02 
February in leap year
01, 02, 03 28, 29, 01 
3) Month counter
Address
Function
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
05
MONTH



10
8
4
2
1
The month counter counts from 01 (January), 02 (February), and up to 12 (December), then starts again
at 01 (January).
4) Year counter
Address
Function
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
06
YEAR
Y80
Y40
Y20
Y10
Y8
Y4
Y2
Y1
The year counter counts from 00, 01, 02 and up to 99, then starts again at 00.
Any year that is a multiple of four (04, 08, 12, 88, 92, 96, etc.) is handled as a leap year.

RA8804 CE
Page - 10 ETM60E-02
8.2.3. Alarm registers
Address
Function
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
08
MIN Alarm
AE
40
20
10
8
4
2
1
09
HOUR Alarm
AE

20
10
8
4
2
1
0A
WEEK Alarm
AE
6
5
4
3
2
1
0
DAY Alarm

20
10
8
4
2
1
The alarm interrupt function is used, along with the AEI, AF, and WADA bits, to set alarms for specified
date, day, hour, and minute values.
When the settings in the above alarm registers and the WADA bit match the current time, the /INT pin
goes to low level and “1”is set to the AF bit to report that an alarm interrupt event has occurred.
8.2.4. Fixed-cycle timer control registers
Address
Function
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0B
Timer Counter 0
128
64
32
16
8
4
2
1
0C
Timer Counter 1
32768
16384
8192
4096
2048
1024
512
256
1B
Setup of Timer
TSTP
TRES






1C
Current value of Timer 0
128
64
32
16
8
4
2
1
1D
Current value of Timer 1
32768
16384
8192
4096
2048
1024
512
256
1E
Current value of Timer 2
8388608
4194304
2097152
1048576
524288
262144
131072
65536
1F
Timer Counter 2
8388608
4194304
2097152
1048576
524288
262144
131072
65536
These registers are used to set the preset countdown value for the fixed-cycle timer interrupt function.
The TE, TF, TIE, and TSEL0/1 bits are also used to set the fixed-cycle timer interrupt function.
When the value in the above fixed-cycle timer control register just changes from 01h to 00h, the /INT pin
goes to low level and “1”is set to the TF bit to report that a fixed-cycle timer interrupt event has occurred.
8.2.5. Extension register
Address
Function
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0D
Extension Register
TEST
WADA
USEL
TE
FSEL1
FSEL0
TSEL1
TSEL0
(Default)
(0)
(0)
(0)
(0)
(0)
(0)
(1)
(0)
The default value is loaded after powering up from 0 V, automatically.
TEST must be always cleared by a zero.
This register is used to specify the target for the alarm function or time update interrupt function and to
select or set operations such as fixed-cycle timer operations.
1) TEST bit
This is the manufacturer's test bit. Its value should always be “0”.
Be careful to avoid writing a “1”to this bit when writing to other bits.
TEST
Data
Description
Write/Read
0
Normal operation mode Default
1
Setting prohibited (manufacturer's test bit)
2) WADA (Week Alarm/Day Alarm) bit
This bit is used to specify either WEEK or DAY as the target of the alarm interrupt function.
Writing a “1”to this bit specifies a DAY alarm, meaning the alarm interrupt is initiated independent of the actual
day when the set time is reached.
Writing a “0”to this bit specifies a WEEK alarm, so an alarm interrupt is only generated when the set time is
reached on a dedicated day of a week.

RA8804 CE
Page - 11 ETM60E-02
3) USEL (Update Interrupt Select) bit
This bit is used to define if the RTC should output a “second update”or “minute update”interrupt, allowing to
synchronize external clocks with the time registers of the RTC.
USEL
Data
update interrupts
Auto reset time
tRTN
Write/Read
0
second update Default
500 ms
1
minute update
Min. 7.813 ms
4) TE (Timer Enable) bit
This bit controls the start/stop setting for the fixed-cycle timer interrupt function.
Writing a “1”to this bit specifies starting of the fixed-cycle timer interrupt function (a countdown starts from a preset
value).
Writing a “0”to this bit specifies stopping of the fixed-cycle timer interrupt function.
5) FSEL0, 1 (FOUT frequency Select 0, 1) bits
The combination of these two bits is used to set the FOUT frequency.
Note: All frequencies are temperature compensated!
FSEL0,1
FSEL1
(bit 3)
FSEL0
(bit 2)
FOUT frequency
Write/Read
0
0
32768HzOutput Default
0
1
1024HzOutput
1
0
1HzOutput
1
1
32768HzOutput
6) TSEL0, 1 (Timer Select 0, 1) bits
The combination of these two bits is used to set the countdown period (source clock) for the fixed-cycle timer
interrupt function (four settings can be made).
TSEL0,1
TSEL1
(bit 1)
TSEL0
(bit 0)
Source clock
Write/Read
0
0
4096 Hz
/ Once per 244.14 s
0
1
64 Hz
/ Once per 15.625 ms
1
0
“Second update”/ Once per second
1
1
“Minute update”/ Once per minute
8.2.6. Flag register
Address
Function
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0E
Flag register


UF
TF
AF

VLF
VDET
(Default)
(0)
(0)
(0)
(0)
(0)
(0)
(1)
(1)
1. The default value is the value that is read (or is set internally) after powering up from 0 V.
2. “o”indicates write-protected bits. A zero is always read from these bits.
This register is used to detect the occurrence of various interrupt events and low voltage which might
compromise the reliability of provided time and data.
1) UF (Update Flag) bit
If set to “0”beforehand, this flag bit's value changes from “0”to “1”when a time update interrupt event has
occurred. Once this flag bit's value is “1”, its value is retained until a “0”is written to it.
For details, see 8.4. Time Update Interrupt Function.
2) TF (Timer Flag) bit
If set to “0”beforehand, this flag bit's value changes from “0”to “1”when a fixed-cycle timer interrupt event has
occurred. Once this flag bit's value is “1”, its value is retained until a “0”is written to it.
For details, see 8.3. Fixed-cycle Timer Interrupt Function.
3) AF (Alarm Flag) bit
If set to “0”beforehand, this flag bit's value changes from “0”to “1”when an alarm interrupt event has occurred.
Once this flag bit's value is “1”, its value is retained until a “0”is written to it.
For details, see “8.5. Alarm Interrupt Function”.

RA8804 CE
Page - 12 ETM60E-02
4) VLF (Voltage Low Flag) bit
This flag bit indicates the retained status of clock operations or internal data. Its value change from “0”to “1”
indicates a possible data loss or time data error due to a supply voltage drop. Once this flag bit's value is “1”, its
value is retained until a “0”is written to it.
After powering up from 0 V, make sure to set this bit's value to “1”. Please confirm table in 8.11. Backup and
Recovery.
VLF
Data
Description
Write
0
The VLF bit is cleared to zero to prepare for the next status detection.
1
Invalid (writing a 1 will be ignored)!
Read
0
No supply voltage drops occurred.
1
Low voltage has been detected, so data loss might have occurred and time
information might be compromised.
All registers must be initialized.
(This setting is retained until a “” is written to this bit.)
5) VDET (Voltage Detection Flag) bit
This flag bit indicates the status of temperature compensation. Its value changes from “0”to “1”when the
temperature compensation function has stopped operation due to a supply voltage drop. Once this flag bit's value
is 1, its value is retained until a 0 is written to it.
After powering up from 0 V, make sure to set this bit's value to “1”. Please confirm table in 8.11. Backup and
Recovery.
VDET
Data
Description
Write
0
The VDET bit is cleared to zero to prepare for the next low voltage detection.
1
Invalid (writing a 1 will be ignored)!
Read
0
Temperature compensation is normal.
1
Temperature compensation has been stopped.

RA8804 CE
Page - 13 ETM60E-02
8.2.7. Control register
Address
Function
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0F
Control Register
CSEL1
CSEL0
UIE
TIE
AIE


RESET
(Default)
(0)
(1)
(0)
(0)
(0)
(0)
(0)
(0)
1. The default value is the value that is read (or is set internally) after powering up from 0 V.
2. “o”indicates write-protected bits. A zero is always read from these bits.
This register is used to control interrupt event output from the /INT pin and the stop/start status of clock
and calendar operations.
1) CSEL0, 1 (Compensation interval Select 0, 1) bits
The combination of these two bits is used to set the temperature compensation interval.
CSEL0,1
CSEL1
(bit 7)
CSEL0
(bit 6)
Compensation interval
Write/Read
0
0
0.5 s
0
1
2.0 s Default
1
0
10 s
1
1
30 s
2) UIE (Update Interrupt Enable) bit
When a time update interrupt event is generated (when the UF bit value changes from 0 to 1), this bit's value
specifies if an interrupt signal is generated (/INT status changes from Hi-Z to low) or is not generated (/INT status
remains Hi-Z).
When a “1”is written to this bit, an interrupt signal is generated (/INT status changes from Hi-Z to low) when an
interrupt event is generated.
When a “0”is written to this bit, no interrupt signal is generated when an interrupt event occurs.
UIE
Data
Function
Write/Read
0
When a time update interrupt event occurs, an interrupt signal is not generated
or is canceled (/INT status changes from low to Hi-Z).
1
When a time update interrupt event occurs, an interrupt signal is generated
(/INT status changes from Hi-Z to low).
 When a time update interrupt event occurs, low-level output from the /INTpin occurs only when
the value of the control register's UIE bit is “1”. This /INT status is automatically cleared (/INT
status changes from low to Hi-Z) earliest 7.813ms after the interrupt occurs.
3) TIE (Timer Interrupt Enable) bit
When a fixed-cycle timer interrupt event occurs (when the TF bit value changes from “0”to “1”), this bit's value
specifies if an interrupt signal is generated (/INT status changes from Hi-Z to low) or is not generated (/INT status
remains Hi-Z).
When a “1”is written to this bit, an interrupt signal is generated (/INT status changes from Hi-Z to low) when an
interrupt event is generated.
When a “0”is written to this bit, no interrupt signal is generated when an interrupt event occurs.
TIE
Data
Function
Write/Read
0
When a fixed-cycle timer interrupt event occurs, an interrupt signal is not
generated or is canceled (/INT status changes from low to Hi-Z).
1
When a fixed-cycle timer interrupt event occurs, an interrupt signal is
generated (/INT status changes from Hi-Z to low).
*When a fixed-cycle timer interrupt event has been generated low-level output from the /INT pin
occurs only when the value of the control register's TIE bit is 1. Earliest 7.813 ms after the interrupt
occurs, the /INT status is automatically cleared (/INT status changes from low to Hi-Z).

RA8804 CE
Page - 14 ETM60E-02
4) AIE (Alarm Interrupt Enable) bit
When an alarm timer interrupt event occurs (when the AF bit value changes from “0”to “1”), this bit's value
specifies if an interrupt signal is generated (/INT status changes from Hi-Z to low) or is not generated (/INT status
remains Hi-Z).
When a “1”is written to this bit, an interrupt signal is generated (/INT status changes from Hi-Z to low) when an
interrupt event is generated.
When a “0”is written to this bit, no interrupt signal is generated when an interrupt event occurs.
AIE
Data
Function
Write/Read
0
When an alarm interrupt event occurs, an interrupt signal is not generated or is
canceled (/INT status changes from low to Hi-Z).
1
When an alarm interrupt event occurs, an interrupt signal is generated
(/INT status changes from Hi-Z to low).
 When an alarm interrupt event has been generated low-level output from the /INT pin occurs only
when the value of the control register's AIE bit is “1””. This setting is retained until the AF bit value
is cleared to zero. (No automatic cancellation)
For details, see “8.7. Alarm Interrupt Function”.
[Caution]
(1) The /INT pin is a shared interrupt output pin for three types of interrupts. It outputs the OR'ed result of these interrupt outputs.
When an interrupt has occurred (when the /INT pin is at low level), the UF, TF,read AF flags to determine which flag has a value
of 1”
(this indicates which type of interrupt event has occurred).
(2) The status of update interrupt, timer interrupt and alarm interrupt can be checked by software polling without using the /INT pin.
In this case, write “0”into UIE,TIE,and AIE bits to avoid physical interrupt generation and thus reduce power consumption.
5) RESET bit
When highly precise synchronization of both time or timer is necessary, use RESET.
RESET
Data
Function
Write/Read
0
The read value of RESET is 0, always.
writes 0, it is invalid.
1
writes 1, it executes reset of count-down-chain from 32.768kHz.
The detailed function of RESET.
For example.
S is start condition. P is stop condition.
[ Write access to RESET-bit.]
S---Slave address(w)---ACK1---0Fh---ACK2---01h---ACK3---P.
RESET executes and it keeps between P from ACK3.
After P, RESET-bit clears automatically.
reset area of circuit are the count-down-chain of 2 Hz from 16 kHz, are cleared.
As for next update timing of a Seconds counter from RESET.
That range is 1000 ms-30.5 s from just 1000 ms.
RESET affects time update interruption, alarm, FOUT and timer.
but, it doesn't affect 32 kHz output.
Note:
RESET is released by the reception of a START or RE-START condition before receiving an STOP condition.
The Single write access is recommended for precise RESET.
Unnecessary use of RESET, will be the cause of delay error of time.

RA8804 CE
Page - 15 ETM60E-02
8.3. Fixed-cycle Timer Interrupt Function
The fixed-cycle timer interrupt generation function generates an interrupt event periodically at any fixed cycle set
between 244.14µs and 32 years.
When an interrupt event is generated, the /INT pin goes to low level and “1”is set to the TF bit to report that an
event has occurred. (However, when a fixed-cycle timer interrupt event has been generated low-level output from
the /INT pin occurs only when the value of the control register's TIE bit is “1”. Earliest 7.813 ms after the interrupt
occurs, the /INT status is automatically cleared (/INT status changes from low-level to Hi-Z).
Example of
/INT operation
TIE ="1"
TE="0""1"
7.813ms
Min.
period
TIE="1""0"
8.3.1. Diagram of fixed-cycle timer interrupt function
TIE bit
/INT output
TF bit
Event occurs
TE bit
tRTN
tRTN
tRTN
period
period
period
tRTN
period
"1"
"0"
"1"
"0"
Hi-z
"L"
"1"
"0"
Even when the TF
bit is cleared to zero,
the /INT status does
not change.
Even when the TE bit is
cleared to zero, /INT
remains low during the
tRTN time.
Operation of fixed-cycle timer
When the TE bit value changes from "0"to "1"the fixed-cycle timer function starts.
The counter always starts counting down from the preset value when the TE value changes from "0" to "1".
RTC internal operation
Write operation
Fixed-cycle timer starts
Fixed-cycle timer stops
(1)
(1)
(2)
001h000h
(3)
(4)
(5)
"1"
(6)
(7)
(7)
(7)
(8)
(9)
(1) When a “1”is written to the TE bit, the fixed-cycle timer countdown starts from the preset value.
(2) A fixed-cycle timer interrupt event starts a countdown based on the countdown period (source clock). When the
count value changes from 01h to 00h, an interrupt event occurs.
After the interrupt event occurs, the counter automatically reloads the preset value and again starts to count
down. (Repeated operation)
(3) When a fixed-cycle timer interrupt event occurs, “1”is written to the TF bit.
(4) When the TF bit = “1”its value is retained until it is cleared to zero.
(5) If the TIE bit = 1 when a fixed-cycle timer interrupt occurs, /INT pin output goes low.
If the TIE bit = “0”when a fixed-cycle timer interrupt occurs, /INT pin output remains Hi-Z.
(6) Output from the /INT pin remains low during the tRTN period following each event, after which it is
automatically cleared to Hi-Z status.
/INT is again set low when the next interrupt event occurs.
(7)When a 0 is written to the TE bit, the fixed-cycle timer function is stopped and the /INT pin is set to Hi-Z status.
When /INT=low, the fixed-cycle timer function is stopped. The tRTN period is the maximum amount of time
before the /INT pin status changes from low to Hi-Z.
(8)As long as /INT=low, the /INT pin status does not change when the TF bit value changes from “1”to “0”.
(9)When /INT=low, tshe /INT pin status changes from low to Hi-Z as soon as the TIE bit value changes from “1”
to ”0”.

RA8804 CE
Page - 16 ETM60E-02
8.3.2. Related registers for function of fixed-cycle timer interruption
The fixed-cycle timer interrupt generation function generates an interrupt event periodically at any fixed cycle set
between 244.14 s and 16777215 minutes.
Address
Function
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Read
Write
0B
Timer Counter 0
128
64
32
16
8
4
2
1


0C
Timer Counter 1
32768
16384
8192
4096
2048
1024
512
256


0D
Extension Register
TEST
WADA
USEL
TE
FSEL1
FSEL0
TSEL1
TSEL0


0E
Flag Register


UF
TF
AF

VLF
VDET

Clear only
0F
Control Register
CSEL1
CSEL0
UIE
TIE
AIE


RESET


1B
Setup of Timer
TSTP
TRES








1C
Monitor of Timer 0
128
64
32
16
8
4
2
1

-
1D
Monitor of Timer 1
32768
16384
8192
4096
2048
1024
512
256

-
1E
Monitor of Timer 2
8388608
4194304
2097152
1048576
524288
262144
131072
65536

-
1F
Timer Counter 2
8388608
4194304
2097152
1048576
524288
262144
131072
65536


Timer Counter 0, 1, 2 are preset value of Timer.
Monitor of Timer 0, 1, 2 are current count value of a timer.
Before entering settings for operations, we recommend writing a “0”to the TE and TIE bits to prevent
hardware interrupts from occurring inadvertently while entering settings.
When the RESET bit value is “1”the time update interrupt function does not operate.
When the fixed-cycle timer interrupt function is not using, the fixed-cycle timer counter (0Bh, 0Ch,1Fh),
these can use as a RAM register. In such cases, stop the fixed-cycle timer function by writing “0”to the
TE and TIE bits.
When writes 00h to all timer counter, Timer countdown are stop, and new Timer interruption are
inhibited.
1) TSEL0, 1 (Timer Select 0, 1) bits
The combination of these two bits is used to set the countdown period (source clock) for the fixed-cycle timer
interrupt function (four settings can be made).
TSEL0,1
TSEL1
(bit 1)
TSEL0
(bit 0)
Source clock
Auto reset time
tRTN (Min.)
Effects of
RESET bits
Write/Read
0
0
4096 Hz / Once per 244.14 µs
122µs

0
1
*Default 64 Hz / Once per 15.625ms
7.813ms
Does not operate
when the RESET
bit value is “1”.
1
0
Second” update / Once per second
7.813ms
1
1
“Minute” update / Once per minute
7.813ms
1. tRTN is different with a source clock in automatic release time. TF is not cleared automatically.
2. Source clock of 1Hz does not synchronize to update of a second. (It is a 1Hz clock for timers)
3. Source clock 1/60Hz synchronize in update of a minute.
4. A preset value, it is loaded with the first source clock of a timer counter after having set TE.
5. Therefore, two periods of source clocks are needed at the maximum till the first countdown starts after
TE=”1”.
Delay of the first countdown. Preset value is 3.
Delay
TE
Period of Clock
Source Clock
TF ”0” ⇒“1”
TF
3
2
1
undefine
Down counter
3
3
Preset Value
Load preset value
When timer count value is 0 from 1, preset value is loaded at the same time by a
timer. Therefore, can't monitor 0 of timer counter.