Fluke 9100 Series User manual

9100 Series
9100A-017
Vector Output I/O Module
Service Manual
P/N 855531
August 1989
© 1989, John Fluke Mfg. Co., Inc. All rights reserved. Litho in U.S.A.

LIMITED WARRANTY
John Fluke Mfg. Co., Inc. (Fluke) warrants your 9100A-017 Vector Output I/O Module to be free from
defects in material and workmanship under normal use and service for one (1) year from the date of
shipment. Software and firmware products are provided “AS IS.” We do not warrant that software or
firmware products will be error free, operated without interruption or that all errors will be corrected. This
warranty extends to you if you are the original purchaser and does not apply to fuses, batteries, or any
product which, in our sole opinion, has been subject to misuse, alteration, or abnormal conditions of
operation or handling.
To obtain warranty service, contact a Fluke Service Center or send the product, with the description of the
difficulty, postage prepaid, to the nearest Fluke Service Center. Fluke assumes no risk for damage in
transit.
Fluke will, at our option, repair or replace the defective product free of charge. However, if we determine
that the failure was caused by misuse, alteration, or abnormal condition of operation or handling, you will
be billed for the repair. The repaired product will be returned to you, transportation prepaid.
THIS WARRANTY IS EXCLUSIVE AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTY OF MERCHANTABILITY OR
FITNESS FOR A PARTICULAR PURPOSE OR USE. FLUKE WILL NOT BE LIABLE FOR ANY SPECIAL,
INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES OR LOSS WHETHER IN CONTRACT, TORT,
OR OTHERWISE.

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Table of Contents
______________________________________________________________________________
SECTION TITLE PAGE
1 Introduction and Specifications ...........................1-1
INTRODUCTION1 ............................................1-1
SPECIFICATIONS ...........................................1-1
Theory of Operation .......................................2-1
VECTOR OUTPUT I/O MODULE OVERVIEW ........................2-1
INPUT SECTION THEORY OF OPERATION ........................2-5
Mainframe to Bus Interface Functional Block .........2-5
MAINFRAME ADDRESSING OF THE MODULE .............2-5
CUSTOM CHIP SELECTION ..........................2-6
Custom Chip Functional Block ........................2-8
Clock and Enable Mux Functional Block ...............2-9
CLOCK AND ENABLE MUX OPERATION .................2-9
General Control Latch Functional Block ..............2-11
CONTROL REGISTER ...............................2-12
DATA COMPARISON INPUTS .........................2-12
FUSE DETECTION .................................2-12
DATA COMPARISON AND GENERAL INTERRUPTS .........2-13
DATA COMPARE EQUAL OUTPUT PIN ..................2-13
OPERATION OF GENERAL CONTROL LATCH BLOCK .......2-13
Connector Code Functional Block .....................2-16
Input Protection Functional Block ...................2-16
OUTPUT SECTION THEORY OF OPERATION .......................2-16
Main PCA to Top PCA Interface Functional Block ......2-17
ADDRESSING .....................................2-18
Internal Oscillator Control Functional Block ........2-20
Output Control Functional Block .....................2-20
RAM Select Functional Block .........................2-21
CHIP COUNTER OPERATION .........................2-22
SSLOGIC (Start/Stop Logic) Functional Block .........2-22
SIGNAL POLARITY/CONTROL REGISTER ...............2-22
DRIVE CLOCK SELECTION ..........................2-23
HANDSHAKE SYNCHRONIZATION ......................2-24
VECTOR DRIVE COMPLETE LOGIC ....................2-25
Vector Address Functional Block .....................2-26
Vector Pattern RAM Functional Block .................2-26
Vector Control RAM Functional Block .................2-26
Loop Control Functional Block .......................2-27
Capture Clock Functional Block ......................2-28
Drive Status Functional Block .......................2-28
Output Protection Functional Block ..................2-29

-ii-
SECTION TITLE PAGE
3 Maintenance ...............................................3-1
INTRODUCTION .............................................3-1
CHANGING THE VECTOR OUTPUT I/O MODULE FUSE ...............3-1
CLEANING .................................................3-2
VECTOR OUTPUT I/O MODULE SELF TEST .......................3-2
DISASSEMBLY ..............................................3-2
TROUBLESHOOTING ..........................................3-3
General Information .................................3-3
4 List of Replaceable Parts .................................4-1
INTRODUCTION .............................................4-3
HOW TO OBTAIN PARTS ......................................4-3
ADDITIONAL INFORMATION ...................................4-4
5 Schematic Diagrams ........................................5-1

-iii-
List of Tables
______________________________________________________________________________
TABLE TITLE PAGE
1-1. Vector Output I/O Module Specifications ...................1-1
2-1. Custom Chip Pin Description ...............................2-11
2-2. Clock and Enable Mux Truth Table ..........................2-12
2-3. VHI and VLO for TTL and CMOS Logic Levels .................2-15
2-4. Dip-Clip and Calibration Module Configuration Codes .......2-17
2-5. Connector Code Examples ...................................2-18
2-6. Vector I/O Module Output Section Address Map ..............2-19
2-7. U25 Drive Register 2 Bit Description (Write @ $D0X21) .....2-20
2-8. U5 Register Bit Description (Write @ $D0X01) ..............2-21
2-9. U6 Register Bit Description (Write @ $D0X11) ..............2-23
2-10. U25 ID/Status Register Bit Description (Read @ $D0X01) ....2-29
4-1. 9100A-017 Vector I/O Final Assembly .......................4-5
4-2. A1 Main PCA ...............................................4-8
4-3. A2 Top PCA ................................................4-10
4-4. Module Revision Information ...............................2-12

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-v-
List of Figures
______________________________________________________________________________
FIGURE TITLE PAGE
2-1. Input Section Functional Block Diagram ....................2-3
2-2. Output Section Functional Block Diagram ...................2-4
2-3. Input Section Address Decoding Summary ....................2-7
2-4. Address Decoding Example ..................................2-8
2-5. Hot-Bit Decoding Examples .................................2-9
2-6. Bus Interface Timing Diagram ..............................2-10
2-7. I/O Module Control and Interrupt Registers ................2-14
2-8. Custom Chip Voltage Level Detection .......................2-15
4-1. 9100A-017 Final Assembly ..................................4-6
4-2. A1 Main PCA ...............................................4-9
4-3. A2 Top PCA ................................................4-11

-vi-

1-1
Section 1
Introduction and Specifications
INTRODUCTION
This manual presents service information for the 9100A-017 Vector Output
I/O Module. Included are a theory of operation, general maintenance
procedures, performance tests, troubleshooting information, a list of
replacement parts, and schematic diagrams.
SPECIFICATIONS
Table 1-1 contains the specifications for the Vector Output I/O Module.
NOTE
Output specifications for Table 1-1 were obtained using
the Y9100-102 Card Edge Interface Module into 10 LSTTL
loads. Results may vary depending on the impedance,
length, and shielding of the connector used. (Output
timing is measured at 50% of signal amplitude.)
Table 1-1. Vector Output I/O Module Specifications
______________________________________________________________________________
VECTOR OUTPUT I/O MODULE OUTPUT
(into 10 LSTTL loads with card edge connector attached):
Module Vector Size ......................... 8192 vectors, 40 channels wide.
Maximum Vector Pattern (4 Modules) ......... 8192 vectors, 160 channels wide.
Vector Looping ............................. Up to 65536 repetitions of
one vector set.
Output Logic Levels:
High ................................... 3.7V minimum (6.0 mA source).
Low .................................... 0.4V maximum (6.0 mA sink).
INT CLK (internal clock) ................... 1, 5, 10, or 20 MHz (±100
ppm).
DR CLK (external clock) .................... 25 MHz maximum. (This frequency
maximum may be exceeded in some
cases based upon application
and hardware interfacing.)
Clock to Vector Out (tdel):
INT CLK Out to Vector Out Delay ........ 37 ns typical, 45 ns maximum.
DR CLK In to Vector Out Delay .......... 50 ns typical, 58 ns maximum.
______________________________________________________________________________

1/Introduction and Specifications
1-2
Table 1-1. Vector Output I/O Module Specifications (cont.)
______________________________________________________________________________
WAIT (Handshake) Setup Time (twsu) ......... 42.5 ns maximum (35 ns typical)
from WAIT acknowledgement until
next clock cycle drives vector.
If the setup time is not met,
the next clock drives out the
vector. Minimum WAIT pulse
width is 10 ns.
Single Module Channel to Channel Skew* ..... 6 ns maximum (1 ns typical).
Module to Module Channel Skew* ............. 10 ns maximum (1 ns typical).
TRISTATE-:
Activation (txout) ..................... Output source/sink released 25
ns maximum (20 ns typical)
after TRISTATE- goes low.
Minimum TRISTATE- pulse width
is 10 ns.
Recovery (txsu) ........................ TRISTATE- must go high no later
than 5 ns after the rising edge
of the INT CLK or no later than
10 ns after the programmed edge
of DR CLK for the vector to be
output by that clock, otherwise
that vector is only driven
internally and the output is
held tri-stated, effectively
skipping that vector.
Output Series Termination .................. 33 Ohms
Capture Clock:**
INT CLK ................................ Capture Clock clocks 42.5 ns
±5 ns after the falling edge
of INT CLK.
DR CLK ................................. Capture Clock clocks 55 ns
±10 ns after non-clocking edge
of DR CLK (approximate 50% duty
cycle).
START, STOP, and ENABLE:
START, STOP Pulse Width .................... 10 ns minimum.
INT CLK
START Setup Time .................. 30 ns minimum.
STOP Setup Time ................... 30 ns minimum.
ENABLE Setup Time ................. 25 ns minimum.
ENABLE Hold Time .................. 20 ns minimum.
______________________________________________________________________________
* Skew measurement assumes equal loading. Differences in capacitance
may affect results.
** Capture clock may be adjusted in approximate 15 ns steps by using the
setoffset command (see the 9100 Series TL/1 Reference Manual).
______________________________________________________________________________

1/Introduction and Specifications
1-3
Table 1-1. Vector Output I/O Module Specifications (cont.)
______________________________________________________________________________
DR CLK
START Setup Time .................. 20 ns minimum.
STOP Setup Time ................... 20 ns minimum.
ENABLE Setup Time ................. 15 ns minimum.
ENABLE Hold Time .................. 35 ns minimum.
Input Impedance:
DR CLK ................................. 40 kilohm minimum, 35 pF maximum.
TRISTATE- .............................. 40 kilohm minimum, 80 pF maximum.
WAIT ................................... 40 kilohm minimum, 50 pF maximum.
VECTOR OUTPUT I/O MODULE INPUT:
Input Impedance ............................ 50 kilohm minimum, 90 kilohm
typical; 100 pF maximum, 65 pF
typical.*
Operating Voltage Range .................... -0.5V to +5.5V (all lines).
Input/Output Protection .................... +10V/-5V for one minute
maximum, one line only (all
lines).
Input Thresholds:
________________________________________________
| | | |
| TTL | CMOS | |
|_________|__________|___________________________|
| | | |
| 5.0V | 5.0V | \ |
| | | >- Guaranteed HIGH |
| 2.6V | 3.4V | < |
| | | >- HIGH or INVALID |
| 2.1V | 2.9V | < |
| | | >- Guaranteed INVALID |
| 1.0V | 1.2V | < |
| | | >- LOW or INVALID |
| 0.6V | 0.8V | < |
| | | >- Guaranteed LOW |
| 0.0V | 0.0V | / |
|_________|__________|___________________________|
CLOCK, START, STOP, and ENABLE Inputs:
Thresholds:
Logic LOW ......................... 0.8V maximum.
Logic HIGH ........................ 2.0V minimum.
Input Current .......................... 125 uA maximum.
Input/Output Protection ................ +10V/-5V for one minute
maximum, one line only.
______________________________________________________________________________
* Input capacitance includes the Y9100A-102 Card Edge Interface Module.
______________________________________________________________________________

1/Introduction and Specifications
1-4
Table 1-1. Vector Output I/O Module Specifications (cont.)
______________________________________________________________________________
Transition Counter:
Maximum Frequency ...................... 10 MHz minimum.
Maximum Count (Transition Mode) ........ 8388608 (23 bits) counts
(+ overflow).
Frequency Accuracy (Frequency Mode) .... ±250 ppm ±2 Hz.
Stop Counter:
Maximum Frequency ...................... 10 MHz.
Maximum Count .......................... 65535 clocks.
Clock:
Maximum Frequency ...................... 10 MHz.
Minimum Pulse Width .................... 50 ns.
Timing for Synchronous Measurements:
Maximum Frequency of Clock ............. 10 MHz.
Maximum Frequency of Data .............. 5 MHz.
Data Setup Time ........................ 30 ns minimum.
Data Hold Time ......................... 30 ns minimum.
Minimum Pulse Width
(Start/Stop/Enable/Clock) ............ 50 ns.
Start Edge Setup Time
(before clock edge, for clock to
be recognized) ....................... 0 ns minimum.
Stop Edge Setup Time
(before clock edge, for clock
edge to not be recognized) ........... 5 ns minimum.
Enable Setup Time
(before clock edge, for clock
edge to be recognized) ............... 0 ns minimum.
Enable Hold Time
(after clock edge, for clock
edge to be recognized) ............... 10 ns minimum.
Data Timing for Asynchronous Measurements:
Maximum Frequency ...................... 10 MHz.
Minimum Pulse Width (HIGH or LOW) ...... 50 ns.
Minimum Pulse Width (tri-state) ........ 150 ns.
Data Compare Equal:
Minimum Pulse Width of
Data and Enable ...................... 75 ns.
PHYSICAL SPECIFICATIONS
Operating Temperature:
5 to 27oC, 95% RH maximum (non-condensing).
27 to 40oC, RH decreasing linearly from 95% to 50% (non-condensing).
Storage/Shipping Temperature:
20 to 60oC, 8% to 80% RH (non-condensing).
______________________________________________________________________________

2-1
Section 2
Theory of Operation
VECTOR OUTPUT I/O MODULE OVERVIEW
The 9100A-017 Vector Output I/O Module adds 40 lines of input and
high-speed output capability to the 9100A/9105A mainframe. Up to four
Vector Output I/O Modules may be connected to the mainframe for a
maximum of 160 channels of vector output and stimulus measurement. Any
number of the 160 channels may be used simultaneously.
The Vector Output I/O Module has the same input measurement capabilities
as the 9100A-003 Parallel I/O Module. The Vector Output I/O Module is
capable of generating cyclic redundancy checks (CRCs), measuring
frequency or taking event counts, and recording logic level histories.
The input measurements can be synchronized to the 9100A/9105A
microprocessor-specific Pod, to external events (using the module
external START, STOP, ENABLE, and CLOCK lines), to a software strobe, or
to a free-running clock. The input section may also be synchronized to
the output section by using the Capture Clock (a user-programmable clock
generated during vector driving). The module also has a programmable
“breakpoint” capability. The input thresholds may be set to either “TTL”
and “CMOS” levels.
The Vector Output I/O Module can drive vector patterns synchronized to a
user-supplied external clock (at up to 25 MHz), to a user-selectable
internal clock at 1, 5, 10, or 20 MHz, to a software strobe, or to the
Pod. The output can be latched to a level (either high or low) on any of
the module’s lines to test devices using either a “writeword” or
“writepin” command. Each pin can be driven either high or low, or be
tri-stated. An external input is available to provide handshaking
synchronization with the UUT. All 40 outputs can be simultaneously
tri-stated by an external signal.
The Vector Output I/O Module consists of two assemblies: the Main PCA
(9100A-4021) and the Top PCA (9100A-4022).
The Main PCA provides the interface to the mainframe, and is used for
input measurements. The Main PCA includes the inputs for the external
synchronization lines START, STOP, ENABLE, and CLOCK. It also contains
some support circuitry for vector driving, including:
o bus interfacing circuitry for the Top PCA.
o vector drive internal clock control.
o vector loop control circuitry.

2/Theory of Operation
2-2
o vector drive status register.
o six-pin jack for control signals for vector driving.
The Top PCA is used primarily for vector output, although it also
provides the 40-channel input signals, Clip Module Connector Code, and
ready button signals to the input section on the Main PCA. It also
generates the Capture Clock (available as an input sync mode).
The input section of the Vector Output I/O Module consists of the
following six functional blocks (See Figure 2-1):
o Mainframe to Bus Interface Functional Block.
o Custom Chip Functional Block.
o Clock and Enable Mux Functional Block.
o General Control Latch Functional Block.
o Connector Code Functional Block.
o Input Protection Functional Block.
The output section consists of the following twelve functional blocks
(See Figure 2-2):
o Main PCA to Top PCA Interface Functional Block.
o Internal Oscillator Control Functional Block.
o Output Control Functional Block.
o RAM Select Functional Block.
o SSLOGIC (Start/Stop Logic) Functional Block.
o Vector Address Functional Block.
o Vector Pattern RAM Functional Block.
o Vector Control RAM Functional Block.
o Loop Control Functional Block.
o Capture Clock Functional Block.
o Drive Status Functional Block.
o Output Protection Functional Block.

2/Theory of Operation
2-3
Figure 2-1. Input Section Functional Block Diagram

2/Theory of Operation
2-4
Figure 2-2. Output Section Functional Block Diagram

2/Theory of Operation
2-5
INPUT SECTION THEORY OF OPERATION
NOTE
All of the input section circuitry is located on the
Main PCA unless otherwise indicated.
Mainframe to Bus Interface Functional Block
The bus interface block connects the 9100A/9105A mainframe
microprocessor bus to the Vector Output I/O Module. The module is a
memory-mapped device, with all control performed by writing to the
module memory space. The control bus enters the module on connector J1
and consists of the following lines:
o Seven address lines, A1 through A7.
o Eight data lines, D0 through D7.
o Two differential strobe lines, STROBE+ and STROBE-.
o One control line, R/W-.
The two mainframe strobe signals, STROBE+ and STROBE-, are translated by
U9 into the module STROBE- signal. STROBE- is the key signal that
qualifies all of the bus activities and is used by U7 to latch the
addresses and R/W-, and to enable the data bus buffer. The STROBE-
signal, in conjunction with the latched version of the R/W-, generates
the read strobe (RD-) and the write strobe (WR-). The STROBE- signal and
the decoder U6 provide address decoding by generating signals AD8-
through ADE- and ALLCHIP-. Signals AD8- through ADC- and ALLCHIP- are
input to AND Gates U3 and U5 to provide the custom chip selects CS0-
through CS4-. Signals ADD- and ADE- are used as register select lines.
(The mainframe STROBE- signal has already had some amount of address
decoding. STROBE- for any particular module is only active on accesses
to addresses $DXXXX, with address bit 0 = 1, and with the proper “hot
bit” identifying the module. See the heading, “Mainframe Addressing of
the Module”, further on in this section for more information on hot-bit
decoding).
MAINFRAME ADDRESSING OF THE MODULE
Memory reserved for module control occupies the mainframe addresses
$D0000 through $DFFFF. Out of this 64K-byte block, four modules can be
addressed. Lower Data Strobe (LDS-) on the mainframe qualifies all
module addresses; thus address bit 0 is effectively a 1. Addresses
within this space using Upper Data Strobe (UDS-) are unused. Figure 2-3
shows a summary of module input section address decoding. Figure 2-4
provides an addressing example.
Each of the four modules is controlled via “hot-bit decoding” of the
mainframe address lines A8 through A11. This method of decoding allows
any combination of modules to be addressed simultaneously. Figure 2-5

2/Theory of Operation
2-6
shows the third least significant digit of the 5-digit hex module
address broken down into binary format. The position of the set bit(s)
determines the module(s) to be addressed.
The Vector Output I/O Module bus interface timing diagram (Figure 2-6)
shows the signals contained in the bus interface block during a read and
write cycle. Each transition point (indicated by the letters A through
I) designates the following actions:
A. The address appears on the bus. R/W- goes high, signifying a read
cycle.
B. STROBE- goes low, allowing RD- and CSX- to go active. Data bus
transceiver U8 turns on, driving data from the module to the
mainframe. Addresses and R/W- are latched by U7 and are guaranteed
valid.
C. Valid read data appears on the data bus.
D. STROBE-, RD-, and CSX- return high. Read data is guaranteed valid at
this point.
E. End of the read cycle.
F. The address appears on the bus. R/W- goes low, signifying a write
cycle.
G. STROBE- goes low, allowing WR- and CSX- to go active. Data bus
transceiver U8 turns on, receiving data from the mainframe to the
module. Addresses and R/W- are guaranteed valid.
H. STROBE-, WR-, and CSX- return high. Write data is latched into the
module registers.
I. End of the write cycle.
CUSTOM CHIP SELECTION
The Bus Interface also decodes address lines A1 through A7 from the
mainframe to determine which custom chips are enabled. As the address
signals enter the Main PCA through J1, the address lines are latched by
U7 (the latch signal is STROBE-). Address lines A7 through A4 are used
as address inputs for the decoder (U6). The outputs of U6 are gated to
determine which custom chip is enabled. Any one of the five custom chips
can be addressed, or all five of the chips can be addressed
simultaneously (no other combination of the custom chips can be
addressed within a module).
For example, to select custom chip U100, the input at U7-13 (A7) from
the address bus of the mainframe must be at logic high and U7-18 (A4),
U7-17 (A5), and U7-14 (A6) must be at logic low. When STROBE- occurs, U7
latches the logic levels on these pins. On the output lines of U7,
LAT-A7 is set at logic high, and LAT-A4, LIT-A5, and LAT-A6 are logic

2/Theory of Operation
2-7
Figure 2-3. Input Section Address Decoding Summary

2/Theory of Operation
2-8
Figure 2-4. Address Decoding Example
low. U6 decodes the latched address lines and sets output line AD8- low.
The logic low on AD8- is gated through U5 and sets up a logic low on
CS0-, thereby enabling custom chip U100. To select custom chip U100 on
Module 3, the address $D0481 is used.
A custom chip may be addressed individually, or all custom chips may be
addressed simultaneously. Address bits A4 through A7 determine the
custom chip selection. To address all chips, an address in the form
$DXXFX must be used (X means don’t care). This address causes the
ALLCHIP- signal (U6-7) to go active, which when gated through U5 and U3,
makes all five chip selects CS0- through CS4- active.
Custom Chip Functional Block
The custom chips each contain eight channels of data acquisition. Each
channel performs 16-bit Cyclic Redundancy Checking (CRC), 23-bit (with
overflow) transition counting, 3-bit asynchronous level history
recording, 3-bit synchronous level history recording, and 1-bit data
comparison. The custom chips are used for module control, and are