Fluke 9100A-017 User manual

9100A Series
9100A-017
Vector Output
I/O Module
P/N 855437
May 1989
©1989, John Fluke Mfg. Co., Inc.
All rights reserved. Litho in U.S.A.

LIMITED WARRANTY
John Fluke Mfg.Co., Inc. (Fluke) warrants your 9100A-017 Vector Output I/O
Module to be free from defects in material and workmanship under normal
use and service for one (1) year from the date of shipment. Software and
firmware products are provided "AS IS." We do not warrant that software or
firmware products will be error free, operated without interruption or that all
errors will be corrected. This warranty extends to you if you are the original
purchaser and does not apply to fuses, batteries, or any product which, in our
sole opinion, has been subject to misuse, alteration, or abnormal conditions
of operation or handling.
To obtain warranty service, contact a Fluke Service Center or send the
product, with the description of the difficulty, postage prepaid, to the nearest
Fluke Service Center. Fluke assumes no risk for damage in transit.
Fluke will, at our option, repair or replace the defective product free of charge.
However, if we determine that the failure was caused by misuse, alteration, or
abnormal condition of operation or handling, you will be billed for the repair.
The repaired product will be returned to you, transportation prepaid.
THIS WARRANTY IS EXCLUSIVE AND IS IN LIEU OF ALL OTHER
WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
TO ANY IMPLIED WARRANTY OF MERCHANTABILITY OR FITNESS FOR
A PARTICULAR PURPOSE OR USE. FLUKE WILL NOT BE LIABLE FOR
ANY SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES
OR LOSS WHETHER IN CONTRACT, TORT, OR OTHERWISE.

iii
Contents
Section Title Page
1. Introduction ...................................................................................1-1
1-1. THE VECTOR OUTPUT I/O MODULE ..............................1-1
1-2. HIGH SPEED PARALLEL STIMULUS ...............................1-1
1-3. BUS EMULATION ..............................................................1-2
1-4. TEST VECTOR PATTERN GENERATION ........................1-2
1-5. USER OPERATIONS .........................................................1-3
2. Specifications ................................................................................2-1
2-1. SPECIFICATIONS ..............................................................2-1
3. Vector Output Operation ..............................................................3-1
3-1. INTRODUCTlON ................................................................3-1
3-2. CLOCK SELECTION ..........................................................3-1
3-3. VECTOR LOADING ...........................................................3-2
3-4. VECTOR DRIVING .............................................................3-2
3-5. LOOP CONTROL ...............................................................3-2
3-6. HANDSHAKING .................................................................3-2
3-7. STOPPING VECTOR DRIVING .........................................3-3
3-8. TRISTATE CONTROL ........................................................3-4
3-9. COMPLETION STATUS .....................................................3-5
4. Hardware ........................................................................................4-1
4-1. PHYSICAL DESCRIPTION ................................................4-1
4-2. CONNECTING THE MODULE
TO THE MAINFRAME .......................................................4-5
4-3. PERFORMING THE MODULE SELF TEST ......................4-6
4-4. CALIBRATING THE MODULE ...........................................4-6
4-5. I/O Module to External and Capture ......................... 4-7
4-6. I/O Module to Pod ..........................................................4-8

iv
Section Title Page
4-7. CONNECTING THE MODULE
TO THE UUT .................................................................... 4-9
4-8. Using the Clip Modules ................................................. 4-9
4-9. Connecting the External Lines ...................................... 4-10
4-10. Using the Card Edge Fixture Kit ................................... 4-10
4-11. SYNCHRONIZING THE MODULE TO THE UUT .............. 4-11
4-12. External Sync Mode ...................................................... 4-11
4-13. Pod Sync Mode ............................................................. 4-13
4-14. Freerun Sync Mode ...................................................... 4-14
4-15. Internal Sync Mode ....................................................... 4-14
4-16. Capture Mode ............................................................... 4-15
4-17. SYNCHRONIZING MULTIPLE MODULE
VECTORS ......................................................................... 4-16
5. TL/1 Functions .............................................................................. 5-1
5-1. INTRODUCTION ............................................................... 5-1
5-2. CLOCKFREQ ..................................................................... 5-1
5-3. DRIVEPOLL ....................................................................... 5-1
5-4. EDGEOUTPUT .................................................................. 5-2
5-5. ENABLEOUTPUT .............................................................. 5-3
5-6. STROBEOUTCLOCK ........................................................ 5-3
5-7. SYNCOUTPUT .................................................................. 5-3
5-8. VECTORDRIVE ................................................................. 5-3
5-9. VECTORLOAD .................................................................. 5-3
6. Using the Vector Editor ............................................................... 6-1
6-1. INTRODUCTION ............................................................... 6-1
6-2. CREATING A NEW VECTOR FILE ................................... 6-1
6-3. SOFTKEY OPERATIONS .................................................. 6-2
6-4. WORKING WITH THE VECTOR FILE .............................. 6-4
6-5. The Groups Line ........................................................... 6-4
6-6. The Display Line ........................................................... 6-5
6-7. Comment Lines ............................................................. 6-6
6-8. Data Fields .................................................................... 6-6
6-9. Control Phrases in Data Fields ..................................... 6-11
7. Applications .................................................................................. 7-1
7-1. USING THE VECTOR OUTPUT I/O MODULE ................. 7-1
7-2. BUS EMULATION .............................................................. 7-2

v
Section Title Page
7-3. TESTING THE IBM CGA VIDEO CARD ............................7-4
7-4. Fixturing the CGA Interface ...........................................7-5
7-5. Fixturing Considerations ................................................7-6
7-6 Vector File Programming ...............................................7-6
7-9. Vector File Generation ...................................................7-10
7-10. CGA Write/Read Program Example ..............................7-11
7-11. 68000 BUS VIDEO APPLICATION ....................................7-12
7-12. Testing The Video Board ...............................................7-12
7-13. Fixturing the Video Board Interface ...............................7-13
7-14. Determining Bus Cycles ................................................7-14
7-15. Determining the Write Cycle ..........................................7-14
7-16. Determining the Read Cycle ..........................................7-16
7-17. WAIT APPLICATION ..........................................................7-18
7-18. TIMING SETS .....................................................................7-19
7-19. TL/1 VECTOR FILE GENERATION ...................................7-21
Appendices
A. New TL/1 Commands ....................................................................A-1
B. I/O Module Clip/Pin Mapping .......................................................B-1
C. Keypad Reference Changes ........................................................C-1

vi

vii
Tables
Table Title Page
2-1. Vector Output I/O Module Specifications ............................2-1
7-1. CGA to Vector Output I/O Module Mapping .......................7-5
7-2. Video Board to Vector Output I/O Module Mapping ...........7-13

viii

ix
Figures
Figure Title Page
3-1. WAIT Input Timing Diagram ...............................................3-3
3-2. TRISTATE Input Timing Diagram .......................................3-4
4-1. Vector Output I/O Module Block Diagram ..........................4-4
4-2. Vector Output I/O Module Output Section ..........................4-4
4-3. Input Section Block Diagram ..............................................4-5
4-4. Pod Sync Input/Output Section Timing Diagram ................4-13
4-5. Capture Clock Timing Diagram ..........................................4-15
5-1. Vector I/O Control ...............................................................5-2
7-1. MC6845 Cycle Timing Diagram ..........................................7-7
7-2. SCN2674 Controller Timing Diagram .................................7-15
7-3. Using WAIT to Check for a Level (Method 1) .....................7-19
7-4. Using WAIT to Check for a Level (Method 2) .....................7-19
7-5. Connecting Two Modules for Timing Sets ..........................7-20

x

1-1
Section 1
Introduction
THE VECTOR OUTPUT I/O MODULE 1.1.
The Fluke 9100A-017 Vector Output I/O Module adds high
speed test stimulus capabilities to the 9100A Digital Test System
and 9105A Digital Test Station (referred to in this manual as the
Mainframe). The 9100A-017 can generate vectors (parallel pat-
terns) with clock speeds up to 25 MHz for functional testing and
troubleshooting. This speed improves card edge stimulus and
bus emulation performance for both microprocessor and non-
microprocessor bus-based cards.
HIGH SPEED PARALLEL STIMULUS 1.2.
The Vector Output I/O Module allows you to drive vectors
(parallel patterns) with four different clock modes. Vectors can
be clocked out at up to 25 MHz using an external clock source.
Each 40-pin module also provides a selectable internal clock
generator of 1, 5, 10, or 20 MHz. The clock can be qualified by
external lines that control start, stop, and enable. A handshaking
line allows additional synchronization between the module and
the unit under test (UUT) bus. Each pin can be tri-stated indi-
vidually for any number of vectors by program control in a vec-
tor file. An external tri-state input allows all 40 pins to be tri-
stated simultaneously.
Parallel vectors may be up to 8192 bits deep. With 40 pins per
module, four modules may be used together for a total width of

9100A-017
1-2
160 pins. The ability to loop on a set of vectors from 1 to 65536
times makes the maximum effective depth of the test vector
536,870,912 patterns.
The Vector Output I/O Module input response capabilities are
identical to the 9100-003 Parallel I/O Module. Responses may
be gathered at clock speeds up to 10 MHz for signature analysis
and frequency/count measurement.
BUS EMULATION 1.3.
The high speed vector generation allows the module to emulate
many common busses. An external input, WAIT, can be used to
synchronize the output vectors to bus cycle events. Separate
drive and receive clocks allows bus cycles to be simulated with
many drive patterns, and data input can be sampled on com-
mand.
TEST VECTOR PATTERN GENERATION 1.4.
The generation of the test vector patterns can be accomplished in
two ways: using the 9100A Editor or downloading from another
system.
The 9100A Editor has been enhanced to effectively enter test
vectors for the 9100A-017. Vectors can be entered in user-pro-
grammable groups in hexadecimal notation, binary notation, or a
mixture of both. The vector editor displays the vector
information in the order set by the pin group assignments. Each
vector is displayed in its position in the driving sequence.
Test vectors generated on a CAE workstation can be down-
loaded into the 9100A. Once they are in the 9100A, these vec-
tors can then be translated to the 9100A vector format, making
them suitable for use with the 9100A-017.
Several new Test Language (TL/1) functions have been added to
make use of the new capabilities of the 9100A-017. Loading the
vectors from the 9100A hard disk to each module during pro-
gram execution requires a maximum of 3 seconds, with 1 sec-
ond typical.

9100A-017
1-3
USER OPERATIONS 1.5.
Users may access the new Vector Output I/O Module through
functions provided in the Operator’s Interface, TL/1, and the
Editor.
From the Operator’s Interface, all the input functions of the
original 9100A-003 Parallel I/O Module are still available for
the new Vector Output I/O Module. In addition, another soft key,
CAPTURE, has been added to the SYNC I/O MOD operation.
The user may now select CAPTURE as the input measurement
clock. This clock synchronizes the vector output section with the
input section (this clock is user-programmable and is generated
by the vector file).
To create a vector file using the 9100A Editor, you need to edit a
file of the new type, VECTOR, which has been added under
each UUT directory. The file type should be specified as
VECTOR when editing the file.
Eight new TL/1 built-in functions have been added to the 9100A
Test Language (TL/1) to support the new Vector Output I/O
Module. These functions are:
Clockfreq
Drivepoll
Edgeoutput
Enableoutput
Strobeoutclock
Syncoutput
Vectordrive
Vectorload
In addition, other TL/1 built-in functions have been modified for
use with the new Vector Output I/O Module.
The Vector Output I/O Module is designed for high-speed output
applications in which overdrive capabilities are not required. If
overdrive capabilities are a requirement, use the 9100A-003
Parallel I/O Module.

9100A-017
1-4

2-1
Section 2
Specifications
SPECIFICATIONS 2.1.
Table 2-1 contains the specifications for the Vector Output I/O
Module.
NOTE
Output specifications for Table 2-1 were obtained
using the Y9100-102 Card Edge Interface Module
into 10 LSTTL loads. Results may vary depending
on the impedance, length, and shielding of the
connector used. Output timing is measured at 50%
of signal amplitude. Typical input signal transition
times: clocks 5 ns, all others 12 ns.
Table 2-1. Vector Output I/O Module Specifications
VECTOR OUTPUT I/O MODULE OUTPUT SECTION
(into 10 LS TTL loads with card edge connector attached):
Module Vector Size ............................................... 8192 Vectors 40 Channels Wide
Maximum Vector Pattern (4 Modules)................... 8192 Vectors 160 Channels Wide
Vector Looping ...................................................... Up to 65536 Repetitions of One
Vector Set
Output Logic Levels:
High.................................................................. 3.7V minimum (6.0 mA Source)
Low................................................................... 0.4V maximum (6.0 mA Sink)
INT CLK (internal dock) ........................................ 1,5, 10, or 20 MHz (±100 ppm).
DR CLK (external dock)........................................ 25 MHz Maximum. (This may be
exceeded in some cases based
upon application and hardware
interfacing.)

9100A-017
2-2
Table 2-1. Vector Output I/O Module Specifications (cont)
Clock to Vector Out (tdel):
INT CLK Out to Vector Out Delay .....................37 ns typical, 45 ns maximum.
DR CLK in to Vector Out Delay.........................50 ns typical, 58 ns maximum.
WAIT (Handshake) Setup Time (twsu) ..................42.5 ns maximum (35 ns typical)
from WAIT acknowledgement until
next dock cycle drives vector. If the
setup time is not met, the next clock
drives out the vector. Minimum
WAIT pulse width is 10 ns.
Single Module Channel to Channel Skew * ...........6 ns Maximum (1 ns typical).
Module to Module Channel Skew *........................10 ns Maximum (1 ns typical).
TRISTATE:
Activation (txout) ...............................................Output source/sink released 25 ns
maximum (20 ns typical) after
TRISTATE goes low. Minimum
TRISTATE pulse width is 10 ns.
Recovery (txsu)................................................. TRISTATE must go high no later
than 5 ns after the rising edge of
the INT CLK or no later than 10 ns
after the clocked edge of DR CLK
for the vector to be output by that
dock, otherwise that vector is only
driven internally and the output is
held tri-stated, effectively skipping
that vector.
Output Series Termination .....................................33 Ohms
Capture Clock: **
INT CLK ............................................................Capture Clock clocks 42.5 ns ±5 ns
after the falling edge of INT CLK.
DR CLK.............................................................Capture Clock clocks 55 ns ±10 ns
after non-clocking edge of DR CLK
(approximate 50% duty cycle).
START, STOP, and ENABLE:
START, STOP pulse width.....................................10 ns minimum
INT CLK
START Setup Time ......................................30 ns minimum
STOP Setup Time ........................................30 ns minimum
ENABLE Setup Time....................................25 ns minimum
ENABLE Hold Time......................................20 ns minimum
DR CLK
START Setup Time ......................................20 ns minimum
STOP Setup Time ........................................20 ns minimum
ENABLE Setup Time....................................15 ns minimum
ENABLE Hold Time......................................35 ns minimum
Input Impedance:
DR CLK.............................................................40 KQ minimum, 35 pF maximum.
TRISTATE .........................................................40 KQ minimum, 80 pF maximum.
WAIT .................................................................40 KQ minimum, 50 pF maximum.
* Skew measurement assumes equal loading. Differences in capacitance may affect
results.
** Capture clock may be adjusted in approximate 15 ns steps by using the
setoffset
command (see the 9100 Series TL/1 Reference Manual).

9100A-017
2-3
Table 2-1. Vector Output I/O Module Specifications (cont)
VECTOR OUTPUT I/O MODULE INPUT SECTION:
Input Impedance ................................................... 50 KΩMinimum, 90 KΩtypical. 100
pF Maximum, 65 pF typical. *
Operating Voltage Range...................................... -0.5V to +5.5V (all lines)
Input/Output Protection ......................................... +10V/-5V for one minute max. one
line only (all lines).
Input Thresholds:
CLOCK, START, STOP, and ENABLE Inputs:
Thresholds:
Logic LOW................................................... 0.8V maximum.
Logic HIGH.................................................. 2.0V minimum.
Input Current .................................................... 125 µA. maximum
Input/Output Protection .................................... +10V/-5V for one minute maxi-
mum, one line only.
Transition Counter:
Maximum Frequency........................................ 10 MHz minimum.
Maximum Count (Transition Mode) .................. 8388608 (23 bits) counts
(+ overflow).
Frequency Accuracy (Frequency Mode) .......... ±250 ppm ±2 Hz
Stop Counter:
Maximum Frequency........................................ 10 MHz
Maximum Count ............................................... 65535 clocks
Clock:
Maximum Frequency........................................ 10 MHz
Minimum Pulse Width ...................................... 50ns
Timing for Synchronous Measurements:
Maximum Frequency of Clock.......................... 10 MHz
Maximum Frequency of Data ........................... 5MHz
Data Setup Time .............................................. 30 ns minimum
Data Hold Time ................................................ 30 ns minimum
Minimum Pulse Width
(Start/Stop/Enable/Clock) ............................ 50ns
Start Edge Setup Time (before clock edge,
for clock to be recognized) .......................... 0 ns minimum
* Input capacitance includes the Y9100A-102 Card Edge Interface Module.
TTL CMOS LEVEL
- - - 5.0V- - - - - - - - 5.0V- - - - - - - - - - - - - - - - - - - - - - - - - -
Guaranteed HIGH
- - - 2.6V- - - - - - - - 3.4V- - - - - - - - - - - - - - - - - - - - - - - - - -
HIGH or INVALID
- - - 2.1V- - - - - - - - 2.9V- - - - - - - - - - - - - - - - - - - - - - - - - -
Guaranteed INVALID
- - - 1.0V- - - - - - - - 1.2V- - - - - - - - - - - - - - - - - - - - - - - - - -
LOW or INVALID
- - - 0.6V- - - - - - - - 0.8V- - - - - - - - - - - - - - - - - - - - - - - - - -
Guaranteed LOW
- - - 0.0V- - - - - - - - 0.0V- - - - - - - - - - - - - - - - - - - - - - - - - -

9100A-017
2-4
Table 2-1. Vector Output I/0 Module Specifications (cont)
Stop Edge Setup Time (before clock edge,
for clock edge to not be recognized)............5 ns minimum
Enable Setup Time (before clock edge,
for clock edge to be recognized)..................0 ns minimum
Enable Hold Time (after clock edge,
for clock edge to be recognized)..................10 ns minimum
Data Timing for Asynchronous Measurements:
Maximum Frequency ........................................10 MHz
Minimum Pulse Width (HIGH or LOW) .............50 ns
Minimum Pulse Width (tri-state)........................150 ns
Data Compare Equal:
Minimum Pulse Width of Data and Enable .......75ns
PHYSICAL SPECIFICATIONS
Operating Temperature:
5 to 27°C, 95% RH maximum (non-condensing).
27 to 40°C, RH decreasing linearly form 95% to 50% (non-condensing).
Storage/Shipping Temperature:
20 to 60°C, 8% to 80% RH, (non-condensing).

3-1
Section 3
Vector Output Operation
INTRODUCTlON 3.1.
This section describes the general functions of the Vector Output
I/O Module. Each of these functions are covered more fully in
the Sections that follow.
CLOCK SELECTION 3.2.
The Vector Output I/O Module can be synchronized to a number
of different clock sources, both external and internal.
There are several methods of synchronizing the Vector Output
I/O Module to the UUT. To synchronize vector driving with a
UUT clock, the DR CLK input of the Vector Output I/O Module
can be connected to a UUT clock source. The syncoutput
command would then be set to “drclk”. To synchronize re-
sponse gathering with a UUT clock, connect the Vector Output
I/O Module CLOCK input (yellow lead) to the UUT clock
source and set the sync command to “ext”.
To synchronize the UUT to the Vector Output I/O Module, con-
nect the UUT clock input to INT CLK and set the syncoutput
command to “intfreq”. Use the clockfreq command to select ei-
ther 1, 5, 10, or 20 MHz as the clock rate. If the delay between
INT CLK and the vector data output is too long, dedicate one
output line in the 40-pin connector of the Vector Output I/O
Module as the clock input to the UUT and program that line (in
the vector file) to perform as a clock.

9100A-017
3-2
To synchronize response gathering, connect the Vector Output
I/O Module input CLOCK line to the INT CLK output and set
the sync command to “ext”. Another method would be to use
the TL/1 sync “capture” mode. This method allows you to pro-
gram clocks into the vector file to determine when data is gath-
ered in the input section of the I/O Module.
VECTOR LOADING 3.3.
The vector file to be output is loaded by the vectorload
command into the designated module(s) and resides in the
module until changed by a writeword or writepin command
directed to that module, or by another vectorload.
VECTOR DRIVING 3.4.
Vector driving has two modes of operation. In the first mode of
operation, vector driving can begin immediately upon receipt of
the proper start, enable, and clock signals. In the second mode of
operation, driving begins after the execution of the TL/1 arm
command and upon the receipt of the proper start, enable, and
clock signals. The second mode permits the simultaneous
starting of vector driving and response gathering. The vector
number (in the current vector file) that the driving begins on can
also be selected.
LOOP CONTROL 3.5.
To drive a certain pattern of vectors more than once within a
single file, use the LOOP and ENDLOOP commands within a
vector file to control the number of times and the bounds of the
pattern to be repeated. The number of loops must be set be-
tween 1 and 65536. At least 2 vectors must appear between the
LOOP and ENDLOOP commands.
HANDSHAKING 3.6.
The vector file WAIT command enhances synchronization of the
Vector Output I/O module to the UUT. This command suspends
vector driving until the programmed edge (+ or -) transition has
occurred on the WAIT input pin (see Figure 3-1). Once the edge