Fluke 9100 Series User manual

9100 Series
9100A-017
Vector Output I/O Module
Service Manual
P/N 855531
August 1989
© 1989, John Fluke Mfg. Co., Inc. All rights reserved. Litho in U.S.A.

LIMITED WARRANTY
John Fluke Mfg. Co., Inc. (Fluke) warrants your 9100A-017 Vector Output I/O Module to be free from
defects in material and workmanship under normal use and service for one (1) year from the date of
shipment. Software and firmware products are provided “AS IS.” We do not warrant that software or
firmware products will be error free, operated without interruption or that all errors will be corrected. This
warranty extends to you if you are the original purchaser and does not apply to fuses, batteries, or any
product which, in our sole opinion, has been subject to misuse, alteration, or abnormal conditions of
operation or handling.
To obtain warranty service, contact a Fluke Service Center or send the product, with the description of the
difficulty, postage prepaid, to the nearest Fluke Service Center. Fluke assumes no risk for damage in
transit.
Fluke will, at our option, repair or replace the defective product free of charge. However, if we determine
that the failure was caused by misuse, alteration, or abnormal condition of operation or handling, you will
be billed for the repair. The repaired product will be returned to you, transportation prepaid.
THIS WARRANTY IS EXCLUSIVE AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTY OF MERCHANTABILITY OR
FITNESS FOR A PARTICULAR PURPOSE OR USE. FLUKE WILL NOT BE LIABLE FOR ANY SPECIAL,
INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES OR LOSS WHETHER IN CONTRACT, TORT,
OR OTHERWISE.

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Table of Contents
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SECTION TITLE PAGE
1 Introduction and Specifications ...........................1-1
INTRODUCTION1 ............................................1-1
SPECIFICATIONS ...........................................1-1
Theory of Operation .......................................2-1
VECTOR OUTPUT I/O MODULE OVERVIEW ........................2-1
INPUT SECTION THEORY OF OPERATION ........................2-5
Mainframe to Bus Interface Functional Block .........2-5
MAINFRAME ADDRESSING OF THE MODULE .............2-5
CUSTOM CHIP SELECTION ..........................2-6
Custom Chip Functional Block ........................2-8
Clock and Enable Mux Functional Block ...............2-9
CLOCK AND ENABLE MUX OPERATION .................2-9
General Control Latch Functional Block ..............2-11
CONTROL REGISTER ...............................2-12
DATA COMPARISON INPUTS .........................2-12
FUSE DETECTION .................................2-12
DATA COMPARISON AND GENERAL INTERRUPTS .........2-13
DATA COMPARE EQUAL OUTPUT PIN ..................2-13
OPERATION OF GENERAL CONTROL LATCH BLOCK .......2-13
Connector Code Functional Block .....................2-16
Input Protection Functional Block ...................2-16
OUTPUT SECTION THEORY OF OPERATION .......................2-16
Main PCA to Top PCA Interface Functional Block ......2-17
ADDRESSING .....................................2-18
Internal Oscillator Control Functional Block ........2-20
Output Control Functional Block .....................2-20
RAM Select Functional Block .........................2-21
CHIP COUNTER OPERATION .........................2-22
SSLOGIC (Start/Stop Logic) Functional Block .........2-22
SIGNAL POLARITY/CONTROL REGISTER ...............2-22
DRIVE CLOCK SELECTION ..........................2-23
HANDSHAKE SYNCHRONIZATION ......................2-24
VECTOR DRIVE COMPLETE LOGIC ....................2-25
Vector Address Functional Block .....................2-26
Vector Pattern RAM Functional Block .................2-26
Vector Control RAM Functional Block .................2-26
Loop Control Functional Block .......................2-27
Capture Clock Functional Block ......................2-28
Drive Status Functional Block .......................2-28
Output Protection Functional Block ..................2-29

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SECTION TITLE PAGE
3 Maintenance ...............................................3-1
INTRODUCTION .............................................3-1
CHANGING THE VECTOR OUTPUT I/O MODULE FUSE ...............3-1
CLEANING .................................................3-2
VECTOR OUTPUT I/O MODULE SELF TEST .......................3-2
DISASSEMBLY ..............................................3-2
TROUBLESHOOTING ..........................................3-3
General Information .................................3-3
4 List of Replaceable Parts .................................4-1
INTRODUCTION .............................................4-3
HOW TO OBTAIN PARTS ......................................4-3
ADDITIONAL INFORMATION ...................................4-4
5 Schematic Diagrams ........................................5-1

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List of Tables
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TABLE TITLE PAGE
1-1. Vector Output I/O Module Specifications ...................1-1
2-1. Custom Chip Pin Description ...............................2-11
2-2. Clock and Enable Mux Truth Table ..........................2-12
2-3. VHI and VLO for TTL and CMOS Logic Levels .................2-15
2-4. Dip-Clip and Calibration Module Configuration Codes .......2-17
2-5. Connector Code Examples ...................................2-18
2-6. Vector I/O Module Output Section Address Map ..............2-19
2-7. U25 Drive Register 2 Bit Description (Write @ $D0X21) .....2-20
2-8. U5 Register Bit Description (Write @ $D0X01) ..............2-21
2-9. U6 Register Bit Description (Write @ $D0X11) ..............2-23
2-10. U25 ID/Status Register Bit Description (Read @ $D0X01) ....2-29
4-1. 9100A-017 Vector I/O Final Assembly .......................4-5
4-2. A1 Main PCA ...............................................4-8
4-3. A2 Top PCA ................................................4-10
4-4. Module Revision Information ...............................2-12

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-v-
List of Figures
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FIGURE TITLE PAGE
2-1. Input Section Functional Block Diagram ....................2-3
2-2. Output Section Functional Block Diagram ...................2-4
2-3. Input Section Address Decoding Summary ....................2-7
2-4. Address Decoding Example ..................................2-8
2-5. Hot-Bit Decoding Examples .................................2-9
2-6. Bus Interface Timing Diagram ..............................2-10
2-7. I/O Module Control and Interrupt Registers ................2-14
2-8. Custom Chip Voltage Level Detection .......................2-15
4-1. 9100A-017 Final Assembly ..................................4-6
4-2. A1 Main PCA ...............................................4-9
4-3. A2 Top PCA ................................................4-11

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1-1
Section 1
Introduction and Specifications
INTRODUCTION
This manual presents service information for the 9100A-017 Vector Output
I/O Module. Included are a theory of operation, general maintenance
procedures, performance tests, troubleshooting information, a list of
replacement parts, and schematic diagrams.
SPECIFICATIONS
Table 1-1 contains the specifications for the Vector Output I/O Module.
NOTE
Output specifications for Table 1-1 were obtained using
the Y9100-102 Card Edge Interface Module into 10 LSTTL
loads. Results may vary depending on the impedance,
length, and shielding of the connector used. (Output
timing is measured at 50% of signal amplitude.)
Table 1-1. Vector Output I/O Module Specifications
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VECTOR OUTPUT I/O MODULE OUTPUT
(into 10 LSTTL loads with card edge connector attached):
Module Vector Size ......................... 8192 vectors, 40 channels wide.
Maximum Vector Pattern (4 Modules) ......... 8192 vectors, 160 channels wide.
Vector Looping ............................. Up to 65536 repetitions of
one vector set.
Output Logic Levels:
High ................................... 3.7V minimum (6.0 mA source).
Low .................................... 0.4V maximum (6.0 mA sink).
INT CLK (internal clock) ................... 1, 5, 10, or 20 MHz (±100
ppm).
DR CLK (external clock) .................... 25 MHz maximum. (This frequency
maximum may be exceeded in some
cases based upon application
and hardware interfacing.)
Clock to Vector Out (tdel):
INT CLK Out to Vector Out Delay ........ 37 ns typical, 45 ns maximum.
DR CLK In to Vector Out Delay .......... 50 ns typical, 58 ns maximum.
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1/Introduction and Specifications
1-2
Table 1-1. Vector Output I/O Module Specifications (cont.)
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WAIT (Handshake) Setup Time (twsu) ......... 42.5 ns maximum (35 ns typical)
from WAIT acknowledgement until
next clock cycle drives vector.
If the setup time is not met,
the next clock drives out the
vector. Minimum WAIT pulse
width is 10 ns.
Single Module Channel to Channel Skew* ..... 6 ns maximum (1 ns typical).
Module to Module Channel Skew* ............. 10 ns maximum (1 ns typical).
TRISTATE-:
Activation (txout) ..................... Output source/sink released 25
ns maximum (20 ns typical)
after TRISTATE- goes low.
Minimum TRISTATE- pulse width
is 10 ns.
Recovery (txsu) ........................ TRISTATE- must go high no later
than 5 ns after the rising edge
of the INT CLK or no later than
10 ns after the programmed edge
of DR CLK for the vector to be
output by that clock, otherwise
that vector is only driven
internally and the output is
held tri-stated, effectively
skipping that vector.
Output Series Termination .................. 33 Ohms
Capture Clock:**
INT CLK ................................ Capture Clock clocks 42.5 ns
±5 ns after the falling edge
of INT CLK.
DR CLK ................................. Capture Clock clocks 55 ns
±10 ns after non-clocking edge
of DR CLK (approximate 50% duty
cycle).
START, STOP, and ENABLE:
START, STOP Pulse Width .................... 10 ns minimum.
INT CLK
START Setup Time .................. 30 ns minimum.
STOP Setup Time ................... 30 ns minimum.
ENABLE Setup Time ................. 25 ns minimum.
ENABLE Hold Time .................. 20 ns minimum.
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* Skew measurement assumes equal loading. Differences in capacitance
may affect results.
** Capture clock may be adjusted in approximate 15 ns steps by using the
setoffset command (see the 9100 Series TL/1 Reference Manual).
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