Fujitsu PB-91469G-LS-256BGA User manual

Fujitsu Microelectronics Europe
User Guide
FMEMCU-UG-910022-13
MB91V460 FAMILY
PROBE CABLE
PB-91469G-LS-256BGA
USER GUIDE

PB-91469G-LS-256BGA V12
Revision History
UG-910022-13 - 2 - © Fujitsu Microelectronics Europe GmbH
Revision History
Date Issue
2006-Jun-06 V1.0, HLi, First Release
2007-Mar-02 V1.1 Recycling Note added
2007-Apr-11 V1.2 Hli, remove MCU before using probe info added
2008-Sep-16 V1.3 MSc, China-RoHS regulation added
This document contains 27 pages and the schematic in the middle.

PB-91469G-LS-256BGA V12
Warranty and Disclaimer
© Fujitsu Microelectronics Europe GmbH - 3 - UG-910022-13
Warranty and Disclaimer
To the maximum extent permitted by applicable law, Fujitsu Microelectronics Europe GmbH restricts
its warranties and its liability for the PB-91469G-LS-256BGA Probe and all its deliverables (e.g.
software include or header files, application examples, target boards, evaluation boards, engineering
samples of IC’s etc.), its performance and any consequential damages, on the use of the Product in
accordance with (i) the terms of the License Agreement and the Sale and Purchase Agreement under
which agreements the Product has been delivered, (ii) the technical descriptions and (iii) all
accompanying written materials. In addition, to the maximum extent permitted by applicable law,
Fujitsu Microelectronics Europe GmbH disclaims all warranties and liabilities for the performance of
the Product and any consequential damages in cases of unauthorised decompiling and/or reverse
engineering and/or disassembling. Note, the PB-91469G-LS-256BGA Probe and all its
deliverables are intended and must only be used in an evaluation laboratory environment.
1. Fujitsu Microelectronics Europe GmbH warrants that the Product will perform substantially in
accordance with the accompanying written materials for a period of 90 days form the date of
receipt by the customer. Concerning the hardware components of the Product, Fujitsu
Microelectronics Europe GmbH warrants that the Product will be free from defects in material
and workmanship under use and service as specified in the accompanying written materials
for a duration of 1 year from the date of receipt by the customer.
2. Should a Product turn out to be defect, Fujitsu Microelectronics Europe GmbH´s entire liability
and the customer’s exclusive remedy shall be, at Fujitsu Microelectronics Europe GmbH´s
sole discretion, either return of the purchase price and the license fee, or replacement of the
Product or parts thereof, if the Product is returned to Fujitsu Microelectronics Europe GmbH in
original packing and without further defects resulting from the customer’s use or the transport.
However, this warranty is excluded if the defect has resulted from an accident not attributable
to Fujitsu Microelectronics Europe GmbH, or abuse or misapplication attributable to the
customer or any other third party not relating to Fujitsu Microelectronics Europe GmbH.
3. To the maximum extent permitted by applicable law Fujitsu Microelectronics Europe GmbH
disclaims all other warranties, whether expressed or implied, in particular, but not limited to,
warranties of merchantability and fitness for a particular purpose for which the Product is not
designated.
4. To the maximum extent permitted by applicable law, Fujitsu Microelectronics Europe GmbH´s
and its supplier’s liability are restricted to intention and gross negligence.
NO LIABILITY FOR CONSEQUENTIAL DAMAGES
To the maximum extent permitted by applicable law, in no event shall Fujitsu
Microelectronics Europe GmbH and its suppliers be liable for any damages whatsoever
(including but without limitation, consequential and/or indirect damages for personal
injury, assets of substantial value, loss of profits, interruption of business operation,
loss of information, or any other monetary or pecuniary loss) arising from the use of
the Product.
Should one of the above stipulations be or become invalid and/or unenforceable, the remaining
stipulations shall stay in full effect

PB-91469G-LS-256BGA V12
Contents
UG-910022-13 - 4 - © Fujitsu Microelectronics Europe GmbH
0 Contents
REVISION HISTORY............................................................................................................ 2
WARRANTY AND DISCLAIMER ......................................................................................... 3
0 CONTENTS...................................................................................................................... 4
1 OVERVIEW...................................................................................................................... 5
1.1 Abstract...................................................................................................................5
2 DEFAULT JUMPER SETTING......................................................................................... 6
3 JUMPERS...................................................................................................................... 10
3.1 Power Supply Voltage (JP: 99, 100, 101, 102, 103) .............................................. 10
3.2 Level-shifter Direction Control: (JP1 – JP3, JP27 – JP32, JP59, JP61 –
JP65 and JP86 – JP88)......................................................................................... 10
3.3 Data Bus............................................................................................................... 12
3.4 Chip Select: JP66 – JP81...................................................................................... 14
3.5 DMA Signals: DACK, DEOP, DREQ, DEOTX and IOWRX, IORDX (JP89 –
JP98)..................................................................................................................... 16
3.6 External Bus Signals: (RDY, ASX, BGRNTX, BRQ, WEX, BAAX).........................18
3.7 Other Jumpers: MCLKE (JP14), RDY (JP17), VCC3C (JP24), WEX (JP45),
MONCLK (JP55), RDY or WEX (JP60), AVCC5 (JP82), AVSS (JP83/84), AVRH5
(JP85) ...................................................................................................................19
4 INSTALLATION............................................................................................................. 20
CSICE256Y2027FJ01 Top view...................................................................................21
CSICE256Y2027FJ01 Bottom view.............................................................................. 21
5 DIMENSIONS................................................................................................................. 22
PB-91469G-LS-256BGA ................................................................................................ 22
YQSOCKET256SE.........................................................................................................23
6 INFORMATION IN THE WWW....................................................................................... 24
7 CHINA-ROHS REGULATION........................................................................................ 25
8 RECYCLING.................................................................................................................. 27

PB-91469G-LS-256BGA V12
Chapter 1 Overview
© Fujitsu Microelectronics Europe GmbH - 5 - UG-910022-13
1 Overview
1.1 Abstract
The PB-91469G-LS-256BGA is a probe cable with Level shifters to support the MB91V460
external bus interface at 3.3 V levels.
This fix/flex cable can be connected between the BGA-660P ADAPTER ( MB2198-300) and
the starter kit (SK-91469G-256BGA), or the own target application.
Related documents such as MB91460 or MB91F46x “Hardware Manual” are available and
should always be use in addition to this manual.

PB-91469G-LS-256BGA V12
Chapter 2 Default Jumper Setting
UG-910022-13 - 6 - © Fujitsu Microelectronics Europe GmbH
2 Default Jumper Setting
The following jumper setting is the default setting. All jumpers are named directly on the
board, so it is easy to set the jumpers according to the features.
Jumper
Description / Function
Type
Default
Coordinat
e
JP1 Levelshifter1 / direction control 1DIR 1x3pol 1 - 2 N5/6
JP2 Levelshifter2 / direction control 1DIR 1x3pol 2 – 3 K5/6
JP3 Levelshifter3 / direction control 1DIR 1x3pol 2 - 3 D5/6
JP4
P08_7
RDY
/ use LV3 A/B > JP
1
6
is closed
Jumper 2pol open C/D9
JP5
P03_0
D0
/ use LV1 > JP34 must be open
Jumper 2pol closed N9
JP6
P03_1
D1 /
use LV1 > JP35 must be open
Jumper 2pol closed N9
JP7
P10_1
ASX
/ use LV3 A/B > JP19 is open
Jumper 2pol closed C9
JP8
P03_2
D2
/ use LV1 > JP38 must be open
Jumper 2pol closed N9
JP9
P03_3
D3
/ use LV1 > JP39 must be open
Jumper 2pol closed N9
JP10
P03_4
D4
/ use LV1 > JP41 must be open
Jumper 2pol closed M/N9
JP11
P03_5
D5
/ use LV1 > JP42 must be open
Jumper 2pol closed M9
JP12
P03_6
D6
/ use LV1 > JP43 must be open
Jumper 2pol closed M9
JP13
P03_7
D7
/ use LV1 > JP44 must be open
Jumper 2pol closed M9
JP14
P10_6
MCLKE
/ use LV3
Jumper 2pol closed C6
JP15
P02_0
D8
/ use LV1 > JP46 must be open
Jumper 2pol closed M9
JP16
P08_7
RDY
/ use LV3 B/A > JP4 is open
Jumper 2pol closed D6
JP17
P08_7
RDY
pull up 3V3
Jumper 2pol closed C9
JP18
P02_1
D9
/ use LV1 > JP48 must be open
Jumper 2pol closed L/M9
JP19
P10_1
ASX
/ use LV3 B/A > JP7 is closed
Jumper 2pol open C/D6
JP20
P02_2
D10
/ use LV1 > JP50 must be open
Jumper 2pol closed L9
JP21
P02_3
D11
/ use LV1 > JP52 must be open
Jumper 2pol closed L9
JP22
P02_4
D12
/ use LV1 > JP54 must be open
Jumper 2pol closed L9
JP23
P02_5
D13
/ use LV1 > JP56 must be open
Jumper 2pol closed L9
JP24 VCC3C > 10LF | 10nF > GND Jumper 2pol closed N5
JP25
P02_6
D14
/ use LV1 > JP57 must be open
Jumper 2pol closed K/L9
JP26
P02_7
D15
/ use LV1 > JP58 must be open
Jumper 2pol closed K9
JP27 Levelshifter1 / direction control 2DIR 1x3pol 1 – 2 M5/6
JP28 Levelshifter2 / direction control 2DIR 1x3pol 2 – 3 J5/6
JP29 Levelshifter3 / direction control 2DIR 1x3pol 1 – 2 C5/6
JP30 Levelshifter4 / direction control 2DIR 1x3pol 2 – 3 M5/6
JP31 Levelshifter5 / direction control 2DIR 1x3pol 2 – 3 J5/6
JP32 Levelshifter6 / direction control 2DIR 1x3pol 1 – 2 E5/6
JP33
P08_5
BGRNTX
/ use LV6 A
/B
>JP
47
is closed
Jumper 2pol open E6
JP34
P03_0
D0
/ use LV4 > JP5 is closed
Jumper 2pol open N6
JP35
P03_1
D1
/
use LV4 > JP6 is closed
Jumper 2pol open N6
JP36
P08_6
BRQ
/ use L
V6 A
/B
> JP49 must be open
Jumper 2pol closed E6
JP37
P10_3
WEX
/ use LV6 A/B > JP
51
is closed
Jumper 2pol open D/E6
JP38
P03_2
D2
/ use LV4 > JP8 is closed
Jumper 2pol open N6
JP39
P03_3
D3
/ use LV4 > JP9 is closed
Jumper 2pol open N6
JP40
P10_2
BAA
X
/ use LV6 A/B > JP53 is closed
Jumper 2pol open D6
JP41
P03_4
D4
/ use LV4 > JP10 is closed
Jumper 2pol open N6
JP42
P03_5
D5
/ use LV4 > JP11 is closed
Jumper 2pol open M6
JP43
P03_6
D6
/ use LV4 > JP12 is closed
Jumper 2pol open M6

PB-91469G-LS-256BGA V12
Chapter 2 Default Jumper Setting
© Fujitsu Microelectronics Europe GmbH - 7 - UG-910022-13
JP44 P03_7
D7
/ use LV4 > JP13 is closed Jumper 2pol open M6
JP45
WEX
or
V460_WEX
1x3pol 2 – 3 G9
JP46
P02_0
D8
/ use LV4 > JP14 is closed
Jumper 2pol open L6
JP47
P8_5
BGRNTX
/use LV6
B/A>JP33 must be open
Jumper 2pol closed E9
JP48
P02_1
D9
/ use LV4 > JP18 is closed
Jumper 2pol open L6
JP49
P08_6
BRQ
/ use LV6 B/A > JP36 is closed
Jumper 2pol open E9
JP50
P02_2
D10
/ use LV4 > JP20 is closed
Jumper 2pol open L6
JP51
P10_3
WEX
/ u
se LV6 B/A > JP37 must be open
Jumper 2pol closed E9
JP52
P02_3
D11
/ use LV4 > JP21 is closed
Jumper 2pol open L6
JP53
P10_2
BAAX
/ use LV6 B/A > JP40 must be open
Jumper 2pol closed D/E9
JP54
P02_4
D12
/ use LV4 > JP22 is closed
Jumper 2pol open K6
JP55
MONCLK
Jumper 2pol closed J6
JP56
P02_5
D13
/ use LV4 > JP23 is closed
Jumper 2pol open K6
JP57
P02_6
D14
/ use LV4 > JP25 is closed
Jumper 2pol open K6
JP58
P02_7
D15
/ use LV1 > JP26 is closed
Jumper 2pol open J/K6
JP59 Levelshifter4 / direction control 2DIR 1x3pol 2 – 3 K/L5/6
JP60
RDX
or
WEX
1x3pol 1 – 2 H9
JP61 Levelshifter5 / direction control 2DIR 1x3pol 2 – 3 H5/6
JP62 Levelshifter6 / direction control 2DIR 1x3pol 2 – 3 D5/6
JP63 Levelshifter7 / direction control 1DIR 2x3pol 2 – 5 H5/6
JP64 Levelshifter8 / direction control 1DIR 1x3pol 2 – 3 C5/6
JP65 Levelshifter9 / direction control 1DIR 1x3pol 1 – 2 G5/6
JP66
P09_0
CSX0
/ use LV8 B/A > JP74 must be open
Jumper 2pol closed C9
JP67
P09_1
CSX1
/ use LV8 B/A > JP75
must be open
Jumper 2pol closed C9
JP68
P09_2
CSX2 /
use LV8 B/A > JP76 must be open
Jumper 2pol closed B9
JP69
P09_3
CSX3
/ use LV8 B/A > JP77 must be open
Jumper 2pol closed B9
JP70
P09_4
CSX4
/ use LV8 B/A > JP78 must be open
Jumper 2pol closed B9
JP71
P09_5
CSX5
/ use LV8 B/A > JP79 must be open
Jumper 2pol closed B9
JP72
P09_6
CSX6
/ use LV8 B/A > JP80 must be open
Jumper 2pol closed A/B9
JP73
P09_7
CSX7
/ use LV8 B/A > JP81 must be open
Jumper 2pol closed A9
JP74
P09_0
CSX0
/ use LV8 A/B
> JP66 is closed
Jumper 2pol open C6
JP75
P09_1
CSX1
/ use LV8 A/B > JP67 is closed
Jumper 2pol open B6
JP76
P09_2
CSX2 /
use LV8 A/B > JP68 is closed
Jumper 2pol open B6
JP77
P09_3
CSX3
/ use LV8 A/B > JP69 is closed
Jumper 2pol open B6
JP78
P09_
4
CSX4
/ use LV8 A/B > JP70 is closed
Jumper 2pol open B6
JP79
P09_5
CSX5
/ use LV8 A/B > JP71 is closed
Jumper 2pol open B6
JP80
P09_6
CSX6
/ use LV8 A/B > JP72 is closed
Jumper 2pol open A/B6
JP81
P09_7
CSX7
/ use LV8 A/B > JP73 is closed
Jumper 2pol open A6
JP82
AVCC5
Jumper 2pol closed H/J6
JP83
AVSS
Jumper 2pol closed K9
JP84
AVSS
Jumper 2pol closed K9
JP85
AVRH5
Jumper 2pol closed J/K9
JP86 Levelshifter7 / direction control 2DIR 2x3pol 2 – 5 G/H5/6
JP87 Levelshifter8 / direction control 2DIR 1x3pol 1 – 2 A5/6
JP88 Levelshifter9 / direction control 2DIR 1x3pol 2 – 3 E5/6
JP89
DACKX0
2x3pol 1–2, 4-5 E/F5/6
JP90
DEOP0
2x3pol 1–2, 4-5
E/F9
JP91
DREQ0
2x3pol 2-3, 5-6
G5/6
JP92
DEOTX0
2x3pol 2-3, 5-6
F/G5/6
JP93
DACKX1
2x3pol 1–2, 4-5
F/G9
JP94
DEOP1
2x3pol 1–2, 4-5
F9

PB-91469G-LS-256BGA V12
Chapter 2 Default Jumper Setting
UG-910022-13 - 8 - © Fujitsu Microelectronics Europe GmbH
JP95
DREQ1
2x3pol 2-3, 5-6
F5/6
JP96
DEOTX1
2x3pol 2-3, 5-6
F9
JP97
IOWRX
2x3pol 1–2, 4-5
D9
JP98
IORDX
2x3pol 1–2, 4-5
C/D9
JP99 5V supply jumper 1x3+1 1 – 2
B10
JP100 VDD35 jumper 1x3pol 1 – 2
C/D10
JP101 3V supply jumper 1x3+1 1 – 2
C/D10
JP102 5V_T > UVCC5 Jumper 2pol closed
A9
JP103 3V3 > UVCC3 Jumper 2pol closed
C9

PB-91469G-LS-256BGA V12
© Fujitsu Microelectronics Europe GmbH - 9 - UG-910022-13
A B C D E F G H J K L M N
1
1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
9
9
10 10
11 11
12 12
13 13
14 14
15 15
16 16
17 17
18 18
19 19
20 20
21 21
22 22
23 23
24 24
25 25
26 26
27 27
28 28
29 29
A B C D E F G H J K L M N

PB-91469G-LS-256BGA V12
Chapter 3 Jumpers
UG-910022-13 - 10 - © Fujitsu Microelectronics Europe GmbH
3 Jumpers
This chapter describes all jumpers that can be modified on the probe. The default setting is
shown with a grey shaded area. All jumpers are named directly on the board, so it is very
easy to set the jumpers according to the features.
3.1 Power Supply Voltage (JP: 99, 100, 101, 102, 103)
3V3 and 5V are the supply voltages for the Level shifters. The Jumpers JP99 and JP101 in
conjunction with S1 and S2, allow to use an externally power supply for the Level shifters. In
that case, take care of the input-voltage. Neither a voltage regulation nor an over-voltage-
protection does exist for an external power-supply. The default setting is supplying the level
shifters with UVCC3 and UVCC5 directly.
Jumper Setting Description
1 - 2 The emulator site of the level shifters (B-site, 5V) is
supplied by 5V_T.
JP99 (5V
supply) 2 - 3 The emulator site of the level shifters (B-site, 5V) is
supplied by external power-supply from S1.
1 - 2 The target site of the level shifters (A-site, 3V3) is
supplied by VDD35.
JP101 (3V3
supply) 2 - 3 The target site of the level shifters (A-site, 3V3) is
supplied by external power-supply from S2.
ON (closed) 5V_T (target) is connected to UVCC5 of the
emulator MB2198-300. (see also JP100)
JP102 (UVCC5
> 5V_T) OFF (open) 5V_T (target) is not connected to UVCC5 of the
emulator MB2198-300. (see also JP100)
ON (closed) 3V3 (target) is connected to UVCC3 of MB2198-
300. (see also JP100)
JP103 (UVCC3
> 3V3) OFF (open) 3V3 (target) is not connected to UVCC3 of
MB2198-300. (see also JP100)
1 – 2 VDD35 is connected to 3V3
2 – 3 VDD35 is connected to 5V_T
JP100
Open
3.2 Level-shifter Direction Control: (JP1 – JP3, JP27 – JP32, JP59,
JP61 – JP65 and JP86 – JP88)
Jumper Setting Description
1 – 2 1DIR connected to DIR -> the direction of LV1/1
1A<>1B is selectable
JP1 (D0-D7)
direction control
LV1 /1DIR 2 – 3 1DIR connected to GND -> LV1/1 direction B/A
(MB2198-300 to target)

PB-91469G-LS-256BGA V12
Chapter 3 Jumpers
© Fujitsu Microelectronics Europe GmbH - 11 - UG-910022-13
1 – 2 1DIR connected to 5V -> LV2/1 direction A/B
(target to MB2198-300)
JP2 (A0-A7)
direction control
LV2 1DIR 2 – 3 1DIR connected to GND -> LV2/1 direction B/A
(MB2198-300 to target)
1 – 2 1DIR connected to 5V -> LV3/1 direction A/B
(target to MB2198-300)
JP3 (RDY, ASX,
RDX, WRX0-3)
direction control
LV3 1DIR 2 – 3 1DIR connected to GND -> LV3/1 direction B/A
(MB2198-300 to target)
1 – 2 2DIR connected to DIR -> the direction of LV1/2
1A<>1B is selectable
JP27 (D8-D15)
direction control
LV1 2DIR 2 – 3 2DIR connected to GND -> LV1/2 direction B/A
(MB2198-300 to target)
1 – 2 2DIR connected to 5V -> LV2/2 direction A/B
(target to MB2198-300)
JP28 (A8-A15)
direction control
LV2 2DIR 2 – 3 2DIR connected to GND -> LV2/2 direction B/A
(MB2198-300 to target)
1 – 2 2DIR connected to 5V -> LV3/2 direction A/B
(target to MB2198-300)
JP29 (RDY,
ASX ) direction
control
LV3 2DIR 2 - 3 2DIR connected to GND -> LV3/2 direction B/A
(MB2198-300 to target)
1 – 2 1DIR connected to DIR -> the direction of LV4/1
1A<>1B is selectable
JP30 (D0-D7)
direction control
LV4 1DIR 2 - 3 1DIR connected to 5V -> LV4/1 direction A/B
(MB2198-300 to target)
1 – 2 1DIR connected to 5V > LV5/1 direction A/B >
(target to MB2198-300)
JP31 (A16-A23)
direction control
LV5 1DIR 2 - 3 1DIR connected to GND -> LV5/1 direction B/A
(MB2198-300 to target)
1 – 2 1DIR connected to 5V > LV6/1 direction A/B >
(target to MB2198-300)
JP32 (external
bus control
signals)
direction control
LV6 1DIR
2 - 3 1DIR connected to GND -> LV6/1 direction B/A
(MB2198-300 to target)
1 – 2 2DIR connected to DIR -> the direction of LV4/2
1A<>1B is selectable
JP59 (D8-D15)
direction control
LV4 2DIR 2 - 3 2DIR connected to 5V -> LV4/2 direction A/B
(MB2198-300 to target)
1 – 2 2DIR connected to 5V > LV5/2 direction A/B >
(target to MB2198-300)
JP61 (A24-A27,
MONCLK)
direction control
LV5 2DIR
2 - 3 2DIR connected to GND -> LV5/2 direction B/A
(MB2198-300 to target)

PB-91469G-LS-256BGA V12
Chapter 3 Jumpers
UG-910022-13 - 12 - © Fujitsu Microelectronics Europe GmbH
1 – 2 2DIR connected to 5V > LV6/2 direction A/B >
(target to MB2198-300)
JP62 (BGRNTX,
BRQ, WEX,
BAAX)
direction control
LV6 2DIR
2 - 3 2DIR connected to GND -> LV6/2 direction B/A
(MB2198-300 to target)
1 – 4 1DIR connected to 5V > LV7/1 direction A/B >
(target to MB2198-300)
2 – 5 1DIR connected to DIR -> the direction of LV7/1
1A<>1B is selectable
JP63 (D16-D23)
direction control
LV7 1DIR
3 – 6 1DIR connected to GND -> LV7/1 direction B/A
(MB2198-300 to target)
1 – 2 1DIR connected to 5V > LV8/1 direction A/B >
(target to MB2198-300)
JP64 (CSX0-C7)
direction control
LV8 1DIR
2 - 3 1DIR connected to GND -> LV8/1 direction B/A
(MB2198-300 to target)
1 – 2 1DIR connected to 5V > LV9/1 direction A/B >
(target to MB2198-300)
JP65 (DMA
signals)
direction control
LV9 1DIR 2 - 3 1DIR connected to GND -> LV9/1 direction B/A
(MB2198-300 to target)
1 – 4 2DIR connected to 5V > LV7/2 direction A/B >
(target to MB2198-300)
2 – 5 2DIR connected to DIR -> the direction of LV7/2
1A<>1B is selectable
JP86 (D24-D31)
direction control
LV7 2DIR
3 – 6 2DIR connected to GND -> LV7/2 direction B/A
(MB2198-300 to target)
1 – 2 2DIR connected to 5V > LV8/2 direction A/B >
(target to MB2198-300)
JP87 (CSX0-7)
direction control
LV8 2DIR 2 - 3 2DIR connected to GND -> LV8/2 direction B/A
(MB2198-300 to target)
1 – 2 2DIR connected to 5V > LV9/2 direction A/B >
(target to MB2198-300)
JP88 (DMA
signals)
direction control
LV9 2DIR 2 - 3 2DIR connected to GND -> LV9/2 direction B/A
(MB2198-300 to target)
3.3 Data Bus
Jumper Setting Description
ON (closed)
JP5 (D0) OFF (open)
P03_0 D0 > JP34 must be open
Direction control via DIR (D0-D7 in all)
ON (closed)
JP6 (D1) OFF (open)
P03_1 D1 > JP35 must be open
Direction control via DIR (D0-D7 in all)
ON (closed)
JP8 (D2) OFF (open)
P03_2 D2 > JP38 must be open
Direction control via DIR (D0-D7 in all)

PB-91469G-LS-256BGA V12
Chapter 3 Jumpers
© Fujitsu Microelectronics Europe GmbH - 13 - UG-910022-13
ON (closed)
JP09 (D3) OFF (open)
P03_3 D3 > JP39 must be open
Direction control via DIR (D0-D7 in all)
ON (closed)
JP10 (D4) OFF (open)
P03_4 D4 > JP41 must be open
Direction control via DIR (D0-D7 in all)
ON (closed)
JP11 (D5) OFF (open)
P03_5 D5 > JP42 must be open
Direction control via DIR (D0-D7 in all)
ON (closed)
JP12 (D6) OFF (open)
P03_6 D6 > JP43 must be open
Direction control via DIR (D0-D7 in all)
ON (closed)
JP13 (D7) OFF (open)
P03_7 D7 > JP44 must be open
Direction control via DIR (D0-D7 in all)
ON (closed)
JP15 (D8) OFF (open)
P02_0 D8 > JP46 must be open
Direction control via DIR (D0-D15 in all)
ON (closed)
JP18 (D9) OFF (open)
P02_1 D9 > JP48 must be open
Direction control via DIR (D8-D15 in all)
ON (closed)
JP20 (D10) OFF (open)
P02_2 D10 > JP50 must be open
Direction control via DIR (D8-D15 in all)
ON (closed)
JP21 (D11) OFF (open)
P02_3 D11 > JP52 must be open
Direction control via DIR (D8-D15 in all)
ON (closed)
JP22 (D12) OFF (open)
P02_4 D12 > JP54 must be open
Direction control via DIR (D8-D15 in all)
ON (closed)
JP23 (D13) OFF (open)
P02_5 D13 > JP56 must be open
Direction control via DIR (D8-D15 in all)
ON (closed)
JP25 (D14) OFF (open)
P02_6 D14 > JP57 must be open
Direction control via DIR (D8-D15 in all)
ON (closed)
JP26 (D15) OFF (open)
P02_7 D15 > JP58 must be open
Direction control via DIR (D8-D15 in all)
ON (closed)
JP34 (D0) OFF (open)
P03_0 D0 > in case of close JP34, JP5 must be
open. > Direction control via DIR (D0-D7 in all)
ON (closed)
JP35 (D1) OFF (open)
P03_1 D1 > in case of close JP35, JP6 must be
open. > Direction control via DIR (D0-D7 in all)
ON (closed)
JP38 (D2) OFF (open)
P03_2 D2 > in case of close JP38, JP8 must be
open. > Direction control via DIR (D0-D7 in all)
ON (closed)
JP39 (D3) OFF (open)
P03_3 D3 > in case of close JP39, JP9 must be
open. > Direction control via DIR (D0-D7 in all)

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ON (closed)
JP41 (D4) OFF (open)
P03_4 D4 > in case of close JP41, JP10 must be
open. > Direction control via DIR (D0-D7 in all)
ON (closed)
JP42 (D5) OFF (open)
P03_5 D5 > in case of close JP42, JP11 must be
open. > Direction control via DIR (D0-D7 in all)
ON (closed)
JP43 (D6) OFF (open)
P03_6 D6 > in case of close JP43, JP12 must be
open. > Direction control via DIR (D0-D7 in all)
ON (closed)
JP44 (D7) OFF (open)
P03_7 D7 > in case of close JP44, JP13 must be
open. > Direction control via DIR (D0-D7 in all)
ON (closed)
JP46 (D8) OFF (open)
P02_0 D8 > in case of close JP46, JP15 must be
open. > Direction control via DIR (D7-D15 in all)
ON (closed)
JP48 (D9) OFF (open)
P02_1 D9 > in case of close JP48, JP18 must be
open. > Direction control via DIR (D7-D15 in all)
ON (closed)
JP50 (D10) OFF (open)
P02_2 D10 > in case of close JP50, JP20 must be
open. > Direction control via DIR (D7-D15 in all)
ON (closed)
JP52 (D11) OFF (open)
P02_3 D11 > in case of close JP52, JP21 must be
open. > Direction control via DIR (D7-D15 in all)
ON (closed)
JP54 (D12) OFF (open)
P02_4 D12 > in case of close JP54, JP22 must be
open. > Direction control via DIR (D7-D15 in all)
ON (closed)
JP56 (D13) OFF (open)
P02_5 D13 > in case of close JP56, JP23 must be
open. > Direction control via DIR (D7-D15 in all)
ON (closed)
JP57 (D14) OFF (open)
P02_6 D14 > in case of close JP57, JP25 must be
open. > Direction control via DIR (D7-D15 in all)
ON (closed)
JP58 (D15) OFF (open)
P02_7 D15 > in case of close JP58, JP26 must be
open. > Direction control via DIR (D7-D15 in all)
3.4 Chip Select: JP66 – JP81
Jumper Setting Description
ON (closed)
JP66 (CSX0) OFF (open)
P09_0 CSX0 / > in case of close JP66, JP74 must
be open. > Direction control via JP64 (CSX0 –
CSX7 in all)
ON (closed)
JP67 (CSX1) OFF (open)
P09_1 CSX1 / > in case of close JP67, JP75 must
be open. > Direction control via JP64 (CSX0 –
CSX7 in all)
ON (closed)
JP68 (CSX2) OFF (open)
P09_2 CSX2 / > in case of close JP68, JP76 must
be open. > Direction control via JP64 (CSX0 –
CSX7 in all)

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ON (closed)
JP69 (CSX3) OFF (open)
P09_3 CSX3 / > in case of close JP69, JP77 must
be open. > Direction control via JP64 (CSX0 –
CSX7 in all)
ON (closed)
JP70 (CSX4) OFF (open)
P09_4 CSX4 / > in case of close JP70, JP78 must
be open. > Direction control via JP64 (CSX0 –
CSX7 in all)
ON (closed)
JP71 (CSX5) OFF (open)
P09_5 CSX5 / > in case of close JP71, JP79 must
be open. > Direction control via JP64 (CSX0 –
CSX7 in all)
ON (closed)
JP72 (CSX6) OFF (open)
P09_6 CSX6 / > in case of close JP72, JP80 must
be open. > Direction control via JP64 (CSX0 –
CSX7 in all)
ON (closed)
JP73 (CSX7) OFF (open)
P09_7 CSX7 / > in case of close JP73, JP81 must
be open. > Direction control via JP64 (CSX0 –
CSX7 in all)
ON (closed)
JP74 (CSX0) OFF (open)
P09_0 CSX0 / > in case of close JP74, JP66 must
be open. > Direction control via JP87 (CSX0 –
CSX7 in all)
ON (closed)
JP75 (CSX1) OFF (open)
P09_1 CSX1 / > in case of close JP75, JP67 must
be open. > Direction control via JP87 (CSX0 –
CSX7 in all)
ON (closed)
JP76 (CSX2) OFF (open)
P09_2 CSX2 / > in case of close JP76, JP68 must
be open. > Direction control via JP87 (CSX0 –
CSX7 in all)
ON (closed)
JP77 (CSX3) OFF (open)
P09_3 CSX3 / > in case of close JP77, JP69 must
be open. > Direction control via JP87 (CSX0 –
CSX7 in all)
ON (closed)
JP78 (CSX4) OFF (open)
P09_4 CSX4 / > in case of close JP78, JP70 must
be open. > Direction control via JP87 (CSX0 –
CSX7 in all)
ON (closed)
JP79 (CSX5) OFF (open)
P09_5 CSX5 / > in case of close JP79, JP71 must
be open. > Direction control via JP87 (CSX0 –
CSX7 in all)
ON (closed)
JP80 (CSX6) OFF (open)
P09_6 CSX6 / > in case of close JP80, JP72 must
be open. > Direction control via JP87 (CSX0 –
CSX7 in all)
ON (closed)
JP81 (CSX7) OFF (open)
P09_7 CSX7 / > in case of close JP81, JP73 must
be open. > Direction control via JP87 (CSX0 –
CSX7 in all)

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3.5 DMA Signals: DACK, DEOP, DREQ, DEOTX and IOWRX, IORDX
(JP89 – JP98)
Jumper Setting Description
1 – 2 1DACKX0 > V460_DACKX0
2 – 3 V460_DACKX0 > 2DACKX0
4 – 5 4DACKX0 > MCU_D1
JP89
(DACKX0)
DMA
Acknowledge 5 – 6 MCU_D1 > 5DACKX0
1 – 2 1DEOP0 > V460_DEOP0
2 – 3 V460_DEOP0 > 2DEOP0
4 – 5 4DEOP0 > MCU_E1
JP90 (DEOP0
)
DMA
termination
output pin
5 – 6 MCU_E1 > 5DEOP0
1 – 2 1DREQ0 > V460_DREQ0
2 – 3 V460_DREQ0 > 2DREQ0
4 – 5 4DREQ0 > MCU_C1
JP91 (DREQ0)
DMA Request
5 – 6 MCU_C1 > 5DREQ0
1 – 2 1DEOTX0 > V460_DEOTX0
2 – 3 V460_DEOTX0 > 2DEOTX0
4 – 5 4DEOTX0 > MCU_D2
JP92
(DEOTX0)
DMA stop
request
5 – 6 MCU_D2 > 5DEOTX0
1 – 2 1DACKX1 > V460_DACKX1
2 – 3 V460_DACKX1 > 2DACKX1
4 – 5 4DACKX1 > MCU_E3
JP93
(DACKX1)
DMA
Acknowledge 5 – 6 MCU_E3 > 5DACKX1
1 – 2 1DEOP1 > V460_DEOP1
2 – 3 V460_DEOP1 > 2DEOP1
4 – 5 4DEOP1 > MCU_F2
JP94 (DEOP1)
DMA
termination
output pin
5 – 6 MCU_F2 > 5DEOP1
1 – 2 1DREQ1 > V460_DREQ1
2 – 3 V460_DREQ1 > 2DREQ1
4 – 5 4DREQ1 > MCU_E2
JP95 (DREQ1)
DMA Request
5 – 6 MCU_E2 > 5DREQ1

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1 – 2 1DEOTX1 > V460_DEOTX1
2 – 3 V460_DEOTX1 > 2DEOTX1
4 – 5 4DEOTX1 > MCU_F1
JP96
(DEOTX1)
DMA stop
request
5 – 6 MCU_F1 > 5DEOTX1
1 – 2 1IOWRX > V460_IOWRX
2 – 3 V460_IOWRX > 2IOWRX
4 – 5 4IOWRX > MCU_G1
JP97 (IOWRX)
DMA control
signal
5 – 6 MCU_G1 > 5IOWRX
1 – 2 1IORDX > V460_IORDX
2 – 3 V460_IORDX > 2IORDX
4 – 5 4IORDX > MCU_F3
JP98 (IORDX)
DMA control
signal
5 – 6 MCU_F3 > 5IORDX

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3.6 External Bus Signals: (RDY, ASX, BGRNTX, BRQ, WEX, BAAX)
Jumper Setting Description
ON (closed)
JP4 (RDY) OFF (open)
RDY P08_7: Input pin for external wait. > in case of
close JP4, JP16 must be open. > Direction control
via JP3
ON (closed)
JP16 (RDY) OFF (open)
RDY P08_7: Input pin for external wait. > JP4 must
be open. > Direction control via JP29
ON (closed)
JP7 (ASX) OFF (open)
ASX P10_1: Output pin for external bus address
strobe. > JP19 must be open. > Direction control
via JP3
ON (closed)
JP19 (ASX) OFF (open)
ASX P10_1: Output pin for external bus address
strobe. > in case of close JP19, JP7 must be open.
> Direction control via JP29
ON (closed)
JP33
(BGRNTX) OFF (open)
BGRNTX P08_5: Output pin for external bus
granted. > in case of close JP33, JP47 must be
open. > Direction control via JP32
ON (closed)
JP47
(BGRNTX) OFF (open)
BGRNTX P08_5: Output pin for external bus
granted. > JP33 must be open > Direction control
via JP62
ON (closed)
JP36 (BRQ) OFF (open)
BRQ P08_6: Input pin for external bus request. >
JP49 must be open > Direction control via JP32
ON (closed)
JP49 (BRQ) OFF (open)
BRQ P08_6: Input pin for external bus request. > in
case of close JP49, JP36 must be open. >
Direction control via JP62
ON (closed)
JP37 (WEX) OFF (open)
WEX P10_3: Output pin for external bus write
strobe. > in case of close JP37, JP51 must be open
> Direction control via JP32
ON (closed)
JP51 (WEX) OFF (open)
WEX P10_3: Output pin for external bus write
strobe. > JP51 must be open > Direction control via
JP62
ON (closed)
JP40 (BAAX) OFF (open)
BAAX P10_2: Output pin for external bus burst
access. > in case of close JP40, JP53 must be
open > Direction control via JP32
ON (closed)
JP53 (BAAX) OFF (open)
BAAX P10_2: Output pin for external bus burst
access. > JP40 must be open > Direction control
via JP62

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3.7 Other Jumpers: MCLKE (JP14), RDY (JP17), VCC3C (JP24), WEX (JP45),
MONCLK (JP55), RDY or WEX (JP60), AVCC5 (JP82), AVSS (JP83/84),
AVRH5 (JP85)
Jumper Setting Description
ON (closed)
JP14 (MCLKE) OFF (open)
MCLKE P10_6:
Output pin for external bus memory clock enable.
ON (closed)
JP17 (RDY) OFF (open)
RDY P08_7: Input pin for external wait.
Pull up 3V3
ON (closed)
JP24 (VCC3C) OFF (open)
VCC3C > 10µF | 10nF > GND
1-2 WEX P10_3 use for DIR
JP45 (WEX) 2-3 V460_WEX use for DIR
ON (closed)
JP55
(MONCLK) OFF (open)
MONCLK: Clock Monitor Output
1-2 RDX is for SRAM and Flash
JP60 (RDX or
WEX) 2-3 WEX is for SRAM and SDRAM
ON (closed) Analog supply voltage is connected to the target
JP82 (AVCC5) OFF (open) Analog supply voltage is disconnected from the
target
ON (closed) Analog input voltage is connected to the target
JP83, JP84
(AVSS) OFF (open) Analog input voltage is disconnected from the
target
ON (closed) Analog reference voltage is connected to the target
JP85 (AVRH5) OFF (open) Analog reference voltage is disconnected from the
target

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Chapter 4 Installation
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4 Installation
- Remove carefully the board from the shipping carton.
- Check first if there are any damages.
- Check and compare the jumper setting with the default jumper settings (page 9)
- Open the box CSICE256Y2027FJ01 and take out the four screws. Put the screws with the
slot on top into bottom of the CSICE256Y2027FJ01 > see following figure part “h”
- Note: The connection between CSICE256Y2027FJ01 and the first YQSOCKET256SE
is only once pluggable, since otherwise the pins can break off. Decide how many
YQSOCKET256SE are needed for the required high of the buildup.
- Press/connect carefully and smooth the CSICE256Y2027FJ01 into the
YQSOCKET256SE.
- Remove MCU out of the socket (CS-PACK) before using the probe cable
f: PB-91469G-LS-256BGA g: YQSOCKET256SE
h: CSICE256Y2027FJ01 i: CSPACK256
k: Target board
(e.g. SK-91469G-256BGA)