General Standards Corporation PCIe-24DSI32 User manual

PCIe-24DSI32
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Rev: 042514
PCIe-24DSI32
24-BIT, 32-CHANNEL DELTA-SIGMA, 200 KSPS
ANALOG INPUT PCIe BOARD
________________________
REFERENCE MANUAL

PCIe-24DSI32
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i
TABLE OF CONTENTS
SECTION
TITLE ___ 
PAGE
1.0
INTRODUCTION
1-1
1.1
General Description
1-1
1.2
Functional Overview
1-2
2.0
INSTALLATION AND MAINTENANCE
2-1
2.1
Board Configuration
2-1
2.2
Installation
2-1
2.2.1
Physical Installation
2-1
2.2.2
Input/Output Cable Connections
2-1
2.3
Analog Input Configuration
2-3
2.3.1
Differential Inputs
2-3
2.3.2
Single-ended Input Sources
2-4
2.4
Multiboard Clocking and Synchronization
2-4
2.4.1
Interboard Connections
2-4
2.4.2
Multiboard Synchronization
2-5
2.5
Maintenance
2-5
2.6
Reference Verification and Adjustment
2-5
2.6.1
Equipment Required
2-6
2.6.2
Adjustment Procedure
2-6
3.0
CONTROL SOFTWARE
3-1
3.1
Introduction
3-1
3.2
Board Control Register
3-2
3.3
Configuration and Initialization
3-3
3.3.1
Board Configuration
3-3
3.3.2
Initialization
3-3
3.4
Analog Input Configuration
3-4
3.4.1
Selftest Modes
3-4
3.4.2
Input Range Selection
3-4
3.4.3
Settling Delays and the Channels Ready Flag
3-5
3.5
Input Data Buffer
3-5
3.5.1
General Characteristics
3-5
3.5.2
Data Organization
3-5
3.5.2.1
Channel Tags
3-5
3.5.2.2
Input Data Format
3-6
3.5.3
Buffer Control Register
3-6
3.5.3.1
Status Flag and Threshold
3-7
3.5.3.2
Buffer Clearing and Disabling
3-7

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TABLE OF CONTENTS (Continued)
SECTION
TITLE 
PAGE
3.5
Input Data Buffer (cont)
---
3.5.4
Buffer Size Register
3-7
3.5.5
Buffer Underflow and Overflow Flags
3-7
3.6
Input Sampling Control
3-8
3.6.1
Sample Rate Control
3-8
3.6.1.1
Rate Clock Organization
3-8
3.6.1.2
Rate Generator Assignment
3-8
3.6.1.3
Sample Clock Generation
3-10
3.6.2
Rate Generator Control
3-11
3.6.2.1
PLL Rate Generator
3-11
3.6.2.2
Legacy Rate Generator
3-14
3.6.3
Direct External Clocking
3-14
3.6.4
Harmonically Locked Channels
3-15
3.6.5
Channel Synchronization
3-15
3.6.6
Multiboard Operation
3-15
3.6.6.1
External Sample Clock
3-15
3.6.6.2
External Sync
3-16
3.7
Autocalibration
3-17
3.8
Interrupt Control
3-17
3.8.1
Local Interrupt Request
3-17
3.8.2
Enabling the PCI Interrupt
3-18
3.9
DMA Operation
3-16
3.9.1
Block Mode
3-16
3.9.2
Demand Mode
3-16
3.10
Scan Synchronization
3-20
3.11
Board Configuration Register
3-22
3.12
External Independent Burst Triggering
3-22
3.13
Settling TIme Considerations
3-23
4.0
PRINCIPLES OF OPERATION
4-1
4.1
General Description
4-1
4.2
Analog Inputs
4-2
4.3
Autocalibration
4-2
4.4
Sampling Clocks
4-2
4.5
Power Control
4-3
Appendix A
Local Register Quick Reference
A-1

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LIST OF ILLUSTRATIONS
FIGURE
TITLE 
PAGE
1.1
Physical Configuration
1-1
1.2
Functional Organization
1-2
2.2.2
System I/O Connections
2-2
2.3.1
Input Configurations
2-3
2.4.1
Multiboard Clock/Sync Connections
2-4
2.6.2
Reference Adjustment Access
2-6
3.6.1.1
ADC Clock and Sync Organization, 32 Channels
3-9
4.1
Functional Block Diagram
4-1
LIST OF TABLES
TABLE
TITLE __ 
PAGE
2.2.2
System Connector Pin Assignments
2-2
2.6.1
Reference Adjustment Equipment
2-6
3.1
Control and Data Registers
3-1
3.2
Board Control Register
3-2
3.3.1
Configuration Operations
3-3
3.4
Analog Input Function Selection
3-4
3.4.3
Analog Input Range Selection
3-4
3.5.2
Input Data Buffer Organization
3-5
3.5.2.2
Analog Input Data Coding; 16-Bit Data Field
3-6
3.5.3
Buffer Control Register
3-6
3.6.1.1
Channel Groups
3-9
3.6.1.2-1
Rate Assignments Register
3-10
3.6.1.2-2
Rate Generator Assignment Codes
3-10
3.6.1.3
Rate Divisor Register
3-10
3.6.2.1-1
PLL Nref Register
3-12
3.6.2.1-2
PLL Nvco Register
3-12
3.6.2.1-3
Summary of PLL Sample Rate Control Parameters
3-12
3.6.2.2-1
Legacy Rate Control Register
3-14
3.6.3
Direct External Clocking
3-14
3.8.1
Interrupt Event Selection
3-18
3.9.1
Typical DMA Register Configuration; Block Mode
3-16
3.9.2
Typical DMA Register Configuration; Demand Mode
3-16
3.10.1
Channel Order
3-20
3.11.1
Board Configuration Register
3-22

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1-1
SECTION 1.0
INTRODUCTION
1.1 General Description
The PCIe-24DSI32 board provides 24-bit analog input capability for the PCIe bus at sample
rates up to 200 KSPS per channel. In addition to providing 32 analog input channels, this
product supports multiboard clocking and synchronization. The board is functionally and
mechanically compatible with the PCI Express Specification revision 1.0a. Power
requirements consist of +3.3 VDC in accordance with the PCI specification, and operation
over the specified temperature range is achieved with minimal (200 LFPM) air cooling.
Specific details pertaining to physical characteristics and performance are contained in the
PCIe-24DSI32 product specification.
The board is designed for minimum off-line maintenance, and includes internal monitoring
features that eliminate the need for disconnecting or removing the module from the system
for calibration. All system input and output connections are made at the panel bracket
through a 100-Pin dual-ribbon cable connector. Figure 1.1 represents the physical
configuration of the board.
DIGITAL SECTION
ANALOG SECTION
POWER
SECTION
I/O CONNECTOR
Representative illustration. Details may vary.
Figure 1.1. Physical Configuration

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1.2 Functional Overview
A PCI Express interface adapter provides the interface between the controlling bus and the
internal local controller through a 32-bit local bus (Figure 1.2). Inputs are organized into
four channel groups, three of which can be designated as either active or inactive
independently of the other groups. Each input channel consists of configuration switches
for selftest and autocalibration operations, as well as range-scaling and analog image filter
networks. Each even-odd channel pair also contains a dual delta-sigma A/D converter
(ADC) that provides two separate but synchronized conversion channels. An internal
voltage reference can be applied to all channels to support selftest operations and
autocalibration. Gain and offset trimming of the input channels is performed by applying
correction values obtained during autocalibration.
PCI
Conn
I/O
Conn
Analog
Inputs
(32 Diff)
Input
Configuration
Switches
PCI
Interface
Adapter
Local
Controller
Voltage
Reference
To ADC’S
Sample-Rate
Generator
Scaling
& Filters
Input
Data
24-Bit ADC’s
(32)
External
Sync
Input
Control
Local Bus
Figure 1.2. Functional Organization
An internal sample-rate clock generator is adjustable from 20 MHz to 55 MHz, and is
divided down within the local controller to provide sample rates from 2.0 KSPS to
200 KSPS. Input bandwidth varies from 1000 Hz to 80 kHz, depending upon the selected
sample rate, and extends down to DC. Conversion data from all active channels is
transferred to the PCI bus through a 256K-sample FIFO data buffer.
Multiple channels can be synchronized to perform sampling in "lockstep", either by a
software command, or by external hardware sync and clock input signals. Hardware sync
and clock input/output signals permit multiple boards to be connected together for phase-
locked operation from a common clock.

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2-1
SECTION 2.0
INSTALLATION AND MAINTENANCE
2.1 Board Configuration
This product has no field-alterable configuration features, and is completely configured at
the factory for field use.
2.2 Installation
2.2.1 Physical Installation
To minimize the opportunity for accidental damage before installation, the board should be
stored in the original protective shipping envelope. System power must be turned OFF
before proceeding with the installation.
CAUTION:
This product is susceptible to damage from electrostatic discharge (ESD).
Before removing the board from the conductive shipping envelope, ensure
that the work surface, the installer and the host system are adequately
discharged to ground.
Before removing the board from the protective shipping envelope, select an empty PCIe
slot in the host computer and, if a blank panel bracket is located in the slot position, remove
the bracket. Then remove the board from the shipping envelope and position the board
with the panel bracket oriented toward the expansion panel opening. Align the board's
PCIe edge-connector with the mating connector on the motherboard, and carefully press
the board into position. Verify that the PCIe connector has mated completely, and that the
panel bracket is seated against the fastener bracket above the panel opening. To
complete the installation, secure the panel bracket with an appropriate machine or panhead
screw; do not overtighten.
2.2.2 Input/Output Cable Connections
System cable signal pin assignments are listed in Table 2.2.2. Unused input pins may be
left disconnected in most applications. However, if very long cables are used or if
excessive cable noise is anticipated, the unused analog inputs should be grounded to the
input return to minimize the injection of noise into the board.
The system I/O connector is designed to mate with a 100-pin dual-ribbon connector,
equivalent to AMP #749621-9. This insulation displacement (IDC) cable connector
accepts two 50-wire 0.050-inch ribbon cables, with the pin numbering convention shown in
Table 2.2.2 and in Figure 2.2.2.

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Figure 2.2.2: System I/O Connections
Circuit
Board
Connector
Pin 1
Row B Row A
Panel
Bracket
a. I/O Connector
b. System Cable Connector
*50-Conductor Ribbon
Cable; 0.050-in Spacing Panel
Bracket
Pin-1 Wire
Pin-1 Wire
Cable-B * Cable-A *
Cable Connector
Table 2.2.2. System Connector Pin Assignments
ROW-A
ROW-B
PIN
FUNCTION
PIN
FUNCTION
1
CLOCK INPUT LO
1
AUX LVDS INP LO
2
CLOCK INPUT HI
2
AUX LVDS INP HI
3
SYNC INPUT LO
3
DIGITAL RETURN
4
SYNC INPUT HI
4
DIGITAL RETURN
5
DIGITAL RETURN
5
AUX LVDS OUT LO
6
DIGITAL RETURN
6
AUX LVDS OUT HI
7
CLOCK OUTPUT LO
7
INPUT RETURN
8
CLOCK OUTPUT HI
8
INPUT RETURN
9
SYNC OUTPUT LO
9
INPUT CH 16 LO
10
SYNC OUTPUT HI
10
INPUT CH 16 HI
11
INPUT RETURN
11
INPUT CH 17 LO
12
INPUT RETURN
12
INPUT CH 17 HI
13
VTEST RETURN
13
INPUT CH 18 LO
14
VTEST OUTPUT
14
INPUT CH 18 HI
15
INPUT RETURN
15
INPUT RETURN
16
INPUT RETURN
16
INPUT RETURN
17
INPUT CH 00 LO
17
INPUT CH 19 LO
18
INPUT CH 00 HI
18
INPUT CH 19 HI
19
INPUT CH 01 LO
19
INPUT CH 20 LO
20
INPUT CH 01 HI
20
INPUT CH 20 HI
21
INPUT CH 02 LO
21
INPUT CH 21 LO
22
INPUT CH 02 HI
22
INPUT CH 21 HI
23
INPUT CH 03 LO
23
INPUT RETURN
24
INPUT CH 03 HI
24
INPUT RETURN
25
INPUT CH 04 LO
25
INPUT CH 22 LO
26
INPUT CH 04 HI
26
INPUT CH 22 HI
27
INPUT CH 05 LO
27
INPUT CH 23 LO
28
INPUT CH 05 HI
28
INPUT CH 23 HI
29
INPUT CH 06 LO
29
INPUT CH 24 LO
30
INPUT CH 06 HI
30
INPUT CH 24 HI
31
INPUT CH 07 LO
31
INPUT RETURN
32
INPUT CH 07 HI
32
INPUT RETURN
33
INPUT CH 08 LO
33
INPUT CH 25 LO
34
INPUT CH 08 HI
34
INPUT CH 25 HI
35
INPUT CH 09 LO
35
INPUT CH 26 LO
36
INPUT CH 09 HI
36
INPUT CH 26 HI
37
INPUT CH 10 LO
37
INPUT CH 27 LO
38
INPUT CH 10 HI
38
INPUT CH 27 HI
39
INPUT CH 11 LO
39
INPUT RETURN
40
INPUT CH 11 HI
40
INPUT RETURN
41
INPUT CH 12 LO
41
INPUT CH 28 LO
42
INPUT CH 12 HI
42
INPUT CH 28 HI
43
INPUT CH 13 LO
43
INPUT CH 29 LO
44
INPUT CH 13 HI
44
INPUT CH 29 HI
45
INPUT CH 14 LO
45
INPUT CH 30 LO
46
INPUT CH 14 HI
46
INPUT CH 30 HI
47
INPUT CH 15 LO
47
INPUT CH 31 LO
48
INPUT CH 15 HI
48
INPUT CH 31 HI
49
INPUT RETURN
49
INPUT RETURN
50
INPUT RETURN
50
INPUT RETURN

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2.3 Analog Input Configuration
The analog inputs are configured as 32 differential input pairs. Differential operation
provides the highest noise immunity, and is recommended for the majority of applications.
Pull-down resistors are provided on all analog inputs. Although the input configuration is
differential, single-ended signal sources can be accommodated as described in
Paragraph 2.3.2.
2.3.1 Differential Inputs
Differential operation is essential when the input source returns are at different potentials.
This operating mode also offers the highest rejection of the common mode noise that is
characteristic of long unshielded cables. When operating in the differential mode, shown in
Figure 2.3.1a, the wire pair from each signal source is connected between the HI(+) and
LO(-) inputs of a single input channel. The input return should be connected to system
ground (remote common) as closely as possible to the input sources. The average HI/LO
signal level relative to the input return is the common mode voltage Vcm which, for
optimum performance, must not exceed the maximum value indicated in the product
specification.
b. Single-ended Analog Input Source
a. Differential Analog Input
Figure 2.3.1. Input Configurations

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2.3.2 Single-Ended Input Sources
Single-ended signal sources can be accommodated as shown in Figure 2.3.1b, with the
signal line connected to INP CHAN XX HI, and the associated INP CHAN XX LO input
connected to INPUT RETURN at the source. The single-ended operating connection
provides suitable performance only when the input signal sources either are isolated from
each other, or are common only to a single isolated signal return.
CAUTION: If a significant potential difference exists between the remote signal return and
INPUT RETURN, a low impedance between the two returns can cause
excessive current to flow, which in turn can cause erroneous measurements or
possible damage to the board. Return-current should be controlled to less than
a few milliamps for best performance, and to less than 100 milliamps to avoid
damage.
2.4 Multiboard Clocking and Synchronization
Analog input converters on multiple boards can be:
a. Clocked from a single clock source (Multiboard clocking), and/or:
b. Synchronized to a common time reference (Multiboard synchronization).
Clocking multiple converters from a single source prevents the sampling drift that occurs
when converters are clocked from different sources. Synchronizing the converters on
multiple boards causes the converters to initiate conversions simultaneously, and can be
used to eliminate sampling skew between channels.
2.4.1 Interboard Connections
Figure 2.4.1 illustrates how multiple PCIe-24DSI32 boards can be daisy-chained together
in an initiator-target sequence to provide common clocking between boards. The
CLOCK OUTPUT HI/LO lines from an initiator are connected to the CLOCK INPUT HI/LO
lines on a target board, and the SYNC output and input pairs are connected similarly. Each
target board can serve as an initiator for another target board, and multiple boards can be
daisy-chained together for synchronous operation.
Clock
Output
Sync
Output
Initiator Board Target Board
#1
Clock
Input Clock
Output
Sync
Output
Target Board
#2
Clock
Input Clock
Output
Sync
Input Sync
Output
HI/LO Wire Pairs
Additional
Target Boards
Sync
Input
Figure 2.4.1. Multiboard Clock/Sync Connections

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By using an external LVDS distribution module, multiple boards can be interconnected in a
'star' configuration to eliminate the clock and sync propagation delay introduced by each
board in a daisy chain configuration.
The clock output signal is generated internally on an initiator board, or is a duplicate of the
clock input signal on a target board. Similarly, the sync output is the software-generated
sync signal on an initiator board, or a duplicate of the sync input signal on a target board.
Note: External clock and sync inputs can be provided from external sources other than an
initiator board. External clock and sync sources must be LVDS-compatible.
Because each board provides active differential outputs for the next board in the chain, the
number of boards in the chain is limited only if the propagation delay of approximately 10
nanoseconds introduced by each board becomes significant over multiple boards. Cable-
length between boards should be less than one meter for general-purpose ribbon cable,
while high-quality 100-Ohm cable can extend the length to 10 meters or more.
Application software controls the designation of each board as an initiator or a target, and
also selects the channels on each board that will respond to the daisy-chained clock.
Although only software-designated channels respond to the daisy-chained clock, all
channels on all target boards respond to the sync signal.
2.4.2 Multiboard Synchronization
Boards that are daisy-chained together for multiboard synchronization initiate internal
synchronization sequences each time a sync pulse is generated by the initiator board. The
sequence has a duration of approximately 100 milliseconds, after which all synchronized
channels operating from a common clock will sample their inputs simultaneously.
The SYNC I/O line can also be used to reset (clear) the data buffers on target boards.
2.5 Maintenance
This product requires no scheduled hardware maintenance other than periodic reference
verification. The optimum adjustment interval will vary, depending upon the specific
application, but in most instances an interval of one year is recommended. In the event of
a suspected malfunction, all associated system parameters, such as I/O cabling, power
voltages, and control bus integrity should be evaluated before a board is returned to the
factory for problem analysis and repair.
2.6 Reference Verification and Adjustment
All input and output channels are software-calibrated to an internal voltage reference by an
embedded autocalibration software utility. This procedure describes the adjustment of the
internal reference. For applications in which the system must not be powered down, the
adjustment can be performed while the board is installed in an operating system.

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2.6.1 Equipment Required
Table 2.6.1 lists the equipment requirements for calibrating the PCIe-24DSI32 board.
Alternative equivalent equipment may be used.
Table 2.6.1. Reference Adjustment Equipment
EQUIPMENT DESCRIPTION
MANUFACTURER
MODEL
Digital Multimeter, 5-1/2 digit, 0.005%
accuracy for DC voltage measurements at
+10 Volts.
Hewlett Packard
34401A
Host system with PCIe expansion slot
---
---
Cable connector, with test leads. (Not
required if calibration test points are made
permanently available at a system
connection point)
AMP
749621-9
2.6.2 Adjustment Procedure
The following procedure describes the single adjustment that is necessary to ensure
conformance to the product specification. Adjustment of the internal reference (Vtest) is
performed with an internal trimmer that is accessible at the top of the board, as shown in
Figure 2.6.2.
B01
P2
REFERENCE ADJUSTMENT ACCESS
Figure 2.6.2. Reference Adjustment Access

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This procedure assumes that the board is installed in an operating system, and that the
±10V input range is selected.
1.
Connect the digital multimeter between the VTEST OUTPUT (+) and VTEST
RETURN (-) pins in the system I/O connector. Refer to Table 2.2.2 for pin
assignments.
2.
If power has been removed from the board, apply power now and wait at least 15
minutes before proceeding.
3.
Select the ±10V input range.
4.
Verify that the digital multimeter indication is +9.9000 VDC ±0.0009 VDC. If the
indication is not within this range, adjust the REFERENCE ADJUSTMENT trimmer
until the digital multimeter indication is within the specified range.

SECTION 3.0
CONTROL SOFTWARE
3.1 Introduction
The PCIe-24DSI32 board is compatible with the PCI Express local bus specification revision
1.0a, and a PLXtm PEX8311 adapter controls the one-lane interface. Configuration-space
registers are initialized internally to support the location of the board on any 32-longword
boundary in memory space.
After initialization, communication between the PCIe bus and the board takes place through the
control and data registers shown in Table 3.1. All data transfers are long-word D32. Reserved
bits in each register are ignored during write operations, and are forced LOW during read
operations. To ensure compatibility of applications with subsequent product upgrades,
reserved bits should be written as LOW.
Table 3.1. Control and Data Registers
LOCAL
ADDR
ACCESS
MODE
REGISTER
DEFAULT
DESCRIPTION
00
R/W
Board Control (BCR)
0000 383Ch *
Board Control Register (BCR)
04
R/W
Nref PLL Control
0000 01F4h
PLL reference oscillator control integer.
(PLL configuration only)
08
R/W
Nvco PLL Control
(Legacy Nrate)
0000 01F4h
PLL vco control integer.
(Nrate for the legacy rate generator)
0C
R/W
Rate Assignments
0000 0000h ****
ADC Clock source; Group disables.
10
R/W
Rate Divisor
0000 0005h
Sample rate divisor.
14
RO
(Reserved)
0000 0000h
---
18
R/W
PLL Reference Freq
XXXX XXXXh
PLL reference frequency indicator
1C
RO
(Reserved)
0000 0000h
---
20
R/W
Buffer Control
0X03 FFFEh **
Input buffer control and status
24
RO
Board Configuration
00XX XXXXh
Installed firmware and hardware options
28
RO
Buffer Size
0XXX XXXXh
Number of ADC values in the input buffer.
2C
RO
Autocal Values ***
---
---
30
RO (DMA)
Input Data Buffer
XXXX XXXXh
Input Data Buffer; Data and channel tag
34-7C
--
(Reserved)
---
---
* Changes to 0000 783Ch when the input buffer fills.
** Changes to 0103 FFFEh when the buffer fills.
*** Maintenance register. Shown for reference only.
**** May be 0000 0190h in earlier firmware revisions.

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3-2
3.2 Board Control Register
The Board Control Register (BCR) controls primary board functions, including analog input
mode and input range selections, and consists of 32 control bits and status flags (Table 3.2).
Control and monitoring functions of the BCR are described in detail throughout the remainder of
this section. Table 3.2. Board Control Register
Offset: 0000h Default: 0000 383Ch **
DATA BIT
MODE
DESIGNATION
DESCRIPTION
D00
R/W
AIM0
Analog input mode. Selects system inputs or
D01
R/W
AIM1
selftest mode. Defaults to system inputs.
D02
R/W
RANGE0
Analog input range selection. Defaults to ±10V range.
D03
R/W
RANGE1
D04
R/W
OFFSET BINARY
Selects offset binary or two's complement input data
format. Defaults HIGH to offset binary.
D05
R/W
INITIATOR
Selects INITIATOR or TARGET mode for external clock
and sync signals. Defaults HIGH to Initiator mode.
D06
R/W
*SOFTWARE SYNC
Initiates a local ADC sync operation when asserted.
Also generates an external sync output if INITIATOR
mode is selected. Clears automatically.
D07
R/W
*AUTOCAL
Initiates an autocalibration operation when asserted.
Clears automatically upon autocal completion.
D08
R/W
INTERRUPT A0
Interrupt event selection. Default is zero.
D09
R/W
INTERRUPT A1
D10
R/W
INTERRUPT A2
D11
R/W
INTERRUPT REQUEST FLAG
Set HIGH when the board requests an interrupt.
Clears the request when cleared LOW by the bus.
D12
RO
AUTOCAL PASS
Set HIGH at reset or autocal initialization. Cleared
LOW if autocalibration terminates unsuccessfully.
D13
RO
CHANNELS READY
LOW during any change in channel parameters.
Asserted HIGH when inputs are ready to acquire data.
D14
RO
BUFFER THRESHOLD FLAG
Asserted HIGH when buffer contents exceed the
assigned threshold.
D15
R/W
*INITIALIZE
Initializes the board when asserted. Sets all defaults.
D16
R/W
SYNCHRONIZE SCAN
Selects synchronous sampling mode.
D17
R/W
CLEAR BUFFER ON SYNC
When this bit is HIGH, the context of the SOFTWARE
SYNC control bit changes to CLEAR BUFFER.
D18
R/W
RATE GEN EXT CLOCK OUT
(Initiator Mode only)
When HIGH:
Selects the internal rate generator as the external
clock output source.
When LOW:
Selects the Group-00 sample clock. (If Group-00
external clocking is selected, the output is driven by
the internal rate generator and the Group-00
divisor).
D19
R/W
SELECT LOW IMAGE FILTER
When this bit is HIGH, the low-frequency image filter is
selected. When LOW, the high filter is selected.
D20
R/W
(Reserved)
--
D21
R/W
ARM EXTERNAL TRIGGER
Arms the external burst trigger input. (3.12)
D22
R/W
THRESHOLD FLAG OUT
Routes the threshold flag to the AUX LVDS output.
D23-31
RO
(Reserved)
---
* Cleared automatically. R/W = Read/Write; RO = Read-Only.
** Changes to 0000 783Ch when the input buffer fills.

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3.3 Configuration and Initialization
3.3.1 Board Configuration
Board configuration is initiated by a PCIe bus RESET, and should be required only once after
the initial application of power. During board configuration, initial values for both the PCIe
configuration registers and the internal control logic are extracted from internal nonvolatile read-
only memory. While the PCIe configuration registers are being loaded, the response to PCIe
target accesses is RETRY's. Configuration operations are executed in the sequence shown in
Table 3.3.1.
Table 3.3.1. Configuration Operations
Operation
Maximum Duration
PCI configuration registers are loaded from internal EEPROM
3 ms
Internal control logic is configured from internal ROM
300 ms
Internal control logic is initialized
3 ms
A/D converters and clocks are initialized
5 seconds
Board configuration terminates with the PCIe interrupts disabled. Attempts to access the local
bus during configuration should be avoided until the PCIe interrupts are enabled and the
initialization-complete interrupt request is asserted.
3.3.2 Initialization
Internal control logic can be initialized without invoking configuration by setting the INITIALIZE
control bit in the BCR. This action causes the internal logic to be initialized, but does not affect
the PCIe configuration registers and does not reconfigure the internal control logic. Initialization
has a maximum duration of 5 seconds, and produces the following conditions:
The Initiator mode is selected, External clock output is Channel-00 sample clock,
The width of the buffer data field is adjusted to 16 bits,
The internal rate generator is the ADC clock source,
Internal rate generator frequency is 32.768 MHz,
Rate divisor(s) are preset to 5,
Sample rate is 12.8 KSPS; i.e.: 32.768MHz / (512 *5).
The analog input buffer is reset to empty; buffer threshold equals 0003 FFFEh,
Analog inputs are configured for ±10 Volt operation,
All control registers are initialized; all defaults are invoked,
The local interrupt request is asserted as an initialization-completed event.
Upon completion of initialization, the INITIALIZE control bit is cleared automatically.

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3.4 Analog Input Configuration
Configuration of the analog input networks is controlled by the BCR control bits designated as
AIM[1..0], the effects of which are summarized in Table 3.4. The analog input selection
arranges all input channels in differential configuration during normal operation, or invokes one
of two selftest modes.
Table 3.4. Analog Input Function Selection
AIM[..0]
FUNCTION OR MODE
0
Differential analog input mode.
1
(Reserved).
2
ZERO test. Internal ground reference is connected to all analog input channels.
3
+VREF test. Internal voltage reference is connected to all analog input channels.
3.4.1 Selftest Modes
Two selftest modes provide the ability to verify the accuracy of any or all input channels by
replacing the system input connections with either a precision internal reference voltage
(+VREF) or a zero reference (ZERO). The +VREF test produces a positive value equal to
99.00 percent of the selected input range (e.g. +9.900 Volts for the ±10 Volt range) from all
input channels, and the ZERO test should produce a value of 0.000 Volts. The accuracy of
selftest measurements should correspond to the product accuracy specification.
NOTE: For maximum test accuracy, the internal reference voltage must be allowed to
settle completely when the test mode is changed. After selecting either of
these test modes, insert the indicated minimum settling delay before acquiring
test values:
ZERO test: 100 milliseconds,
+VREF test: 3 seconds.
3.4.2 Input Range Selection
Any one of three input voltage ranges can be selected for all channels. RANGE[1..0] control
bits in the BCR select the input range, as shown in Table 3.4.3.
Table 3.4.3. Analog Input Range Selection
RANGE[1..0]
ANALOG INPUT RANGE
0
±2.5 Volts
1
±2.5 Volts
2
±5 Volts
3
±10 Volts

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3.4.3 Settling Delays and the Channels Ready Flag
When a critical parameter such as input mode or sample rate is changed, a settling transition
occurs during which input measurements are unpredictable. A settling delay is inserted
automatically when any or all of these parameters are changed, and the CHANNELS READY
status flag in the BCR goes LOW during the delay. A LOW-to-HIGH transition of this flag is
selectable as an interrupt request "channels ready" event (Section 3.8.1). The CHANNELS
READY flag goes low during the following operations for the approximate intervals indicated:
5 Seconds: Board initialization (3.3),
1 us: Buffer reset, if not in synchronous-scanning mode (3.5.3.2),
10 us-5 ms: Buffer reset, if in synchronous-scanning mode (3.5.3.2),
100 ms: Sample rate change ; i.e.: Nrate, Ndiv, Rate assignments (3.6).
1-100 ms: ADC synchronization (3.6.5 and 3.10),
1-100 ms: Synchronous-scan initiation (3.10),
3.5 Input Data Buffer
3.5.1 General Characteristics
Analog input samples accumulate in the analog input data FIFO data buffer, which has a
capacity of 256K (262,144) data values. Data accumulates in the buffer until extracted by the
PCI bus from a single register location, indicated as INPUT DATA BUFFER in Table 3.1.
Reading an empty buffer returns an indeterminate value.
3.5.2 Data Organization
Each value in the data buffer consists of a 5-bit channel tag field, a zero-pad field, and a data
field, as shown in Table 3.5.2. The width of the right-justified data field is adjustable from 16
bits to 24 bits by the buffer control register (Table 3.5.3), and the width of the zero-pad field is
adjusted accordingly. The zero-pad field becomes a sign-extension field if two's complement
data coding is selected.
Table 3.5.2. Input Data Buffer Organization
Offset: 0000 0030h Default: XXXX XXXXh
SELECTED
DATA WIDTH
RESERVED (Zero)
CHANNEL TAG
ZERO-PAD
CHANNEL DATA VALUE
16 Bits
D[31..29]
D[28..24]
D[23..16]
D[15..0]
18 Bits
D[31..29]
D[28..24]
D[23..18]
D[17..0]
20 Bits
D[31..29]
D[28..24]
D[23..20]
D[19..0]
24 Bits
D[31..29]
D[28..24]
---
D[23..0]
3.5.2.1 Channel Tags
If the input channels are not scan-synchronized (Paragraph 3.10), the order in which channel
data accumulates in the buffer is not generally predictable. Therefore, a channel tag that
identifies each input channel is attached to associated data values in the buffer.
.

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3.5.2.2 Input Data Format
Input data values can be represented either in offset binary format by asserting the OFFSET
BINARY control bit HIGH (default state) in the BCR, or in two's complement format by clearing
the control bit LOW. Both coding conventions are illustrated for 16-Bit data in Table 3.5.2.2.
Table 3.5.2.2. Analog Input Data Coding; 16-Bit Data Field
DIGITAL
VALUE (Hex)
ANALOG INPUT LEVEL
OFFSET BINARY
TWO'S COMPLEMENT
Positive Full Scale minus 1 LSB
FFFFh
7FFFh
Zero plus 1 LSB
8001h
0001h
Zero
8000h
0000h
Zero minus 1 LSB
7FFFh
FFFFh
Negative Full Scale plus 1 LSB
0001h
8001h
Negative Full Scale
0000h
8000h
Positive Full Scale is a positive level that equals the selected input voltage range for the board
(e.g.: +5.000 Volts for the ±5V range). Negative Full Scale is the negative equivalent of
positive full-scale. Full-scale Range (FSR)is the total input voltage range. For 16-Bit data,
one LSB equals the full-scale range divided by 65,536. (e.g.: 152.59 microvolts for the ±5V
range).
3.5.3 Buffer Control Register
The buffer control register (Table 3.5.3) contains the threshold value for the buffer status flag,
and also provides control bits for clearing the buffer and for disabling the buffer input.
Table 3.5.3. Buffer Control Register
Offset: 0000 0020h Default: 0X03 FFFEh *
BIT FIELD
MODE
DESIGNATION
FUNCTION
D[17..00]
R/W
BUFFER THRESHOLD
Buffer Flag Threshold (duplicated in the BCR)
D[18]
R/W
DISABLE BUFFER INPUT
Disables ADC inputs to the buffer
D[19]
R/W
CLEAR BUFFER **
Clears (empties) the buffer
D[21..20]
R/W
DATA WIDTH
Controls the width of the buffer data field as:
0 => 16 bits
1 => 18 bits
2 => 20 bits
3 => 24 bits.
D[23..22]
RO
(Reserved)
---
D[24]
R/W
BUFFER OVERFLOW ***
Reports buffer overflow (Write on full)
D[25]
R/W
BUFFER UNDERFLOW ***
Reports buffer underflow (Read on empty)
D[31..26]
RO
(Reserved)
---
* Changes to 0103 FFFEh when the buffer fills. ** Clears automatically. *** Clear by writing LOW, or by board reset.

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NOTE: Since delta-sigma ADC's perform conversions continuously, the initiation and
termination of acquisition sequences is controlled by the buffer's 'Clear' and
'Disable' controls.
3.5.3.1 Status Flag and Threshold
The amount of data contained in the input buffer can be used to control the BUFFER
THRESHOLD FLAG status bit, which can be selected as an interrupt request event. The
interrupt request event can be selected to occur on either the rising or falling edge of the flag
(Table 3.8.1).
The threshold flag is asserted HIGH when the number of samples in the buffer exceeds the
BUFFER THRESHOLD value in the buffer control register. A buffer-empty event is produced
when the threshold value is adjusted to equal 0000 0000h and the threshold flag undergoes a
HIGH-to-LOW transition.
NOTE: Effective in firmware revision 0502 and subsequent 05XX revisions, the
THRESHOLD FLAG OUT control bit is active in the BCR. When this bit is set
HIGH, the threshold flag is routed to the AUX LVDS OUT output in the system I/O
connector.
3.5.3.2 Buffer Clearing and Disabling
Asserting the CLEAR BUFFER control bit in the buffer control register resets (empties) the
buffer, and holds the buffer in reset until the internal data pipeline clears, approximately 1.0
microsecond. This bit clears automatically.
Asserting the DISABLE BUFFER INPUT control bit disables inputs to the buffer from the ADC
input channels, and halts the accumulation of further input data. Input data already present in
the buffer when this bit is asserted remains in the buffer.
Note: The buffer also can be cleared by writing a "one" to the SOFTWARE SYNC control bit in
the BCR when the CLEAR BUFFER ON SYNC control bit is HIGH. See "Global Buffer
Clear" in Paragraph 3.10.
3.5.4 Buffer Size Register
This read-only register contains the number of analog input values currently stored in the input
data buffer.
3.5.5 Buffer Underflow and Overflow Flags
BUFFER OVERFLOW and BUFFER UNDERFLOW status bits in the buffer control register
report overflow (write on full) or underflow (read on empty) events. Once set, these status bits
remain HIGH until cleared by writing LOW directly, or by a board reset.