General Standards Corporation PCIe-24DSI32 User manual

PCIe-24DSI32
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General Standards Corporation Ph:[phone] FAX:[phone] Email: [email protected]
Rev: 042514
PCIe-24DSI32
24-BIT, 32-CHANNEL DELTA-SIGMA, 200 KSPS
ANALOG INPUT PCIe BOARD
________________________
REFERENCE MANUAL

PCIe-24DSI32
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i
TABLE OF CONTENTS
SECTION
TITLE ___ 
PAGE
1.0
INTRODUCTION
1-1
1.1
General Description
1-1
1.2
Functional Overview
1-2
2.0
INSTALLATION AND MAINTENANCE
2-1
2.1
Board Configuration
2-1
2.2
Installation
2-1
2.2.1
Physical Installation
2-1
2.2.2
Input/Output Cable Connections
2-1
2.3
Analog Input Configuration
2-3
2.3.1
Differential Inputs
2-3
2.3.2
Single-ended Input Sources
2-4
2.4
Multiboard Clocking and Synchronization
2-4
2.4.1
Interboard Connections
2-4
2.4.2
Multiboard Synchronization
2-5
2.5
Maintenance
2-5
2.6
Reference Verification and Adjustment
2-5
2.6.1
Equipment Required
2-6
2.6.2
Adjustment Procedure
2-6
3.0
CONTROL SOFTWARE
3-1
3.1
Introduction
3-1
3.2
Board Control Register
3-2
3.3
Configuration and Initialization
3-3
3.3.1
Board Configuration
3-3
3.3.2
Initialization
3-3
3.4
Analog Input Configuration
3-4
3.4.1
Selftest Modes
3-4
3.4.2
Input Range Selection
3-4
3.4.3
Settling Delays and the Channels Ready Flag
3-5
3.5
Input Data Buffer
3-5
3.5.1
General Characteristics
3-5
3.5.2
Data Organization
3-5
3.5.2.1
Channel Tags
3-5
3.5.2.2
Input Data Format
3-6
3.5.3
Buffer Control Register
3-6
3.5.3.1
Status Flag and Threshold
3-7
3.5.3.2
Buffer Clearing and Disabling
3-7

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ii
TABLE OF CONTENTS (Continued)
SECTION
TITLE 
PAGE
3.5
Input Data Buffer (cont)
---
3.5.4
Buffer Size Register
3-7
3.5.5
Buffer Underflow and Overflow Flags
3-7
3.6
Input Sampling Control
3-8
3.6.1
Sample Rate Control
3-8
3.6.1.1
Rate Clock Organization
3-8
3.6.1.2
Rate Generator Assignment
3-8
3.6.1.3
Sample Clock Generation
3-10
3.6.2
Rate Generator Control
3-11
3.6.2.1
PLL Rate Generator
3-11
3.6.2.2
Legacy Rate Generator
3-14
3.6.3
Direct External Clocking
3-14
3.6.4
Harmonically Locked Channels
3-15
3.6.5
Channel Synchronization
3-15
3.6.6
Multiboard Operation
3-15
3.6.6.1
External Sample Clock
3-15
3.6.6.2
External Sync
3-16
3.7
Autocalibration
3-17
3.8
Interrupt Control
3-17
3.8.1
Local Interrupt Request
3-17
3.8.2
Enabling the PCI Interrupt
3-18
3.9
DMA Operation
3-16
3.9.1
Block Mode
3-16
3.9.2
Demand Mode
3-16
3.10
Scan Synchronization
3-20
3.11
Board Configuration Register
3-22
3.12
External Independent Burst Triggering
3-22
3.13
Settling TIme Considerations
3-23
4.0
PRINCIPLES OF OPERATION
4-1
4.1
General Description
4-1
4.2
Analog Inputs
4-2
4.3
Autocalibration
4-2
4.4
Sampling Clocks
4-2
4.5
Power Control
4-3
Appendix A
Local Register Quick Reference
A-1

PCIe-24DSI32
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iii
LIST OF ILLUSTRATIONS
FIGURE
TITLE 
PAGE
1.1
Physical Configuration
1-1
1.2
Functional Organization
1-2
2.2.2
System I/O Connections
2-2
2.3.1
Input Configurations
2-3
2.4.1
Multiboard Clock/Sync Connections
2-4
2.6.2
Reference Adjustment Access
2-6
3.6.1.1
ADC Clock and Sync Organization, 32 Channels
3-9
4.1
Functional Block Diagram
4-1
LIST OF TABLES
TABLE
TITLE __ 
PAGE
2.2.2
System Connector Pin Assignments
2-2
2.6.1
Reference Adjustment Equipment
2-6
3.1
Control and Data Registers
3-1
3.2
Board Control Register
3-2
3.3.1
Configuration Operations
3-3
3.4
Analog Input Function Selection
3-4
3.4.3
Analog Input Range Selection
3-4
3.5.2
Input Data Buffer Organization
3-5
3.5.2.2
Analog Input Data Coding; 16-Bit Data Field
3-6
3.5.3
Buffer Control Register
3-6
3.6.1.1
Channel Groups
3-9
3.6.1.2-1
Rate Assignments Register
3-10
3.6.1.2-2
Rate Generator Assignment Codes
3-10
3.6.1.3
Rate Divisor Register
3-10
3.6.2.1-1
PLL Nref Register
3-12
3.6.2.1-2
PLL Nvco Register
3-12
3.6.2.1-3
Summary of PLL Sample Rate Control Parameters
3-12
3.6.2.2-1
Legacy Rate Control Register
3-14
3.6.3
Direct External Clocking
3-14
3.8.1
Interrupt Event Selection
3-18
3.9.1
Typical DMA Register Configuration; Block Mode
3-16
3.9.2
Typical DMA Register Configuration; Demand Mode
3-16
3.10.1
Channel Order
3-20
3.11.1
Board Configuration Register
3-22

PCIe-24DSI32
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1-1
SECTION 1.0
INTRODUCTION
1.1 General Description
The PCIe-24DSI32 board provides 24-bit analog input capability for the PCIe bus at sample
rates up to 200 KSPS per channel. In addition to providing 32 analog input channels, this
product supports multiboard clocking and synchronization. The board is functionally and
mechanically compatible with the PCI Express Specification revision 1.0a. Power
requirements consist of +3.3 VDC in accordance with the PCI specification, and operation
over the specified temperature range is achieved with minimal (200 LFPM) air cooling.
Specific details pertaining to physical characteristics and performance are contained in the
PCIe-24DSI32 product specification.
The board is designed for minimum off-line maintenance, and includes internal monitoring
features that eliminate the need for disconnecting or removing the module from the system
for calibration. All system input and output connections are made at the panel bracket
through a 100-Pin dual-ribbon cable connector. Figure 1.1 represents the physical
configuration of the board.
DIGITAL SECTION
ANALOG SECTION
POWER
SECTION
I/O CONNECTOR
Representative illustration. Details may vary.
Figure 1.1. Physical Configuration

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1-2
1.2 Functional Overview
A PCI Express interface adapter provides the interface between the controlling bus and the
internal local controller through a 32-bit local bus (Figure 1.2). Inputs are organized into
four channel groups, three of which can be designated as either active or inactive
independently of the other groups. Each input channel consists of configuration switches
for selftest and autocalibration operations, as well as range-scaling and analog image filter
networks. Each even-odd channel pair also contains a dual delta-sigma A/D converter
(ADC) that provides two separate but synchronized conversion channels. An internal
voltage reference can be applied to all channels to support selftest operations and
autocalibration. Gain and offset trimming of the input channels is performed by applying
correction values obtained during autocalibration.
PCI
Conn
I/O
Conn
Analog
Inputs
(32 Diff)
Input
Configuration
Switches
PCI
Interface
Adapter
Local
Controller
Voltage
Reference
To ADC’S
Sample-Rate
Generator
Scaling
& Filters
Input
Data
24-Bit ADC’s
(32)
External
Sync
Input
Control
Local Bus
Figure 1.2. Functional Organization
An internal sample-rate clock generator is adjustable from 20 MHz to 55 MHz, and is
divided down within the local controller to provide sample rates from 2.0 KSPS to
200 KSPS. Input bandwidth varies from 1000 Hz to 80 kHz, depending upon the selected
sample rate, and extends down to DC. Conversion data from all active channels is
transferred to the PCI bus through a 256K-sample FIFO data buffer.
Multiple channels can be synchronized to perform sampling in "lockstep", either by a
software command, or by external hardware sync and clock input signals. Hardware sync
and clock input/output signals permit multiple boards to be connected together for phase-
locked operation from a common clock.

PCIe-24DSI32
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2-1
SECTION 2.0
INSTALLATION AND MAINTENANCE
2.1 Board Configuration
This product has no field-alterable configuration features, and is completely configured at
the factory for field use.
2.2 Installation
2.2.1 Physical Installation
To minimize the opportunity for accidental damage before installation, the board should be
stored in the original protective shipping envelope. System power must be turned OFF
before proceeding with the installation.
CAUTION:
This product is susceptible to damage from electrostatic discharge (ESD).
Before removing the board from the conductive shipping envelope, ensure
that the work surface, the installer and the host system are adequately
discharged to ground.
Before removing the board from the protective shipping envelope, select an empty PCIe
slot in the host computer and, if a blank panel bracket is located in the slot position, remove
the bracket. Then remove the board from the shipping envelope and position the board
with the panel bracket oriented toward the expansion panel opening. Align the board's
PCIe edge-connector with the mating connector on the motherboard, and carefully press
the board into position. Verify that the PCIe connector has mated completely, and that the
panel bracket is seated against the fastener bracket above the panel opening. To
complete the installation, secure the panel bracket with an appropriate machine or panhead
screw; do not overtighten.
2.2.2 Input/Output Cable Connections
System cable signal pin assignments are listed in Table 2.2.2. Unused input pins may be
left disconnected in most applications. However, if very long cables are used or if
excessive cable noise is anticipated, the unused analog inputs should be grounded to the
input return to minimize the injection of noise into the board.
The system I/O connector is designed to mate with a 100-pin dual-ribbon connector,
equivalent to AMP #749621-9. This insulation displacement (IDC) cable connector
accepts two 50-wire 0.050-inch ribbon cables, with the pin numbering convention shown in
Table 2.2.2 and in Figure 2.2.2.

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2-2
Figure 2.2.2: System I/O Connections
Circuit
Board
Connector
Pin 1
Row B Row A
Panel
Bracket
a. I/O Connector
b. System Cable Connector
*50-Conductor Ribbon
Cable; 0.050-in Spacing Panel
Bracket
Pin-1 Wire
Pin-1 Wire
Cable-B * Cable-A *
Cable Connector
Table 2.2.2. System Connector Pin Assignments
ROW-A
ROW-B
PIN
FUNCTION
PIN
FUNCTION
1
CLOCK INPUT LO
1
AUX LVDS INP LO
2
CLOCK INPUT HI
2
AUX LVDS INP HI
3
SYNC INPUT LO
3
DIGITAL RETURN
4
SYNC INPUT HI
4
DIGITAL RETURN
5
DIGITAL RETURN
5
AUX LVDS OUT LO
6
DIGITAL RETURN
6
AUX LVDS OUT HI
7
CLOCK OUTPUT LO
7
INPUT RETURN
8
CLOCK OUTPUT HI
8
INPUT RETURN
9
SYNC OUTPUT LO
9
INPUT CH 16 LO
10
SYNC OUTPUT HI
10
INPUT CH 16 HI
11
INPUT RETURN
11
INPUT CH 17 LO
12
INPUT RETURN
12
INPUT CH 17 HI
13
VTEST RETURN
13
INPUT CH 18 LO
14
VTEST OUTPUT
14
INPUT CH 18 HI
15
INPUT RETURN
15
INPUT RETURN
16
INPUT RETURN
16
INPUT RETURN
17
INPUT CH 00 LO
17
INPUT CH 19 LO
18
INPUT CH 00 HI
18
INPUT CH 19 HI
19
INPUT CH 01 LO
19
INPUT CH 20 LO
20
INPUT CH 01 HI
20
INPUT CH 20 HI
21
INPUT CH 02 LO
21
INPUT CH 21 LO
22
INPUT CH 02 HI
22
INPUT CH 21 HI
23
INPUT CH 03 LO
23
INPUT RETURN
24
INPUT CH 03 HI
24
INPUT RETURN
25
INPUT CH 04 LO
25
INPUT CH 22 LO
26
INPUT CH 04 HI
26
INPUT CH 22 HI
27
INPUT CH 05 LO
27
INPUT CH 23 LO
28
INPUT CH 05 HI
28
INPUT CH 23 HI
29
INPUT CH 06 LO
29
INPUT CH 24 LO
30
INPUT CH 06 HI
30
INPUT CH 24 HI
31
INPUT CH 07 LO
31
INPUT RETURN
32
INPUT CH 07 HI
32
INPUT RETURN
33
INPUT CH 08 LO
33
INPUT CH 25 LO
34
INPUT CH 08 HI
34
INPUT CH 25 HI
35
INPUT CH 09 LO
35
INPUT CH 26 LO
36
INPUT CH 09 HI
36
INPUT CH 26 HI
37
INPUT CH 10 LO
37
INPUT CH 27 LO
38
INPUT CH 10 HI
38
INPUT CH 27 HI
39
INPUT CH 11 LO
39
INPUT RETURN
40
INPUT CH 11 HI
40
INPUT RETURN
41
INPUT CH 12 LO
41
INPUT CH 28 LO
42
INPUT CH 12 HI
42
INPUT CH 28 HI
43
INPUT CH 13 LO
43
INPUT CH 29 LO
44
INPUT CH 13 HI
44
INPUT CH 29 HI
45
INPUT CH 14 LO
45
INPUT CH 30 LO
46
INPUT CH 14 HI
46
INPUT CH 30 HI
47
INPUT CH 15 LO
47
INPUT CH 31 LO
48
INPUT CH 15 HI
48
INPUT CH 31 HI
49
INPUT RETURN
49
INPUT RETURN
50
INPUT RETURN
50
INPUT RETURN

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2-3
2.3 Analog Input Configuration
The analog inputs are configured as 32 differential input pairs. Differential operation
provides the highest noise immunity, and is recommended for the majority of applications.
Pull-down resistors are provided on all analog inputs. Although the input configuration is
differential, single-ended signal sources can be accommodated as described in
Paragraph 2.3.2.
2.3.1 Differential Inputs
Differential operation is essential when the input source returns are at different potentials.
This operating mode also offers the highest rejection of the common mode noise that is
characteristic of long unshielded cables. When operating in the differential mode, shown in
Figure 2.3.1a, the wire pair from each signal source is connected between the HI(+) and
LO(-) inputs of a single input channel. The input return should be connected to system
ground (remote common) as closely as possible to the input sources. The average HI/LO
signal level relative to the input return is the common mode voltage Vcm which, for
optimum performance, must not exceed the maximum value indicated in the product
specification.
b. Single-ended Analog Input Source
a. Differential Analog Input
Figure 2.3.1. Input Configurations

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2-4
2.3.2 Single-Ended Input Sources
Single-ended signal sources can be accommodated as shown in Figure 2.3.1b, with the
signal line connected to INP CHAN XX HI, and the associated INP CHAN XX LO input
connected to INPUT RETURN at the source. The single-ended operating connection
provides suitable performance only when the input signal sources either are isolated from
each other, or are common only to a single isolated signal return.
CAUTION: If a significant potential difference exists between the remote signal return and
INPUT RETURN, a low impedance between the two returns can cause
excessive current to flow, which in turn can cause erroneous measurements or
possible damage to the board. Return-current should be controlled to less than
a few milliamps for best performance, and to less than 100 milliamps to avoid
damage.
2.4 Multiboard Clocking and Synchronization
Analog input converters on multiple boards can be:
a. Clocked from a single clock source (Multiboard clocking), and/or:
b. Synchronized to a common time reference (Multiboard synchronization).
Clocking multiple converters from a single source prevents the sampling drift that occurs
when converters are clocked from different sources. Synchronizing the converters on
multiple boards causes the converters to initiate conversions simultaneously, and can be
used to eliminate sampling skew between channels.
2.4.1 Interboard Connections
Figure 2.4.1 illustrates how multiple PCIe-24DSI32 boards can be daisy-chained together
in an initiator-target sequence to provide common clocking between boards. The
CLOCK OUTPUT HI/LO lines from an initiator are connected to the CLOCK INPUT HI/LO
lines on a target board, and the SYNC output and input pairs are connected similarly. Each
target board can serve as an initiator for another target board, and multiple boards can be
daisy-chained together for synchronous operation.
Clock
Output
Sync
Output
Initiator Board Target Board
#1
Clock
Input Clock
Output
Sync
Output
Target Board
#2
Clock
Input Clock
Output
Sync
Input Sync
Output
HI/LO Wire Pairs
Additional
Target Boards
Sync
Input
Figure 2.4.1. Multiboard Clock/Sync Connections