causing the SCR to fire and a current puLse to flow in the wire. The wire
Passes through the toroids of those flip-flops which must be cleared. The
pulse induces a negative-going secondary vottage large enough to drive the
flip-flop clear input to zero and to reset the ftip-flop. The binary code
corresponding to the characterrs pattern of dots and dashes is thus loaded
into the shift register.
As an example of how the shift register works, consider the transmission of
the letter rrRrr (dot-dash-dot). The wire from the R keyswitch to the SCR
Passes through the toroids connected to flip-flops FFO, FF2, and FF3. When
the keyswitch is closed momentarily, these flip-flops are cleared and their
outputs go to the zero state. A11 of the other flip-flops remain in the high
state, 8s shown in Figure 4,La.
The R keyswitch clears flip-flop FFO so that its output is tow, since it will
produce the first dot. It does not affect the second ftip-flop, FFl, because
the second character will be a dash. However, it ctears the third flip-flop,
FF2, to produce the final dot, The fourth flip-flop, FF3, is also reset to
produce a space at the end of the character, as will be explained later.
After the flip-flops are set to the proper states, the clock oscillator
starts and the character generator produces its first output pulse. Since
the output of the shift register is low, the pulse is short: a dot, At the
end of the dot, the state of each flip-flop shifts one stage to the right.
FFO is now in the high state, FF1 and FF2 are in the low state, and the
remainder are in the high state. Since the data input to FF6 is tied to the
+5 volt bus, this flip-flop remains in the high state. The register contents
are now as shown in Figure 4.Lb. When the next clock pulse occurs, the high
leve1 at the register output results in the production of a dash, and the
register contents again shift one stage to the right.
Each time the register contents shift, a trlrr is again read into FF6, and
the former rrlrr code is transferred to the next stage. After the second dot
has been sent, the register stages are therefore all set high except FFO.
This last zero output would normally produce a dot during the next clock
pu1se. A special gate, however, prevents the dot from being transmitted.
The inputs of TC7, which forms a NOR gate, i." connected. to the inverted
outputs of the register stages. !,lith all of its inputs low, the NOR gate
output bus witl be high. This signal is fed through an inverter to the
input of a NAND gate (pin 13 of IC5) in the character generator, driving it
1ow. The NAND gate output therefore must remain high regardless of the
character generator output state. Although the character generator produces
a dot, the gate prevents its output from reaching the keying transistor and
sidetone oscillator. This feature provides an intercharacter space between
the completion of one letter and the beginning of the next one.
Clock Oscillator
Timing for the keyboard circuits is provided by the clock oscillator, which
consists of an operational amplifier (IC2), a monostable multivibrator (IC3),
two transistors, a triming capacitor, and the speed control.
